CN110429936A - A kind of phase locking loop controlling method and its system based on DSP - Google Patents
A kind of phase locking loop controlling method and its system based on DSP Download PDFInfo
- Publication number
- CN110429936A CN110429936A CN201910568977.6A CN201910568977A CN110429936A CN 110429936 A CN110429936 A CN 110429936A CN 201910568977 A CN201910568977 A CN 201910568977A CN 110429936 A CN110429936 A CN 110429936A
- Authority
- CN
- China
- Prior art keywords
- phase
- voltage
- frequency
- signal
- dsp
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 32
- 238000005070 sampling Methods 0.000 claims abstract description 10
- 238000012545 processing Methods 0.000 claims abstract description 9
- 238000006243 chemical reaction Methods 0.000 claims abstract description 8
- 102100027241 Adenylyl cyclase-associated protein 1 Human genes 0.000 claims description 26
- 108010077333 CAP1-6D Proteins 0.000 claims description 26
- 108010031970 prostasin Proteins 0.000 claims description 26
- 238000001514 detection method Methods 0.000 claims description 15
- 238000004458 analytical method Methods 0.000 claims description 12
- 238000007405 data analysis Methods 0.000 claims description 11
- 230000004048 modification Effects 0.000 claims description 8
- 238000012986 modification Methods 0.000 claims description 8
- 230000000630 rising effect Effects 0.000 claims description 8
- 230000008859 change Effects 0.000 claims description 4
- 238000004364 calculation method Methods 0.000 claims description 3
- 238000001228 spectrum Methods 0.000 claims description 3
- 238000007689 inspection Methods 0.000 claims description 2
- 239000003550 marker Substances 0.000 claims description 2
- 238000001914 filtration Methods 0.000 claims 1
- 238000012544 monitoring process Methods 0.000 claims 1
- 238000013461 design Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 230000004044 response Effects 0.000 description 2
- 241000208340 Araliaceae Species 0.000 description 1
- 235000005035 Panax pseudoginseng ssp. pseudoginseng Nutrition 0.000 description 1
- 235000003140 Panax quinquefolius Nutrition 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000001186 cumulative effect Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 235000008434 ginseng Nutrition 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000000737 periodic effect Effects 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/087—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using at least two phase detectors or a frequency and phase detector in the loop
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/091—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector using a sampling device
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/093—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Abstract
Present invention discloses a kind of phase locking loop controlling method based on DSP, step 1 obtains synchronization signal by the voltage over zero for sampling power grid；The method of step 2, the period by changing timer or maximum loop counter value changes the frequency and phase of synchronization signal；Step 3 carries out A/D conversion and data processing to voltage, obtains the phase and frequency of fundamental wave and harmonic voltage；Step 4, adjustment SPWM sine table pointer address complete the locking phase to fundamental wave and harmonic voltage.The present invention realizes the tracking and locking to power grid fundamental wave and specific subharmonic voltage phase using digital processing unit dsp chip, helps to simplify circuit structure, guarantees phase locked looped function reliability of operation.
Description
Technical field
The present invention relates to dsp software PHASE-LOCKED LOOP PLL TECHNIQUEs.
Background technique
The accurate phase angle for obtaining power grid fundamental wave and harmonic voltage, in power electronic equipments such as frequency converter, active filters
In have great importance, it usually needs be achieved using phaselocked loop.Conventional phase-lock loop circuit is generally filtered by phase discriminator, loop
Wave device, voltage controlled oscillator and frequency divider composition, its working principle is that same by network voltage and inside the control system by phase discriminator
The phase difference of step signal is transformed into voltage signal, voltage controlled oscillator is controlled after loop filter filters, to change in system
The frequency and phase of portion's synchronization signal, are allowed to consistent with network voltage.That there are hardware circuits is complicated for conventional phase locked loops, vulnerable to environment
The problems such as interference and locking phase precision be not high.
Summary of the invention
The technical problem to be solved by the present invention is to realize that a kind of use digital processing unit dsp chip is realized to power grid fundamental wave
And the phase lock control system of tracking and the locking of specific subharmonic voltage phase.
To achieve the goals above, a kind of the technical solution adopted by the present invention are as follows: phase locking loop controlling method based on DSP:
Step 1 obtains synchronization signal by the voltage over zero for sampling power grid；
The method of step 2, the period by changing timer or maximum loop counter value changes the frequency of synchronization signal
And phase；
Step 3 carries out A/D conversion and data processing to voltage, obtains the phase and frequency of fundamental wave and harmonic voltage；
Step 4, adjustment SPWM sine table pointer address complete the locking phase to fundamental wave and harmonic voltage.
In the step 1, zero cross detection circuit acquires the zero passage in each period of any phase voltage in power grid three-phase voltage
The interrupt signal CAP1 that point is generated as system, makes interrupt service routine start to execute, and opens the TIMER of task manager EVA
Cycle interruption, period are set as staying T/128s, trigger A/D module samples, wherein T is two zero passage detections that CAP1 is captured
The interval time of signal rising edge, equal to the cycle T of power grid measured signal.
The method of the interval time of rising edge is captured in the step 1: the capturing unit CAP of DSP is under the jurisdiction of incident management
Device obtains the jump of zero cross detection circuit CAP external pin, and when capturing corresponding pin generation specifically jump, triggering is corresponding
Interruption, and the value of timer is stored in the FIFO storehouse of two-stage depth, reading FIFO heap stack marker ctrl and flag bit
Dft indicates ctrl to detect whether to enter the new update cycle, then starts the analysis of new round data and throwing when reaching set point number
Control amount out.It indicates to reinitialize data analysis operation when flag bit dft is 0, indicates data when flag bit dft is 1
End of operation is analyzed, indicates to allow to start the analysis of new round data when flag bit dft is 2, be indicated when flag bit dft is 3
Currently carrying out data analysis.
Software filtering is used in the step 1 to judge that CAP1 signal whether for burr interference, judgment method: works as generation
It when CAP1 is interrupted, calculates this and interrupts the count difference value with previous interruption, if much smaller than power grid fundamental frequency fluctuation power frequency week
Phase count difference value, then it is assumed that the interruption of capture is that interference generates, and occurs more than twice as the interruption is discontinuous, then interrupts return,
Add up simultaneously to the interruption times of generation, when reaching setting range to the pointer position of voltage zero-cross moment sine table into
Row judgement adjusts sinusoidal table pointer address, realized the calibration of nil pointer.
In the step 2, zero cross signal is capturing input voltage signal zero crossing after software filtering and calibration
When, directly the pointer for sending out sinusoidal signal is zeroed, guarantees the reference synchronization zero passage that DSP is issued when input voltage signal zero passage, it is real
Existing Phase synchronization.
In the step 2, voltage zero-crossing signal is sent into pin CAP1, as the benchmark in a sampling period, the period
128 frequency-doubled signals start benchmark as each ADC.
The calculation method of fundamental wave and harmonic voltage phase frequency and phase in the step 3:
In formula: a, f0、The respectively amplitude, frequency and initial phase angle of signal；
Above-mentioned signal is sampled, record time span is T, and total sampling number is N, sample sequence is divided into two long
Spend identical sequence, s1(t) corresponding preceding N/2 point, sample sequence are as follows:
s2(t) N/2 point after corresponding to, sample sequence are as follows:
s2(n)=s1(n)*exp(j2πf0T)
To s1(t) and s2(t) DFT analysis is carried out, discrete spectrum is obtained:
s2(k)=s1(k)*exp(jπf0T)
In formula: Ak、Respectively s1(k) amplitude and phase；
As the A in formulakWhen being maximum value, corresponding discrete frequency is k0=f0T/2；
Frequency is fk=k0Δ f, works as fk=f0When, Δ f=2/T, Δ f is the maximum resolution of frequency at this time；
In formula: N is carrier wave ratio；frFor modulated signal；fHFor timer frequency；X is timing cycle.
In the step 4, locking phase output is interrupted by capture and timer interruption is completed jointly, and electricity can be completed by capturing to interrupt
The calculating in period and phase is pressed, timer interruption is used to export SPWM waveform.
The step 4 generates triangular carrier using the continuous increase and decrease count mode of general purpose timer, when general purpose timer has
It after effect, starts counting up, the value until being equal to period register, timer starts countdown, when being decremented to zero, opens again
Beginning incremental count, and above procedure is repeated, triangle carrier signal is formed, after obtaining triangular wave, is controlled by comparing unit defeated
The polarity of wave out generates PWM wave；
Value by reading the first phase angular frequency of fundamental wave and harmonic voltage in register and with zero crossing phase difference, adjustment
Corresponding sine table initial phase angle pointer address, changes the frequency of sine wave, modification by modification timer period register
Comparand register changes the amplitude and phase of sine wave, launches phase and frequency control in next zero cross signal zero crossing
Amount completes PGC demodulation when exporting to fundamental wave and harmonic voltage and SPWM.
A kind of phase lock control system based on DSP, zero cross detection circuit acquisition are equipped with comparator chip opo7 and compare
Device chip LM339, comparator chip opo7 input terminal acquire a certain phase signals of network voltage, the output end of comparator chip opo7
The pin CAP1 of DSP2812 task manager EVA is connected, the input terminal of the comparator chip LM339 is by resistance R7 and R8 structure
At hysteresis loop comparator, the phase lock control system executes the phase locking loop controlling method.
The present invention realized using digital processing unit dsp chip to the tracking of power grid fundamental wave and specific subharmonic voltage phase and
Locking helps to simplify circuit structure, guarantees phase locked looped function reliability of operation.
Detailed description of the invention
The content of width attached drawing every in description of the invention expression is briefly described below:
Fig. 1 is the work flow diagram of invention software locking phase；
Fig. 2 is zero cross detection circuit figure of the present invention；
Fig. 3 is interrupt routine flow chart of the present invention；
Fig. 4 is the software flow pattern of capturing unit of the present invention；
Fig. 5 is synchronization zero-cross signal waveforms of the present invention；
Fig. 6 is that power module locking phase of the present invention exports experimental waveform figure.
Specific embodiment
Below against attached drawing, by the description of the embodiment, for example related each component of a specific embodiment of the invention
Shape, construction, the mutual alignment between each section and connection relationship, the effect of each section and working principle, manufacturing process and
Operate with method etc., is described in further detail, to help those skilled in the art to inventive concept of the invention, technology
Scheme has more complete, accurate and deep understanding.
With the development of large scale integrated circuit and digital signal processor, by using programming devices such as high-speed dsps,
The major function of phaselocked loop is realized by software programming.Software phase-lock loop control system of the invention uses digital processing unit
Dsp chip realizes the tracking and locking to power grid fundamental wave and specific subharmonic voltage phase.
The basic ideas of software phase-lock loop design scheme based on DSP are that synchronous letter is obtained by sampled voltage zero crossing
Number, synchronization signal is generated using the cycle count of DSP timer internal to realize the function of voltage controlled oscillator and frequency divider, that is, is led to
The method in the period or maximum loop counter value that change timer is crossed to change the frequency and phase of synchronization signal, while to voltage
A/D conversion and data processing are carried out, obtains the phase and frequency of fundamental wave and harmonic voltage, adjusts SPWM sine table pointer address
Complete the phase-locked function to fundamental wave and harmonic voltage.
In general, zero cross signal can be obtained by the zero crossing of any phase in detection power grid three-phase voltage.In practical solution,
To detect A phase voltage zero crossing as zero cross signal, using by rising edge capture and software filtering after the interruption that generates as adopting
Sample periodic sync signals, the interruption generated after DSP internal clocking frequency multiplication are capturing input voltage signal in zero crossing, will
Send out the pointer zero of sinusoidal signal, the reference sinusoidal signal also synchronization zero-cross that DSP is issued when guaranteeing input voltage signal zero passage,
To realize Phase synchronization.The present invention triggers mode using SPWM, and reference sinusoidal signal is a sinusoidal data form, controls inverse
Become the datum mark of device output；Sampled voltage signal simultaneously carries out FFT calculating through DSP and analyzes its phase and frequency, fundamental wave and harmonic wave
With A phase voltage zero crossing phase difference, the frequency of sine wave when changing SPWM output by modification timer period register；With
Modification comparand register completes the phase lock to fundamental wave and harmonic voltage come the phase of sine wave when changing SPWM output in this way
It is fixed.
1) zero cross signal:
Zero cross signal can be obtained by the zero crossing of any phase in detection power grid three-phase voltage.In practical solution, with inspection
A phase voltage zero crossing is surveyed as zero cross signal.
2) zero cross detection circuit:
The accuracy that zero cross signal captures system phase is affected, using the method for software and hardware combining when system designs
Realize the capture to zero cross signal.Obtaining zero cross signal is substantially to believe every time to provide a system to a synchronization signal
Starting A/D conversion when number zero passage.In the present invention, the zero crossing in zero cross detection circuit acquisition A phase voltage each period is as system
Unite the interrupt signal CAP1 generated, and interrupt service routine is made to start to execute, and Fig. 2 is voltage signal zero cross detection circuit.In Fig. 2,
Comparator chip LM339 output end selection installed pull-up resistor additional, mainly in view of entire circuit to driving, power consumption and
The requirement of speed.Resistance R7 and R8 constitute a hysteresis loop comparator, and output signal changes the ginseng of in-phase end by feedback resistance R7
Voltage is examined, to eliminate the shake that the positive and negative zero passage of input signal generates.
3) zero passage interrupt routine:
Zero passage detection master is to solve sample-synchronous problem, when the voltage signal detected is by bearing positive zero passage, than
Rising edge is generated compared with device chip LM339 output end, this signal is input to the pin CAP1 of DSP2812 task manager EVA.Draw
Foot CAP1 is preset in system initialization routine is set to rising edge triggering interruption, therefore when zero cross signal arrives, CAP1 is interrupted
Subprogram starts to execute, and opens the TIMER cycle interruption of task manager EVA, and the period is set as staying T/128s (each cycle sampling
128 points), trigger A/D module samples.Wherein, when T is the interval for two zero passage detection signal rising edges that CAP1 is captured
Between, equal to the cycle T of power grid measured signal, Fig. 3 is the flow chart of zero passage interrupt routine.
4) capturing unit program:
The capturing unit CAP of DSP is under the jurisdiction of task manager, can capture the jump of CAP external pin, when capturing
It when specific jump occurs for corresponding pin, triggers and interrupts accordingly, and the value of timer is stored in the FIFO heap of a two-stage depth
In stack.A present invention data analysis of every 16 points of startings, while a control amount is launched, this process is a update cycle,
Judgement symbol ctrl is used to detect whether to enter the new update cycle, to judge whether to need to start the analysis of new round data and throw
Control amount out.Flag bit dft is used to judge current data analysis state, indicates to reinitialize data analysis operation when being 0, be
It indicates that data analysis operation finishes when 1, indicates to allow to start the analysis of a new round data when being 2, indicate currently carrying out when being 3
Data analysis.Fig. 4 gives the software flow pattern of capturing unit.
5) software filtering of zero cross signal:
The interval time for two zero cross signal rising edges that CAP1 is captured, i.e., when the interval of two CAP1 interrupt events
Between, equal to the cycle T of power grid measured signal.TIMER is constantly counted after system initialization, then services journey in the interruption of CAP1
The TIMER count value N between two CAP1 interrupt events is recorded in sequence, can calculate T.Meanwhile being judged using software filtering
Whether CAP1 signal is burr interference, and process is as follows: the fluctuation of power grid fundamental frequency is usually no more than according to 0.2Hz, works as generation
When CAP1 is interrupted, this and previous count difference value can be calculated, if being much smaller than power frequency period count difference value, then it is assumed that capture
Interruption be interference generate, occur more than twice as the interruption is discontinuous, then interrupt return.Simultaneously to the interruption times of generation into
Row is cumulative, judges when reaching setting range the pointer position of voltage zero-cross moment sine table, adjusts sinusoidal table and refers to
The calibration of nil pointer was realized in needle address.
6) A/D is converted:
Zero cross signal is after software filtering and calibration, when capturing input voltage signal zero crossing, will directly send out just
The pointer of string signal is zeroed, and guarantees the reference synchronization zero passage that DSP is issued when input voltage signal zero passage, to realize that phase is same
Step.A phase voltage zero cross signal is sent into pin CAP1, as the benchmark in a sampling period, the 128 frequency-doubled signal conducts in the period
Each ADC starts benchmark.CAP1 is opened after system initialization, and be arranged starting ADC, corresponding analog-to-digital conversion, data analysis,
Control amount such as launches at the operation, until shutting down or breaking down.It is 150MHz since the system clock frequency of F2812 is very high,
That is the response time of interrupt service routine is very small, can ignore.In the interrupt service routine of CAP1, according to letter to be measured
Number cycle T is arranged the general purpose timer TIMER of F2812 task manager, starts an A/D conversion automatically every staying T/128s
Carry out data acquisition.
7) phase frequency analysis:
Signal after A/D conversion uses the fft algorithm of sliding window, using the DFT of sliding window and Pruning-FFT as base
Plinth carries out selection calculating to specific subharmonic using DFT, is quickly counted according to sliding window quick response and Pruning-FFT
The characteristics of calculation, makes the processing speed of DSP reach ideal value.The principle for carrying out phase and frequency analysis using FFT is as follows:
In formula: a, f0、The respectively amplitude, frequency and initial phase angle of signal.
Above-mentioned signal is sampled, record time span is T, and total sampling number is N, sample sequence is divided into two long
Spend identical sequence, s1(t) corresponding preceding N/2 point, sample sequence are as follows:
s2(t) N/2 point after corresponding to, sample sequence are as follows:
To s1(t) and s2(t) DFT analysis is carried out, discrete spectrum is obtained:
In formula: Ak、Respectively s1(k) amplitude and phase.
A in formula (6)kWhen being maximum value, corresponding discrete frequency is k0=f0T/2；Frequency is fk=k0Δ f, works as fk
=f0When, Δ f=2/T, Δ f is the maximum resolution of frequency at this time.
In formula: N is carrier wave ratio；frFor modulated signal；fHFor timer frequency；X is timing cycle.
To a certain single-frequency signals, initial phase angle, frequency are obtained by above-mentioned analysis, data are stored in corresponding register
In, complete the phase frequency computing function of fundamental wave and harmonic wave.
8) the phase frequency adjustment of PWM output
Software phlase locking output is to be interrupted to complete jointly with timer interruption by capture, and voltage cycle can be completed by capturing to interrupt
With the calculating of phase, timer interruption is used to export SPWM waveform.In invention, triangular carrier is the company using general purpose timer
What continuous increase and decrease count mode generated, it after general purpose timer is effective, starts counting up, the value until being equal to period register,
Timer starts countdown, when being decremented to zero, restarts incremental count, and repeat above procedure, to form triangle load
Wave signal.After obtaining triangular wave, the polarity of output wave is controlled by comparing unit, generates PWM wave.
Value by reading the first phase angular frequency of fundamental wave and harmonic voltage in register and with zero crossing phase difference, adjustment
Corresponding sine table initial phase angle pointer address, changes the frequency of sine wave, modification by modification timer period register
Comparand register changes the amplitude and phase of sine wave, launches phase and frequency control in next zero cross signal zero crossing
Amount, PGC demodulation when can be completed to fundamental wave and the output of harmonic voltage and SPWM.
The present invention is exemplarily described above in conjunction with attached drawing, it is clear that the present invention implements not by aforesaid way
Limitation, as long as the improvement for the various unsubstantialities that the inventive concept and technical scheme of the present invention carry out is used, or without changing
It is within the scope of the present invention into the conception and technical scheme of the invention are directly applied to other occasions.
Claims (10)
1. a kind of phase locking loop controlling method based on DSP, it is characterised in that:
Step 1 obtains synchronization signal by the voltage over zero for sampling power grid；
The method of step 2, the period by changing timer or maximum loop counter value changes the frequency and phase of synchronization signal
Position；
Step 3 carries out A/D conversion and data processing to voltage, obtains the phase and frequency of fundamental wave and harmonic voltage；
Step 4, adjustment SPWM sine table pointer address complete the locking phase to fundamental wave and harmonic voltage.
2. according to claim 1 based on the phase locking loop controlling method of DSP, it is characterised in that: in the step 1, zero passage inspection
The interrupt signal that the zero crossing in each period of any phase voltage is generated as system in slowdown monitoring circuit acquisition power grid three-phase voltage
CAP1 makes interrupt service routine start to execute, and opens the TIMER cycle interruption of task manager EVA, and the period is set as staying T/
128s triggers A/D module samples, wherein and T is the interval time for two zero passage detection signal rising edges that CAP1 is captured, etc.
In the cycle T of power grid measured signal.
3. according to claim 2 based on the phase locking loop controlling method of DSP, it is characterised in that: capture and rise in the step 1
The method of the interval time on edge: the capturing unit CAP of DSP is under the jurisdiction of outside task manager acquisition zero cross detection circuit CAP and draws
The jump of foot, when capturing corresponding pin specific jump occurring, trigger it is corresponding interrupt, and the value of timer is stored in one
In the FIFO storehouse of a two-stage depth, FIFO heap stack marker ctrl and flag bit dft is read, it is new to detect whether to enter to indicate ctrl
Update cycle, then start the analysis of new round data when reaching set point number and launch control amount.The table when flag bit dft is 0
Show and reinitialize data analysis operation, indicate that data analysis operation is finished when flag bit dft is 1, when flag bit dft is 2
When indicate to allow to start the analysis of new round data, indicate currently is carrying out data analysis when flag bit dft is 3.
4. according to claim 3 based on the phase locking loop controlling method of DSP, it is characterised in that: use software in the step 1
Filtering come judge CAP1 signal whether be burr interference, judgment method: when generate CAP1 interrupt when, calculate this interrupt with it is previous
The count difference value of interruption, if fluctuating power frequency period count difference value much smaller than power grid fundamental frequency, then it is assumed that the interruption of capture is
Interference generates, and occurs more than twice as the interruption is discontinuous, then interrupts return, while adding up to the interruption times of generation,
The pointer position of voltage zero-cross moment sine table is judged when reaching setting range, adjusts sinusoidal table pointer address,
Realized the calibration of nil pointer.
5. according to claim 1 based on the phase locking loop controlling method of DSP, it is characterised in that: in the step 2, zero passage letter
Number after software filtering and calibration, when capturing input voltage signal zero crossing, directly the pointer for sending out sinusoidal signal is returned
Zero, guarantee the reference synchronization zero passage that DSP is issued when input voltage signal zero passage, realizes Phase synchronization.
6. according to claim 5 based on the phase locking loop controlling method of DSP, it is characterised in that: in the step 2, voltage mistake
Zero-signal is sent into pin CAP1, and as the benchmark in a sampling period, 128 frequency-doubled signals in the period start as each ADC
Benchmark.
7. according to claim 1 based on the phase locking loop controlling method of DSP, it is characterised in that: fundamental wave and humorous in the step 3
The calculation method of wave voltage phase frequency and phase:
In formula: a, f0、The respectively amplitude, frequency and initial phase angle of signal；
Above-mentioned signal is sampled, record time span is T, and total sampling number is N, and sample sequence is divided into two length phases
Same sequence, s1(t) corresponding preceding N/2 point, sample sequence are as follows:
s2(t) N/2 point after corresponding to, sample sequence are as follows:
s2(n)=s1(n)*exp(j2πf0T)
To s1(t) and s2(t) DFT analysis is carried out, discrete spectrum is obtained:
s2(k)=s1(k)*exp(jπf0T)
In formula: Ak、Respectively s1(k) amplitude and phase；
As the A in formulakWhen being maximum value, corresponding discrete frequency is k0=f0T/2；
Frequency is fk=k0Δ f, works as fk=f0When, Δ f=2/T, Δ f is the maximum resolution of frequency at this time；
In formula: N is carrier wave ratio；frFor modulated signal；fHFor timer frequency；X is timing cycle.
8. according to claim 7 based on the phase locking loop controlling method of DSP, it is characterised in that: in the step 4, locking phase is defeated
It is interrupted out by capture and timer interruption is completed jointly, capture the calculating interrupted and can complete voltage cycle and phase, timer
It interrupts and is used to export SPWM waveform.
9. according to claim 8 based on the phase locking loop controlling method of DSP, it is characterised in that: the step 4, utilization are general
The continuous increase and decrease count mode of timer generates triangular carrier and starts counting up after general purpose timer is effective, until being equal to
The value of period register, timer start countdown, when being decremented to zero, restart incremental count, and repeat above procedure,
Triangle carrier signal is formed, after obtaining triangular wave, the polarity of output wave is controlled by comparing unit, generates PWM wave；
Value by reading the first phase angular frequency of fundamental wave and harmonic voltage in register and with zero crossing phase difference, adjustment correspond to
Sinusoidal table initial phase angle pointer address, change the frequency of sine wave by modification timer period register, modification is compared
Register changes the amplitude and phase of sine wave, launches phase and frequency control amount in next zero cross signal zero crossing, complete
PGC demodulation when pairs of fundamental wave and harmonic voltage and SPWM export.
10. a kind of phase lock control system based on DSP, it is characterised in that: zero cross detection circuit acquisition is equipped with comparator chip
Opo7 and comparator chip LM339, comparator chip opo7 input terminal acquire a certain phase signals of network voltage, comparator chip
Opo7 output end connection DSP2812 task manager EVA pin CAP1, the comparator chip LM339 input terminal by
Resistance R7 and R8 constitute hysteresis loop comparator, and the phase lock control system executes the phaselocked loop as described in any in claim 1-9
Control method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910568977.6A CN110429936A (en) | 2019-06-27 | 2019-06-27 | A kind of phase locking loop controlling method and its system based on DSP |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910568977.6A CN110429936A (en) | 2019-06-27 | 2019-06-27 | A kind of phase locking loop controlling method and its system based on DSP |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN110429936A true CN110429936A (en) | 2019-11-08 |
Family
ID=68409779
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910568977.6A Pending CN110429936A (en) | 2019-06-27 | 2019-06-27 | A kind of phase locking loop controlling method and its system based on DSP |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN110429936A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111404543A (en) * | 2020-05-27 | 2020-07-10 | 深圳市汇顶科技股份有限公司 | Clock data recovery circuit, processing chip and electronic equipment |
| CN111654361A (en) * | 2020-04-16 | 2020-09-11 | 株洲航飞翔数字系统有限责任公司 | Method and system for dual-channel synchronization |
| CN112152955A (en) * | 2020-09-24 | 2020-12-29 | 无锡华润矽科微电子有限公司 | Method for realizing FSK decoding based on wireless charging system |
| CN115825560A (en) * | 2023-02-17 | 2023-03-21 | 青岛鼎信通讯股份有限公司 | Intelligent low-voltage power grid phase checking device and method based on frequency tracking technology |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB1247240A (en) * | 1969-02-07 | 1971-09-22 | Amalgamated Wireless Australas | Improvements in or relating to phase measuring and monitoring circuits |
| CN101777912A (en) * | 2010-01-15 | 2010-07-14 | 浙江大学 | Method for realizing software phase-locked loop with unfixed sampling frequency |
| JP2012159334A (en) * | 2011-01-31 | 2012-08-23 | Meidensha Corp | Phase detection device and method of sinusoidal signal |
| CN103995181A (en) * | 2014-05-13 | 2014-08-20 | 武汉中元华电科技股份有限公司 | Method for analyzing electric energy quality harmonic waves of digital substation |
| CN106452120A (en) * | 2016-12-02 | 2017-02-22 | 四川英杰电气股份有限公司 | Phase-locking synchronous compensation processing method and system |
| WO2017211060A1 (en) * | 2016-06-08 | 2017-12-14 | 江苏现代电力科技股份有限公司 | High-precision phase locking method for intelligent integrated low-pressure reactive power module |
| CN109709390A (en) * | 2018-12-19 | 2019-05-03 | 深圳市中电电力技术股份有限公司 | A kind of three-phase high-precision harmonic electric energy meter |
-
2019
- 2019-06-27 CN CN201910568977.6A patent/CN110429936A/en active Pending
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB1247240A (en) * | 1969-02-07 | 1971-09-22 | Amalgamated Wireless Australas | Improvements in or relating to phase measuring and monitoring circuits |
| CN101777912A (en) * | 2010-01-15 | 2010-07-14 | 浙江大学 | Method for realizing software phase-locked loop with unfixed sampling frequency |
| JP2012159334A (en) * | 2011-01-31 | 2012-08-23 | Meidensha Corp | Phase detection device and method of sinusoidal signal |
| CN103995181A (en) * | 2014-05-13 | 2014-08-20 | 武汉中元华电科技股份有限公司 | Method for analyzing electric energy quality harmonic waves of digital substation |
| WO2017211060A1 (en) * | 2016-06-08 | 2017-12-14 | 江苏现代电力科技股份有限公司 | High-precision phase locking method for intelligent integrated low-pressure reactive power module |
| CN106452120A (en) * | 2016-12-02 | 2017-02-22 | 四川英杰电气股份有限公司 | Phase-locking synchronous compensation processing method and system |
| CN109709390A (en) * | 2018-12-19 | 2019-05-03 | 深圳市中电电力技术股份有限公司 | A kind of three-phase high-precision harmonic electric energy meter |
Non-Patent Citations (2)
| Title |
|---|
| 洪君等，DENGFAQI1980上传: "《豆丁网》", 9 May 2016 * |
| 纪飞峰等: "应用数字信号处理器的基波相位和频率校正检测方法", 《电网技术》 * |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111654361A (en) * | 2020-04-16 | 2020-09-11 | 株洲航飞翔数字系统有限责任公司 | Method and system for dual-channel synchronization |
| CN111654361B (en) * | 2020-04-16 | 2023-03-24 | 株洲航飞翔数字系统有限责任公司 | Method and system for dual-channel synchronization |
| CN111404543A (en) * | 2020-05-27 | 2020-07-10 | 深圳市汇顶科技股份有限公司 | Clock data recovery circuit, processing chip and electronic equipment |
| CN111404543B (en) * | 2020-05-27 | 2020-09-15 | 深圳市汇顶科技股份有限公司 | Clock data recovery circuit, processing chip and electronic equipment |
| CN112152955A (en) * | 2020-09-24 | 2020-12-29 | 无锡华润矽科微电子有限公司 | Method for realizing FSK decoding based on wireless charging system |
| CN115825560A (en) * | 2023-02-17 | 2023-03-21 | 青岛鼎信通讯股份有限公司 | Intelligent low-voltage power grid phase checking device and method based on frequency tracking technology |
| CN115825560B (en) * | 2023-02-17 | 2023-05-23 | 青岛鼎信通讯股份有限公司 | Intelligent phase checking method of electric power network based on frequency tracking technology |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN110429936A (en) | A kind of phase locking loop controlling method and its system based on DSP | |
| CN105549379B (en) | A kind of synchronous measuring apparatus triggered based on split-second precision benchmark and method | |
| US7646225B2 (en) | Mains phase detection apparatus | |
| CN102045062B (en) | Digital phase-locked loop based on Cordic algorithm | |
| CN104090151A (en) | Zero-crossing-point accurate detection method for AC power-grid voltage signals | |
| CN109412582A (en) | A kind of pwm signal sample detecting circuit, processing circuit and chip | |
| CN105699738A (en) | PWM-based AC signal effective value measurement method | |
| CN109283354A (en) | A kind of change M/T speed-measuring method based on incremental optical-electricity encoder | |
| CN105629061A (en) | Precise frequency measurement device based on high-stability wide reference pulse | |
| CN106645780A (en) | Rotating speed detection method and system base on DSP | |
| Yamaguchi et al. | Extraction of peak-to-peak and RMS sinusoidal jitter using an analytic signal method | |
| CN209170340U (en) | Pwm signal sample detecting circuit, processing circuit and chip | |
| CN102508029A (en) | Phase angle tracking method for power grid | |
| KR20160114070A (en) | Digital period divider | |
| CN214895514U (en) | PWM control sequential sampling period transient frequency measuring circuit | |
| CN107271772B (en) | A kind of mains frequency rapid detection method of high-precision and anti-noise jamming | |
| US6856924B2 (en) | Mixer-based timebase for sampling multiple input signal references asynchronous to each other | |
| CN202453691U (en) | Equally spaced sampling circuit for different-frequency signals | |
| JP2001141853A (en) | Time-interval counter device | |
| US6700516B1 (en) | Mixer-based timebase for signal sampling | |
| CN209231361U (en) | Speed detector, processing circuit and chip based on pwm signal | |
| CN102832931A (en) | Phase demodulation method, phase demodulation device and phase-locked loop based on incomplete period grid voltage signal | |
| CN205249184U (en) | Frequency synthesizer | |
| CN106597092A (en) | High-precision anti-interference fixed-point computer three-phase voltage frequency measurement phase-locking algorithm | |
| EP2110644B1 (en) | Phase difference detector and rotational position detector |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |