CN111654361B - Method and system for dual-channel synchronization - Google Patents
Method and system for dual-channel synchronization Download PDFInfo
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- CN111654361B CN111654361B CN202010297478.0A CN202010297478A CN111654361B CN 111654361 B CN111654361 B CN 111654361B CN 202010297478 A CN202010297478 A CN 202010297478A CN 111654361 B CN111654361 B CN 111654361B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/0016—Arrangements for synchronising receiver with transmitter correction of synchronization errors
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/22—Arrangements for detecting or preventing errors in the information received using redundant apparatus to increase reliability
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/0008—Synchronisation information channels, e.g. clock distribution lines
Abstract
The invention discloses a method for double-channel synchronization, wherein the double channels comprise a main channel and a backup channel, and the double-channel synchronization comprises main channel synchronization and backup channel synchronization; the main channel and the backup channel mutually send and receive the synchronizing signal of the other side, so as to judge whether the main channel and the backup channel are in a synchronizing state, further control the interruption of the timer and realize the synchronization between the main channel and the backup channel. The invention also provides a system for dual-channel synchronization. The method for the double-channel synchronization has the advantages that the double channels can quickly realize synchronization under the condition of step loss, the accumulation of synchronization errors is avoided, the step loss probability is reduced, and the effective synchronous communication of the double channels is realized under different states of a power supply system.
Description
Technical Field
The invention belongs to the technical field of control of aero-engines, and particularly relates to a method and a system for double-channel synchronization.
Background
At present, a system (such as an electronic controller of an aero-engine) with high safety and real-time performance often has a redundant dual-channel structure, wherein one channel works as a main control channel, and the other channel works as a backup channel. When the main control channel breaks down, the system automatically switches the channels. During switching, synchronization should be maintained between the two channels in order to minimize system fluctuations. In addition, data exchange also exists between the two channels, and in order to ensure that the data sampling time is the same, the two channels also need to be kept synchronous. The commonly used dual-channel synchronization method at the present stage has the defects of large time deviation of timing interruption, possibility of permanent step loss and the like. Therefore, how to control the dual channels to achieve synchronization better has become a technical problem to be solved by those skilled in the art.
Disclosure of Invention
Aiming at the defects, the invention provides a method and a system for double-channel synchronization, which can quickly realize synchronization of double channels under the condition of step-out, avoid synchronization error accumulation, reduce the step-out probability and effectively realize synchronization of the double channels under the isolation state of a power system.
In order to achieve the purpose, the invention provides the following technical scheme: a method and system for dual channel synchronization, the dual channel includes main channel and backup channel, the dual channel synchronization includes main channel synchronization and backup channel synchronization;
the method for synchronizing the main channel comprises the following steps:
step S10, initializing the main channel;
s11, the main channel processor sets a first interrupt period of main channel timer interrupt;
step S12, judging whether the main channel timer interrupt is generated or not;
step S13, if the timer of the main channel generates the timer interrupt, outputting a high level to a main channel differential sending unit, and marking the position of a main channel to be 0;
step S14, a main channel differential receiving unit receives the signal output by the backup channel differential sending unit in a first detection time, and if the output signal of the backup channel differential sending unit is detected to be high level, the main channel is marked at position 1;
step S15, after the first detection time is over, outputting a signal output by the main channel differential sending unit to a low level, and receiving a signal output by the backup channel differential sending unit by the main channel differential receiving unit;
step S16, when the flag bit of the main channel is 1, immediately setting the interrupt period of the main channel timer as the difference value between the first interrupt period and the first detection time after detecting that the output signal of the backup channel differential transmission unit is at a low level, and starting the main channel timer; when the main channel flag bit is 0, immediately setting the interrupt period of the main channel timer as the difference value between the first interrupt period and the first detection time, and starting the main channel timer;
the method for synchronizing the backup channels comprises the following steps:
step S20, initializing the backup channel;
step S21, the backup channel processor sets a second interrupt period for the interrupt of the backup channel timer;
step S22, judging whether the backup channel timer interrupt is generated or not;
step S23, if the backup channel timer generates timer interruption, outputting a high level to a backup channel differential sending unit, and marking the position of a backup channel to be 0;
step S24, a backup channel differential receiving unit receives the signal output by the main channel differential sending unit in a second detection time, and if the output signal of the main channel differential sending unit is detected to be high level, the backup channel is marked at position 1;
step S25, after the second detection time is over, outputting a signal output by the backup channel differential transmitting unit to a low level, and receiving a signal output by the main channel differential transmitting unit by the backup channel differential receiving unit;
step S26, when the flag bit of the backup channel is 1, immediately setting the interrupt period of the backup channel timer as the difference value between the second interrupt period and the second detection time after detecting that the output signal of the main channel differential transmission unit is low level, and starting the backup channel timer; and when the backup channel flag bit is 0, delaying the second detection time, setting the interrupt period of the backup channel timer to be the difference value between the second interrupt period and the second detection time, and starting the backup channel timer.
Preferably, the first interrupt cycle and the second interrupt cycle are the same, and the first detection time and the second detection time are the same.
Preferably, the first detection time is shorter than the first interrupt period, and the second detection time is shorter than the second interrupt period.
Preferably, the initialization of the main channel and the backup channel is performed simultaneously.
A system for dual channel synchronization, a dual channel comprising a primary channel and a backup channel; the main channel comprises
The main channel differential transmitting unit is used for transmitting a synchronous signal to the backup channel;
the main channel differential receiving unit is used for receiving the synchronous signal of the backup channel;
the main channel processor is used for setting the state of a main channel flag bit according to the synchronization signal received by the main channel differential receiving unit, setting the interrupt period of a main channel timer according to the synchronization signal received by the main channel differential receiving unit and the state of the main channel flag bit, and controlling the main channel differential sending unit to send the synchronization signal to the backup channel;
the backup channel comprises
The backup channel differential sending unit is used for sending a synchronous signal to the main channel;
the backup channel differential receiving unit is used for receiving the synchronous signal of the main channel;
and the backup channel processor is used for setting the state of a backup channel zone bit according to the synchronous signal received by the backup channel differential receiving unit, setting the interrupt period of a backup channel timer according to the state of the synchronous signal received by the backup channel differential receiving unit and the state of the backup channel zone bit, and controlling the backup channel differential sending unit to send the synchronous signal to the main channel.
Compared with the prior art, the invention has the following beneficial effects:
the invention detects whether the main channel and the backup channel are in a synchronous state by adopting a mode of mutually sending and receiving synchronous signals for the main channel and the backup channel in the double channels and marking by using the channel zone bits, and when the main channel and the backup channel are detected not to be in the synchronous state, the main channel and the backup channel are periodically adjusted at the same time, thereby realizing the quick synchronization of the main channel and the backup channel; synchronous signals are mutually sent and received through the main channel and the backup channel, a mode of mutual detection of the two channels is realized, synchronous errors can be timely and automatically eliminated, synchronous error accumulation is avoided, and the out-of-step probability is reduced; by adopting the mode of the differential receiving unit and the differential sending unit for the main channel and the backup channel, only two paths of signals are needed for synchronous control between the channels, one path is used for synchronous signal sending, and the other path is used for synchronous signal receiving, so that the system has a simple structure; the differential receiving unit and the differential sending unit adopt a differential mode to transmit the synchronous signals, and synchronous communication of the two channels under different states of the power supply system can be realized.
Drawings
FIG. 1 is a block schematic diagram of a system for dual channel synchronization according to the present invention.
FIG. 2 is a flow chart illustrating main channel synchronization according to the present invention.
FIG. 3 is a flow chart illustrating backup channel synchronization according to the present invention.
Fig. 4 is a schematic structural diagram of a system for dual channel synchronization according to the present invention.
FIG. 5 is a diagram illustrating the main channel adjusting to the synchronous state after lagging the backup channel according to the present invention.
FIG. 6 is a diagram illustrating the backup channel adjusting to the synchronous state when lagging behind the primary channel according to the present invention.
FIG. 7 is a diagram illustrating the main channel adjusting to the synchronous state when the backup channel is out of synchronization.
FIG. 8 is a diagram illustrating the backup tunnels being adjusted to a synchronous state when the primary tunnel is out of sync.
In the figure: 1. a main channel; 2. backing up a channel; 11. a main channel processor; 12. a main channel differential transmission unit; 13. a main channel differential receiving unit; 21. a backup channel processor; 22. a main channel differential transmission unit; 23. a main channel differential receiving unit.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The technical solutions of the embodiments of the present invention can be combined, and the technical features of the embodiments can also be combined to form a new technical solution.
Referring to fig. 1 to 8, the present invention provides the following technical solutions: a method and system for dual channel synchronization, dual channel including a primary channel 100 and a backup channel 200, dual channel synchronization including primary channel synchronization and backup channel synchronization;
the method for synchronizing the main channel comprises the following steps:
step S10, initializing the main channel 100;
step S11, the main channel processor 101 sets a first interrupt period of the main channel timer interrupt;
step S12, judging whether the main channel timer interrupt is generated or not;
step S13, if the main channel timer generates timer interruption, the main channel differential sending unit 102 outputs high level, and the main channel mark position is 0;
step S14, the main channel differential receiving unit 103 receives the signal output by the backup channel differential transmitting unit 202 within a first detection time, and if it is detected that the signal output by the backup channel differential transmitting unit 202 is at a high level, marks the main channel at position 1;
step S15, after the first detection time is over, outputting a signal output by the main channel differential transmission unit 102 to a low level, and receiving a signal output by the backup channel differential transmission unit 202 by the main channel differential reception unit 103;
step S16, when the flag bit of the main channel is 1, immediately setting the interrupt period of the main channel timer as the difference between the first interrupt period and the first detection time after detecting that the output signal of the backup channel differential transmission unit 202 is at the low level, and starting the main channel timer; when the main channel flag bit is 0, immediately setting the interrupt period of the main channel timer as the difference value between the first interrupt period and the first detection time, and starting the main channel timer;
the method for synchronizing the backup channels comprises the following steps:
step S20, initializing the backup channel 200;
step S21, the backup tunnel processor 201 sets a second interrupt period for the backup tunnel timer to interrupt;
step S22, judging whether the backup channel timer interrupt is generated or not;
step S23, if the backup channel timer generates a timer interrupt, outputting a high level from the backup channel differential transmission unit 202, and marking the position of the backup channel as 0;
step S24, the backup channel differential receiving unit 203 receives the signal output by the main channel differential transmitting unit 102 within a second detection time, and if the output signal of the main channel differential transmitting unit 102 is detected to be a high level, the backup channel flag is set to 1;
step S25, after the second detection time is over, outputting a signal output by the backup channel differential transmission unit 202 to a low level, and receiving a signal output by the main channel differential transmission unit 102 by the backup channel differential receiving unit 203;
step S26, when the backup channel flag bit is 1, immediately setting the interrupt period of the backup channel timer as the difference between the second interrupt period and the second detection time after detecting that the output signal of the main channel differential transmission unit 102 is at a low level, and starting the backup channel timer; and when the backup channel flag bit is 0, delaying the second detection time, setting the interrupt period of the backup channel timer to be the difference value between the second interrupt period and the second detection time, and starting the backup channel timer.
The first interrupt period is the same as the second interrupt period, and the first detection time is the same as the second detection time. The same time is set for the first interrupt period and the second interrupt period, and the same time is set for the first detection time and the second detection time, so that the main channel and the backup channel are ensured to be in the same working state after initialization, and the synchronous communication after initialization is facilitated; when the main channel and the backup channel are out of synchronization, the main channel and the backup channel can be mutually and quickly detected, so that the interruption period is adjusted, and the synchronous state is quickly restored.
The first detection time is less than the first interrupt period, and the second detection time is less than the second interrupt period.
The initialization of the main channel and the backup channel is performed simultaneously.
A system for dual channel synchronization, a dual channel comprising a primary channel 100 and a backup channel 200; the main channel 100 comprises
A main channel differential transmitting unit 102, configured to transmit a synchronization signal to the backup channel 200;
a main channel differential receiving unit 103, configured to receive a synchronization signal of the backup channel 200;
a main channel processor 101, configured to set a state of a flag bit of a backup channel according to the synchronization signal received by the main channel differential receiving unit 103, set an interrupt period of a main channel timer according to the synchronization signal received by the main channel differential receiving unit 103 and the state of the flag bit of the main channel, and control the main channel differential transmitting unit 102 to transmit the synchronization signal to the backup channel 200;
the backup tunnel 200 includes
A backup channel differential transmitting unit 202, configured to transmit a synchronization signal to the main channel 100;
a backup channel differential receiving unit 203, configured to receive a synchronization signal of the main channel 100;
the backup channel processor 201 is configured to set a state of a flag bit of a main channel according to the synchronization signal received by the backup channel differential receiving unit 203, set an interrupt period of a backup channel timer according to the state of the synchronization signal and the flag bit of the backup channel received by the backup channel differential receiving unit 203, and control the backup channel differential transmitting unit 202 to transmit the synchronization signal to the main channel 100.
The main channel processor 101 and the backup channel processor 201 interrupt control task circulation through a control timer.
After the main channel processor 101 and the backup channel processor 201 are synchronized, the interrupt period of the timer interrupt of the main channel processor 101 is the difference between the first interrupt period and the first detection time, or the interrupt period of the timer interrupt is adjusted to the first interrupt period after synchronization, the interrupt period of the timer interrupt of the backup channel processor 201 is the difference between the second interrupt period and the second detection time, or the interrupt period of the timer interrupt is adjusted to the second interrupt period after synchronization.
Example 1:
the working principle of the invention is as follows:
it is to be noted that the names and meanings used herein are as follows:
a first interrupt period, which refers to a timer interrupt period (denoted by Ts in the figure) set after the main channel 100 is initialized;
a second interrupt period, which refers to a timer interrupt period (denoted by Ts in the figure) set after the backup channel 200 is initialized;
a first detection time (denoted by Δ T1 in the figure) when the main channel 100 enters the timer interrupt and the main channel differential receiving unit 103 receives the synchronization signal sent by the backup channel differential sending unit 202;
a second detection time (denoted by Δ T1 in the figure) when the backup channel 200 enters the timer interrupt and then receives the synchronization signal transmitted by the primary channel differential transmitting unit 102 by using the backup channel differential receiving unit 203;
a first time period, which refers to the time that the primary channel 100 lags behind the backup channel 200, the lag time being less than or equal to the second detection time (identified by Δ T2 in the figure);
a second time period, which is the time that the backup tunnel 200 lags behind the primary tunnel 100, the lagged time being less than or equal to the first detection time (identified by Δ T2 in the figure);
a third time period, which is the time that the primary channel 100 lags behind the backup channel 200, the lag time being greater than the second detection time (identified by Δ T2 in the figure);
a fourth time period, which is the time that the backup channel 200 lags behind the primary channel 100, the lagged time being greater than the first detection time (identified by Δ T2 in the figure);
as shown in fig. 5, when the main channel 100 lags behind the backup channel 200, the main channel 100 lags behind the backup channel 200 for a first time period (denoted by Δ T2 in the figure), the first time period is less than or equal to a second detection time (denoted by Δ T1 in the figure), that is, Δ T2 ≦ Δ T1, a time difference between the main channel 100 and the backup channel 200 is less than a control period tolerance (Δ T1), the backup channel 200 starts a timer to interrupt first, and the backup channel processor 201 outputs a high level to the backup channel difference sending unit 202, sets a backup channel flag to 0, and enters the second detection time (Δ T1); in the second detection time (Δ T1), the main channel 100 starts a timer interrupt, and the main channel processor 101 outputs a high level to the main channel differential transmission unit 102, and the main channel flag position is 0, and enters the first detection time;
in the second detection time of the backup channel 200, the backup channel differential receiving unit 203 detects that the output signal of the main channel differential transmitting unit 102 is at a high level, and marks the backup channel at position 1; after the second detection time is over, outputting a low level of the output signal of the backup channel differential transmitting unit 202, and after the backup channel differential receiving unit 203 receives the low level output by the main channel differential transmitting unit 102, immediately setting the interrupt period of the backup channel timer as the difference value between the second interrupt period and the second detection time and starting the backup channel timer;
in the first detection time of the main channel 100, the main channel differential receiving unit 103 detects that the output signal of the backup channel differential transmitting unit 202 is at a high level, and marks the main channel at position 1; after the first detection time is over, outputting a low level of an output signal of the main channel differential sending unit 102, immediately setting an interrupt period of a main channel timer as a difference value between a first interrupt period and the first detection time after the main channel differential receiving unit 103 receives the low level output by the backup channel differential sending unit 202, and starting the backup channel timer; because the first interrupt cycle is the same as the second interrupt cycle, and the first detection time is the same as the second detection time, the main channel 100 and the backup channel 200 reach the interrupt at the same time in the next interrupt cycle, thereby realizing the automatic elimination of the synchronization error.
As shown in fig. 6, when the backup tunnel 200 lags behind the main tunnel 100, the backup tunnel 200 lags behind the main tunnel 100 by a second time period (denoted by Δ T2 in the figure), where the second time period is less than or equal to the first detection time (denoted by Δ T1 in the figure), i.e., Δ T2 ≦ Δ T1, a time difference between the main tunnel 100 and the backup tunnel 200 is less than the control cycle tolerance (Δ T1), the main tunnel 100 starts a timer to interrupt first, and the main tunnel processor 101 outputs a high level to the main tunnel differential transmission unit 102, and enters the first detection time (Δ T1) at a main tunnel flag position 0; within the first detection time (Δ T1), the backup tunnel 200 starts a timer interrupt, and the backup tunnel processor 201 outputs a high level to the backup tunnel differential transmission unit 202, where the backup tunnel flag position is 0, and enters the second detection time;
in the first detection time of the main channel 100, the main channel differential receiving unit 103 detects that the output signal of the backup channel differential sending unit 202 is at a high level, and marks the main channel with a position 1; after the first detection time is over, outputting a low level of an output signal of the main channel differential sending unit 102, immediately setting an interrupt period of a main channel timer as a difference value between a first interrupt period and the first detection time after the main channel differential receiving unit 103 receives the low level output by the backup channel differential sending unit 202, and starting the main channel timer;
in the second detection time of the backup channel 200, the backup channel differential receiving unit 203 detects that the output signal of the main channel differential transmitting unit 102 is at a high level, and marks the backup channel at position 1; after the second detection time is over, outputting a low level of the output signal of the backup channel differential transmitting unit 202, immediately setting the interrupt period of the backup channel timer as the difference value between the second interrupt period and the second detection time after the backup channel differential receiving unit 203 receives the low level output by the main channel differential transmitting unit 102, and starting the backup channel timer; because the first interrupt cycle and the second interrupt cycle are the same, and the first detection time and the second detection time are the same, the main channel 100 and the backup channel 200 reach the interrupt at the same time in the next interrupt cycle, and the automatic elimination of the synchronization error is realized.
As shown in fig. 7, in a state where the time that the main channel 100 lags the backup channel 200 is greater than the second detection time, the main channel 100 lags the backup channel 200 for a third time period (denoted by Δ T2 in the figure), when the synchronization error of the main channel and the backup channel is large and exceeds the allowable range, the state is generally called that the main channel and the backup channel are out of synchronization, the third time period is greater than the second detection time (denoted by Δ T1 in the figure), that is, Δ T2> Δ T1, the time difference between the main channel 100 and the backup channel 200 is greater than the control period allowable error (Δ T1), the backup channel 200 starts a timer interrupt first, the backup channel processor 201 outputs a high level to the backup channel differential transmitting unit 202, and the backup channel flag position is 0, and the backup channel enters the second detection time (Δ T1); in the second detection time (Δ T1), the main channel 100 does not start the timer interrupt, and the main channel processor 101 outputs the main channel differential transmission unit 102 with a low level;
in the second detection time of the backup channel 200, the backup channel differential receiving unit 203 detects that the output signal of the main channel differential transmitting unit 102 is low level and the backup channel flag position is 0; after the second detection time is finished, outputting a signal output by the backup channel differential sending unit 202 to a low level, receiving the low level output by the main channel differential sending unit 102 by the backup channel differential receiving unit 203, delaying the second detection time, immediately setting an interrupt period of the backup channel timer to be a difference value between the second interrupt period and the second detection time, and starting the backup channel timer;
the main channel 100 starts the main channel timer interruption after the backup channel 200 timer interruption is completed, and the main channel differential receiving unit 103 detects that the output signal of the backup channel differential sending unit 202 is low level and the main channel mark position is 0 within the first detection time of the main channel 100; after the first detection time is over, outputting a low level by the output signal of the main channel differential sending unit 102, receiving the low level output by the backup channel differential sending unit 202 by the main channel differential receiving unit 103, immediately setting the interrupt period of the main channel timer as the difference value between the first interrupt period and the first detection time, and starting the main channel timer; the intervals of the interrupt periods of the start timers between the main channel 100 and the backup channel 200 are different, after a period of time, the main channel 100 lags behind the backup channel 200 for a third time period (marked by Δ T2 in the figure), the third time period is less than a second detection time (marked by Δ T1 in the figure), namely Δ T2< Δ T1, so that the state that the main channel 100 lags behind the backup channel 200 is entered, and it can be known through calculation that after the time of Δ T2/Δ T1 Ts, the automatic elimination of the synchronization error is realized, and the clock synchronization is realized.
As shown in fig. 8, in a state where the backup channel 200 lags behind the main channel 100 for a time greater than the first detection time, the backup channel 200 lags behind the main channel 10 for a fourth time period (denoted by Δ T2 in the figure), the fourth time period is greater than the first detection time (denoted by Δ T1 in the figure), i.e., Δ T2> Δ T1, a time difference between the main channel 100 and the backup channel 200 is greater than a control cycle tolerance (Δ T1), the main channel 100 starts a timer to interrupt first, the main channel processor 101 outputs a high level to the main channel differential transmission unit 102, and the main channel flag position is 0 to enter the first detection time (Δ T1); within the first detection time (Δ T1), the backup tunnel 200 does not start the timer interrupt, and the backup tunnel processor 201 outputs a low level to the backup tunnel differential transmission unit 202;
in the first detection time of the main channel 200, the main channel differential receiving unit 103 detects that the output signal of the backup channel differential sending unit 202 is low level, and the main channel flag position is 0; after the first detection time is over, outputting a low level by the output signal of the main channel differential sending unit 102, receiving the low level output by the backup channel differential sending unit 202 by the main channel differential receiving unit 103, immediately setting the interrupt period of the main channel timer as the difference value between the first interrupt period and the first detection time, and starting the main channel timer;
the backup channel 200 starts the timer interrupt of the backup channel after the timer interrupt of the main channel 100 is completed, and the backup channel differential receiving unit 203 detects that the output signal of the main channel differential transmitting unit 102 is at a low level and the backup channel mark position is 0 within a second detection time of the backup channel 200; after the second detection time is finished, outputting a signal output by the backup channel differential transmitting unit 202 to a low level, receiving the low level output by the main channel differential transmitting unit 102 by the backup channel differential receiving unit 203, delaying the second detection time, immediately setting the interrupt period of the backup channel timer to be the difference value between the second interrupt period and the second detection time, and starting the backup channel timer; the intervals of the interrupt periods of the start timers between the main channel 100 and the backup channel 200 are different, after a period of time elapses, the backup channel 200 lags behind the main channel 100 for a fourth time period (denoted by Δ T2 in the figure), which is less than a first detection time (denoted by Δ T1 in the figure), i.e., Δ T2< Δ T1, thereby entering a state where the backup channel 100 lags behind the main channel 200, and it can be known through calculation that after the time Δ T2/Δ T1 Ts elapses, the automatic elimination of the synchronization error is realized, and the clock synchronization is realized.
The main channel 100 and the backup channel receiving and transmitting unit 203 and the backup channel differential transmitting unit 202 in the backup channel 200 transmit and receive synchronization signals in a differential manner through the main channel differential transmitting unit 102 and the main channel differential receiving unit 103, and judge whether the main channel 100 and the backup channel 200 are in a synchronous state by marking with a channel flag bit, when the main channel 100 and the backup channel 200 are in an asynchronous state, the interrupt cycle of respective channel timer interrupt is controlled by adjusting the main channel processor 101 and the backup channel processor 201, so that the main channel 100 and the backup channel 200 can be quickly synchronized; the synchronous signals are sent and received in a differential mode, so that synchronous communication of the main channel and the backup channel can be realized under different states of a power system (two sets of power supplies which are isolated from each other supply power), and the anti-jamming capability and the stability of the system are improved. If the power systems of the two channels are not isolated, the signal lines may not be differentially connected, but directly connected. When the interruption starts, the synchronous signal output firstly outputs low level instead of high level.
Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that changes, modifications, substitutions and alterations can be made in these embodiments without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.
Claims (5)
1. A method for dual channel synchronization, characterized by: the dual channels comprise a main channel and a backup channel, and the dual channel synchronization comprises main channel synchronization and backup channel synchronization;
the method for synchronizing the main channel comprises the following steps:
step S10, initializing the main channel;
step S11, the main channel processor sets a first interrupt period of main channel timer interrupt;
step S12, judging whether the main channel timer interrupt is generated or not;
step S13, if the timer of the main channel generates the timer interrupt, outputting a high level to a main channel differential sending unit, and marking the position of a main channel to be 0;
step S14, a main channel differential receiving unit receives the signal output by the backup channel differential sending unit in a first detection time, and if the output signal of the backup channel differential sending unit is detected to be high level, the main channel is marked at position 1;
step S15, after the first detection time is over, outputting a signal output by the main channel differential sending unit to a low level, and receiving a signal output by the backup channel differential sending unit by the main channel differential receiving unit;
step S16, when the flag bit of the main channel is 1, immediately setting the interrupt period of the main channel timer as the difference value between the first interrupt period and the first detection time after detecting that the output signal of the backup channel differential transmission unit is at a low level, and starting the main channel timer; when the main channel flag bit is 0, immediately setting the interrupt period of the main channel timer as the difference value between the first interrupt period and the first detection time, and starting the main channel timer;
the method for synchronizing the backup channels comprises the following steps:
step S20, initializing the backup channel;
step S21, the backup channel processor sets a second interrupt period for the interrupt of the backup channel timer;
step S22, judging whether the backup channel timer interrupt is generated or not;
step S23, if the backup channel timer generates timer interruption, outputting a high level to a backup channel differential transmission unit, and marking the position of a backup channel to be 0;
step S24, a backup channel differential receiving unit receives the signal output by the main channel differential sending unit in a second detection time, and marks the backup channel at position 1 if the output signal of the main channel differential sending unit is detected to be high level;
step S25, after the second detection time is over, outputting a signal output by the backup channel differential transmitting unit to a low level, and receiving a signal output by the main channel differential transmitting unit by the backup channel differential receiving unit;
step S26, when the flag bit of the backup channel is 1, immediately setting the interrupt period of the backup channel timer as the difference value between the second interrupt period and the second detection time after detecting that the output signal of the main channel differential transmission unit is low level, and starting the backup channel timer; and when the backup channel flag bit is 0, delaying the second detection time, setting the interrupt period of the backup channel timer to be the difference value between the second interrupt period and the second detection time, and starting the backup channel timer.
2. Method for dual channel synchronization according to claim 1, characterized in that: the first interrupt period is the same as the second interrupt period, and the first detection time is the same as the second detection time.
3. Method for dual channel synchronization according to claim 2, characterized in that: the first detection time is less than the first interrupt period, and the second detection time is less than the second interrupt period.
4. Method for dual channel synchronization according to claim 3, characterized in that: the initialization of the main channel and the backup channel is performed simultaneously.
5. A system for dual channel synchronization, characterized by: the dual channels comprise a main channel and a backup channel; the main channel comprises
The main channel differential transmitting unit is used for transmitting a synchronous signal to the backup channel;
the main channel differential receiving unit is used for receiving the synchronous signal of the backup channel;
the main channel processor is used for setting the state of a main channel flag bit according to the synchronization signal received by the main channel differential receiving unit, setting the interrupt period of a main channel timer according to the synchronization signal received by the main channel differential receiving unit and the state of the main channel flag bit, and controlling the main channel differential sending unit to send the synchronization signal to the backup channel;
the main channel is configured with the following synchronization method:
step S10, initializing the main channel;
s11, the main channel processor sets a first interrupt period of main channel timer interrupt;
step S12, judging whether the main channel timer interrupt is generated or not;
step S13, if the timer of the main channel generates the timer interrupt, outputting a high level to a main channel differential sending unit, and marking the position of a main channel to be 0;
step S14, a main channel differential receiving unit receives the signal output by the backup channel differential sending unit in a first detection time, and if the output signal of the backup channel differential sending unit is detected to be high level, the main channel is marked at position 1;
step S15, after the first detection time is over, outputting a signal output by the main channel differential sending unit to a low level, and receiving a signal output by the backup channel differential sending unit by the main channel differential receiving unit;
step S16, when the flag bit of the main channel is 1, immediately setting the interrupt period of the main channel timer as the difference value between the first interrupt period and the first detection time after detecting that the output signal of the backup channel differential transmission unit is at a low level, and starting the main channel timer; when the flag bit of the main channel is 0, immediately setting the interrupt period of the main channel timer as the difference value between the first interrupt period and the first detection time, and starting the main channel timer;
the backup channel comprises
The backup channel differential sending unit is used for sending a synchronous signal to the main channel;
the backup channel differential receiving unit is used for receiving the synchronous signal of the main channel;
the backup channel processor is used for setting the state of a backup channel flag bit according to the synchronization signal received by the backup channel differential receiving unit, setting the interrupt period of a backup channel timer according to the state of the synchronization signal received by the backup channel differential receiving unit and the state of the backup channel flag bit, and controlling the backup channel differential sending unit to send the synchronization signal to the main channel;
the backup channel is configured with the following synchronization method:
step S20, initializing the backup channel;
step S21, the backup channel processor sets a second interrupt period for the interrupt of the backup channel timer;
step S22, judging whether the backup channel timer interrupt is generated or not;
step S23, if the backup channel timer generates timer interruption, outputting a high level to a backup channel differential sending unit, and marking the position of a backup channel to be 0;
step S24, a backup channel differential receiving unit receives the signal output by the main channel differential sending unit in a second detection time, and if the output signal of the main channel differential sending unit is detected to be high level, the backup channel is marked at position 1;
step S25, after the second detection time is over, outputting a signal output by the backup channel differential transmitting unit to a low level, and receiving a signal output by the main channel differential transmitting unit by the backup channel differential receiving unit;
step S26, when the flag bit of the backup channel is 1, immediately setting the interrupt period of the backup channel timer as the difference value between the second interrupt period and the second detection time after detecting that the output signal of the main channel differential transmission unit is low level, and starting the backup channel timer; and when the backup channel flag bit is 0, delaying the second detection time, setting the interrupt period of the backup channel timer to be the difference value between the second interrupt period and the second detection time, and starting the backup channel timer.
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