CN205249184U - Frequency synthesizer - Google Patents
Frequency synthesizer Download PDFInfo
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- CN205249184U CN205249184U CN201520924509.5U CN201520924509U CN205249184U CN 205249184 U CN205249184 U CN 205249184U CN 201520924509 U CN201520924509 U CN 201520924509U CN 205249184 U CN205249184 U CN 205249184U
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- frequency
- frequency synthesizer
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- prescalar
- counter
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Abstract
The utility model discloses a frequency synthesizer belongs to frequency synthesis technical field. Frequency synthesizer includes: atomic clock, benchmark frequency divider, phase discriminator, loop filter, voltage -controlled crystal oscillator and prescalar, the output of atomic clock with the input electricity of benchmark frequency divider is connected, the output of benchmark frequency divider with an input electricity of phase discriminator is connected, another input of phase discriminator with the output electricity of prescalar is connected, the output of phase discriminator with loop filter's input electricity is connected, loop filter's output with the input electricity of voltage -controlled crystal oscillator is connected, the output of voltage -controlled crystal oscillator with the input electricity of prescalar is connected, provides the reference frequency that the stability is good, the accuracy is high through the atomic clock for the frequency of frequency synthesizer output has better stability and higher accuracy equally, and then makes frequency synthesizer can be applicable to more occasions.
Description
Technical field
The utility model relates to frequency synthesis technique field, particularly a kind of frequency synthesizer.
Background technology
Frequency synthesis technique is by a high stability and reference frequency process arithmetic accurately, produces toolThere is the technology of the optional frequency of same stability and the degree of accuracy. Existing frequency synthesis technique mainly comprises: straightConnect frequency synthesis technique and pll frequency synthesizer.
Existing pll frequency synthesizer mainly adopts the output frequency of quartz oscillator as benchmarkFrequency, realizes frequency synthesis. But, due to accuracy and the stability of quartz oscillator output frequencyLimited, make accuracy and the stability of output frequency of existing pll frequency synthesizer also limited,Can not be applicable to high-precision job requirements.
Utility model content
In order to solve accuracy and the limited problem of stability of existing frequency synthesizer output frequency, this realityProvide a kind of frequency synthesizer by new embodiment. Described technical scheme is as follows:
The utility model embodiment provides a kind of frequency synthesizer, and described frequency synthesizer comprises:
Atomic clock, reference divider, phase discriminator, loop filter, VCXO and prescalar;
The output of described atomic clock is electrically connected with the input of described reference divider, described reference dividerOutput be electrically connected with an input of described phase discriminator, another input of described phase discriminator and instituteState the output electrical connection of prescalar, the output of described phase discriminator and the input of described loop filterEnd electrical connection, the output of described loop filter is electrically connected with the input of described VCXO, described pressureThe control output of crystal oscillator and the input of described prescalar are electrically connected.
Alternatively, described atomic clock be hydrogen atomic clock, rubidium atomic clock, cesium-beam atomic clock any.
Alternatively, described reference divider is R frequency divider, the value of described R is 8,64,128,256,1024, any in 1160,2048.
Alternatively, described phase discriminator comprises: phase detectors, logic control circuit, the first counter,Two counters and lock detecting circuit, described the first counter and described the second counter all with described phase placeDetector electrical connection, described lock detecting circuit is electrically connected with described phase detectors, described logic control electricityRoad is electrically connected with described phase detectors and described lock detecting circuit.
Alternatively, described the first counter is 10 ÷ N counters able to programme, and described the second counter is 6Position ÷ A counter able to programme, 3≤N≤1023,3≤A≤63.
Alternatively, described loop filter comprises that the active proportional integral being made up of lm358 operational amplifier filtersRipple device.
Alternatively, described VCXO comprises MC1648 chip.
Alternatively, described prescalar is dual-mode frequency divider.
Alternatively, described prescalar comprises MC12022 chip.
Alternatively, described frequency synthesizer also comprises output port, and described output port is located at described voltage-controlled crystalline substanceShake and described prescalar between circuit on.
The beneficial effect that the technical scheme that the utility model embodiment provides is brought is:
By adopting atomic clock to provide the reference frequency that a kind of stability is good, accuracy is high for frequency synthesizer,Make the frequency of frequency synthesizer output there is equally good stability and higher accuracy, and then makeFrequency synthesizer can be applicable to more occasion, and its application is more extensive. In addition, at atomic clock and phase discriminatorBetween reference divider is set, the reference frequency that atomic clock is provided is first carried out the processing of integral multiple frequency division, makesThe fast close required output frequency of reference frequency after treatment, and then by reference frequency letter after treatment frequency divisionNumber transfer to phase discriminator, form phase-locked loop to frequency division place by phase discriminator, loop filter, VCXOReference frequency signal after reason carries out fine adjustment, thereby obtains required output frequency, can accelerate like thisThe frequency synthesis speed of frequency synthesizer.
Brief description of the drawings
In order to be illustrated more clearly in the technical scheme in the utility model embodiment, will describe embodiment belowIn the accompanying drawing of required use be briefly described, apparently, the accompanying drawing in the following describes is only thisSome embodiment of utility model, for those of ordinary skill in the art, are not paying creative workPrerequisite under, can also obtain according to these accompanying drawings other accompanying drawing.
Fig. 1 is the structural representation of a kind of frequency synthesizer of providing of the utility model embodiment;
Fig. 2 is the structural representation of a kind of phase discriminator of providing of the utility model embodiment;
Fig. 3 is the circuit diagram of a kind of loop filter of providing of the utility model embodiment;
Fig. 4 is the circuit diagram of a kind of VCXO of providing of the utility model embodiment;
Fig. 5 is the circuit diagram of a kind of prescalar of providing of the utility model embodiment.
Detailed description of the invention
For making the purpose of this utility model, technical scheme and advantage clearer, below in conjunction with accompanying drawing to thisUtility model embodiment is described in further detail.
Embodiment
The utility model embodiment provides a kind of frequency synthesizer, and referring to Fig. 1, this frequency synthesizer comprises:
Atomic clock 1, reference divider 2, phase discriminator 3, loop filter 4, VCXO 5 and prepositionFrequency divider 6.
The output of atomic clock 1 is electrically connected with the input of reference divider 2, the output of reference divider 2End is electrically connected with an input of phase discriminator 3, another input of phase discriminator 3 and prescalar 6Output electrical connection, the output of phase discriminator 3 is electrically connected with the input of loop filter 4, loop is filteredThe output of ripple device 4 is electrically connected with the input of VCXO 5, the output of VCXO 5 and preposition pointFrequently the input of device 6 electrical connection.
In the present embodiment, reference divider 2 is carried out frequency division place for the reference frequency that atomic clock 1 is exportedReason, prescalar 6 is for carrying out frequency division processing (above-mentioned frequency division processing to the output frequency of frequency synthesizerFrequency dividing ratio can be 3-5). Phase discriminator 3 claims again phase comparator, mainly for detection of the two-way receivingSignal (comprises through frequency division reference frequency signal after treatment with through frequency division frequency synthesizer after treatmentOutput frequency signal) phase difference, and the phase signal detecting is changed into error voltage signal outputTo loop filter 4. Loop filter 4 is mainly used in the error voltage signal that filtering phase discriminator 3 generatesIn radio-frequency component and noise, to ensure the desired performance of loop, improve the stability of frequency synthesizer,And voltage signal is controlled in output. The control voltage signal of VCXO 5 for exporting according to loop filter 4,Produce output frequency signal.
The utility model embodiment is by adopting atomic clock to provide a kind of stability good, smart for frequency synthesizerThe reference frequency that exactness is high, makes the frequency of frequency synthesizer output have equally good stability and higherAccuracy, and then make frequency synthesizer can be applicable to more occasion, its application is more extensive. In addition,Between atomic clock and phase discriminator, reference divider is set, the reference frequency that atomic clock is provided is first carried out integerTimes frequency division processing, makes reference frequency after treatment fast near required output frequency, and then by frequency division placeReference frequency signal after reason transfers to phase discriminator, forms lock by phase discriminator, loop filter, VCXOPhase loop back path is carried out fine adjustment to frequency division reference frequency signal after treatment, thereby obtains required output frequentlyRate, can accelerate the frequency synthesis speed of frequency synthesizer like this.
In the utility model embodiment, atomic clock 1 can be hydrogen atomic clock, rubidium atomic clock, cesium-beam atomic clockAny.
Preferably, atomic clock 1 is hydrogen atomic clock, and hydrogen atomic clock is other atomic clocks relatively, and its stability is better,Can be for frequency synthesizer provides stabilizied reference frequency more, and then improve the steady of frequency synthesizer output frequencyQualitative.
Alternatively, reference divider 2 is R frequency divider, the value of R can be 8,64,128,256,1024,1160, any in 2048.
In the present embodiment, the reference frequency that atomic clock 1 produces is first carried out integral multiple by reference divider 2Frequency division processing, by reference frequency first fast near required frequency, then by by phase discriminator 3, loop filter 4,The phase-locked loop that VCXO 5 forms, carries out fine adjustment to reference frequency, makes it reach required frequency,Can accelerate like this frequency synthesis speed, also not reduce the accuracy of synthetic frequency simultaneously.
Alternatively, referring to Fig. 2, phase discriminator 3 can comprise: phase detectors 31, logic control circuit 32,The first counter 33, the second counter 34 and lock detecting circuit 35, the first counters 33 and secondNumber device 34 is all electrically connected with phase detectors 31, and lock detecting circuit 35 is electrically connected with phase detectors 31,Logic control circuit 32 is electrically connected with phase detectors 31 and lock detecting circuit 35. Wherein, the first countingDevice 33 and the second counter 34 are respectively used to two paths of signals to count, and phase detectors 31 are for basisThe first counter 33 and the second counter 34 carry out the phase place judgement of two paths of signals, lock detecting circuit 35 useIn determining according to the judgement of phase detectors 31 whether loop locks. Logic control circuit 32 is for to phase demodulationEach Digital Logic in device 3 is controlled.
Further, the first counter can be 10 ÷ N able to programme (3≤N≤1023) counters, theTwo counters can be 6 ÷ A able to programme (3≤A≤63) counters.
In the present embodiment, phase discriminator 3 (comprises through frequency division mainly for detection of the two paths of signals receivingReference frequency signal after treatment and through the output frequency signal of frequency division frequency synthesizer after treatment) phasePotential difference, and the phase signal detecting is changed into error voltage signal.
Alternatively, loop filter 4 can comprise the active proportional integral being made up of lm358 operational amplifierWave filter, particular circuit configurations can as shown in Figure 3, repeat no more here.
Referring to Fig. 3, in the time building this circuit, suitable electric capacity (C1=C2=C3=C4) can chosenAfter, can come calculated resistance R2 (R2=R1=R3) and resistance R 4 (R4=R5=R6) according to following formula:
R1＝Kv*Kd/(N*ωn*ωn*C)；
R2＝2ξ/(ωn*C)。
Wherein, the original frequency that ω n is phase-locked loop; N is the divider ratio in frequency synthesizer; C is electric capacityValue; Kv is the voltage-controlled slope of VCXO 5; Kd is the sensitivity of phase discriminator 3; ξ is phase-locked loopDamped coefficient. The suitable span of ξ is between 0.5～1.0, preferably ξ=0.707.
Alternatively, VCXO 5 comprises MC1648 chip. Be that VCXO 5 can adopt MC1648Chip is realized, and its frequency that produces signal can reach 225KHz. VCXO 5 particular circuit configurations canWith as shown in Figure 4, repeat no more here.
Alternatively, prescalar 6 is dual-mode frequency divider.
In the present embodiment, prescalar 6 can be dual-mode frequency divider, configures simultaneously with phase discriminator 3Two counters coordinate, and can, in the time that reference frequency is related to required frequency an odd lot times, divide the institute that occurs frequentlyThe frequency needing.
Alternatively, prescalar 6 comprises MC12022 chip. Prescalar 6 particular circuit configurations canWith as shown in Figure 5, this prescalar 6 mainly divides by the level of controlling SW and WC two endsThe selection of frequency ratio, table specific as follows:
| SW | MC | Frequency dividing ratio |
| 1 | 1 | 64 |
| 1 | 0 | 65 |
| 0 | 1 | 128 |
| 0 | 0 | 129 |
In upper table, 1 represents high level, and 0 represents low level.
It should be noted that, prescalar 6 can be dual-mode frequency divider (÷ P/ ÷ P+1), when MC isWhen low level " 0 ", the frequency dividing ratio of prescalar 6 is P+1; In the time that MC is high level " 1 ", frontThe frequency dividing ratio of putting frequency divider 6 is P. Prescalar 6 can with the first counter 33 in phase discriminator 3 andTwo counters 34 coordinate, and wherein, the first counter is 10 ÷ N able to programme (3≤N≤1023) countingsDevice, the second counter is 6 ÷ A able to programme (3≤A≤63) counters, total like this divider ratioN1＝N*P+A。
Further, this frequency synthesizer also comprises output port, and output port is located at described VCXO 5And on circuit between described prescalar 6.
The frequency synthesizer providing for the utility model, now adopts Aglient53132A frequency meter to come itThe signal of output carries out frequency detecting, and test data is as shown in the table:
The unit of the numerical value in upper table is MHz.
As seen from the above table, the stability of this frequency synthesizer output frequency is good, the degree of accuracy is high.
The foregoing is only preferred embodiment of the present utility model, not in order to limit the utility model, allWithin spirit of the present utility model and principle, any amendment of doing, be equal to replacement, improvement etc., all should wrapWithin being contained in protection domain of the present utility model.
Claims (10)
1. a frequency synthesizer, is characterized in that, described frequency synthesizer comprises: atomic clock, basis pointFrequently device, phase discriminator, loop filter, VCXO and prescalar;
The output of described atomic clock is electrically connected with the input of described reference divider, described reference dividerOutput be electrically connected with an input of described phase discriminator, another input of described phase discriminator and instituteState the output electrical connection of prescalar, the output of described phase discriminator and the input of described loop filterEnd electrical connection, the output of described loop filter is electrically connected with the input of described VCXO, described pressureThe control output of crystal oscillator and the input of described prescalar are electrically connected.
2. frequency synthesizer according to claim 1, is characterized in that, described atomic clock is hydrogen atomAny in clock, rubidium atomic clock, cesium-beam atomic clock.
3. frequency synthesizer according to claim 1, is characterized in that, described reference divider is RFrequency divider, the value of described R is any in 8,64,128,256,1024,1160,2048.
4. frequency synthesizer according to claim 1, is characterized in that, described phase discriminator comprises: phaseBit detector, logic control circuit, the first counter, the second counter and lock detecting circuit, described inThe first counter and described the second counter are all electrically connected with described phase detectors, described lock detecting circuitBe electrically connected described logic control circuit and described phase detectors and described locking inspection with described phase detectorsSlowdown monitoring circuit electrical connection.
5. frequency synthesizer according to claim 4, is characterized in that, described the first counter is 10Position ÷ N counter able to programme, described the second counter is 6 ÷ A counters able to programme, 3≤N≤1023,3≤A≤63。
6. frequency synthesizer according to claim 1, is characterized in that, described loop filter comprisesThe active proportional-integral filter being formed by lm358 operational amplifier.
7. frequency synthesizer according to claim 1, is characterized in that, described VCXO comprisesMC1648 chip.
8. frequency synthesizer according to claim 1, is characterized in that, described prescalar is twoMould frequency divider.
9. frequency synthesizer according to claim 8, is characterized in that, described prescalar comprisesMC12022 chip.
10. according to the frequency synthesizer described in claim 1-9 any one, it is characterized in that, described frequency is closedGrow up to be a useful person and also comprise output port, described output port is located between described VCXO and described prescalarCircuit on.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520924509.5U CN205249184U (en) | 2015-11-19 | 2015-11-19 | Frequency synthesizer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520924509.5U CN205249184U (en) | 2015-11-19 | 2015-11-19 | Frequency synthesizer |
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| CN205249184U true CN205249184U (en) | 2016-05-18 |
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| CN201520924509.5U Expired - Fee Related CN205249184U (en) | 2015-11-19 | 2015-11-19 | Frequency synthesizer |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106027046A (en) * | 2016-08-12 | 2016-10-12 | 中国电子科技集团公司第二十九研究所 | Atomic-clock-based high-purity reference source generation method and system |
| CN109167572A (en) * | 2018-10-12 | 2019-01-08 | 南京屹信航天科技有限公司 | It is a kind of for minimizing the frequency synthesizer of ODU receiving channel |
-
2015
- 2015-11-19 CN CN201520924509.5U patent/CN205249184U/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106027046A (en) * | 2016-08-12 | 2016-10-12 | 中国电子科技集团公司第二十九研究所 | Atomic-clock-based high-purity reference source generation method and system |
| CN109167572A (en) * | 2018-10-12 | 2019-01-08 | 南京屹信航天科技有限公司 | It is a kind of for minimizing the frequency synthesizer of ODU receiving channel |
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| Date | Code | Title | Description |
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| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20160518 Termination date: 20161119 |
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| CF01 | Termination of patent right due to non-payment of annual fee |