CN205563133U - Digital PLL phase -locked loop simulation system of high Q value that rebounds - Google Patents

Abstract

The utility model relates to a digital PLL phase -locked loop simulation system of high Q value that rebounds, its characterized in that: including central processing unit, time constant generator, frequency divider, detection amplifier, integrator, emulation driving source generator, frequently steady tester and frequency multiplier, compared with the prior art, the beneficial effects of the utility model are that: the utility model has the advantages of simple structure and reasonable design, can effectively improve the emulation computational accuracy, adopt program control simultaneously, degree of automation is higher, and it is comparatively convenient to use, improves simulation system's simulation ability.

Description

Bounce-back high q-factor digital P LL phaselocked loop analogue system

Technical field

This utility model relates to analogue system field, particularly relates to the high q-factor digital P LL phaselocked loop analogue system that rebounds.

Background technology

So-called system emulation (system simulation), it is simply that according to the purpose of systematic analysis, respectively want in the system of analysis On the basis of disposition matter and mutual relation thereof, set up can descriptive system structure or action process and there is certain logical relation Or the phantom of quantitative relation, carry out accordingly testing or quantitative analysis, to obtain the various information needed for correct decisions.Phase-locked Loop is a kind of feedback control circuit, is called for short phaselocked loop (PLL, Phase-Locked Loop).The feature of phaselocked loop is: utilize The reference signal of outside input controls frequency and the phase place of loop internal oscillation signal.Because phaselocked loop can realize output signal frequency Rate to frequency input signal from motion tracking, so phaselocked loop is generally used for Closed loop track circuit.Phaselocked loop is in the process of work In, when the frequency of output signal and the frequency of input signal are equal, output voltage and input voltage keep fixing phase contrast Value, i.e. output voltage is lockable with the phase place of input voltage, here it is the origin of phaselocked loop title.Phaselocked loop is generally by phase discriminator (PD, Phase Detector), loop filter (LF, Loop Filter) and voltage controlled oscillator (VCO, Voltage Controlled Oscillator) three part compositions；Phase discriminator in phaselocked loop is also called phase comparator, and its effect is Detection input signal and the phase contrast of output signal, and the phase signal detected is converted into uD(t) voltage signal output, The control voltage uC(t of voltage controlled oscillator is formed after the filtering of this signal low-pass filtered device), the frequency to oscillator output signal Implement to control.

Existing analogue system computational accuracy is relatively low, and when emulating complication system, the difficulty that circuit realizes is relatively big, essence Degree is difficult to ensure；When the logic decision part in system is more, emulating relatively difficult, popularity rate is relatively low.

Utility model content

The purpose of this utility model is to overcome the deficiencies in the prior art, it is provided that bounce-back high q-factor digital P LL is phase-locked Loop simulation system.

This utility model is to be achieved through the following technical solutions:

Bounce-back high q-factor digital P LL phaselocked loop analogue system, including central processing unit, time constant generator, frequency dividing Device, detector amplifier, integrator, simulation excitation source generator, frequency stabilization tester and doubler；Described frequency divider connects detection Amplifier, described detector amplifier connects integrator, and described integrator connects central controller；Described central controller is even It is connected to simulation excitation source generator, doubler, frequency stabilization tester and time constant generator；Described simulation excitation source generator is even Being connected to frequency stabilization tester, described doubler connects simulation excitation source generator and frequency divider；Described time constant generator is divided Do not connect with detector amplifier, integrator.

Further, in analogue system signal transmission figure F0 be high steady reference source original frequency,,It is respectively High steady reference source crossover frequency and simulation excitation generator output frequency.,,,,It is respectively Gao Wencan Examine source, detector amplifier, integrator, simulation excitation generator and the error of doubler outfan.M is Clock Multiplier Factor,For Detector amplifier discrimination gradient,Voltage-controlled slope for simulation excitation generator.1/(1+STh) be equivalence RC wave filter ring Road transmission function, wherein S is complex Fourier frequency, Th is RC time constant.A and Ti is respectively integrator Amplification and time constant, here, for realizing the emulation of Fig. 1, we add time constant generator module, it by Resistance is constituted with condenser type multistage connection in series-parallel loop, in order to produce different RC time constants, and is applied to detection amplification in Fig. 1 The Th of device and the Ti of integrator.

In the integrator of Fig. 1, for simplifying simulation scenarios, we have a mind to arrange amplification A of integrator is infinity, The transmission function that can approximate understanding integrator when A is the biggest is 1/STi.Definition:

(1)

Then the analogue system open-loop gain of Fig. 1 is:

(2)

The stable state output frequency of simulation excitation source generator is represented by:

(3)

System, after loop work reaches stable state, generally has G (s) " 1, so (3) formula can be written into:

(4)

From (4) formula, the stable state output frequency of simulation excitation source generator should be joined equal to high stable in the ideal situation Examine frequency after the frequency dividing of source

Rate value has a multiple proportion:

(5)

Design parameter in this utility model is:

1, multiple proportion

In order to realize in Fig. 1 and formula (5), the stable state output frequency of the theoretical simulation excitation source generator expressed should be steady with height Determine the multiple proportion between reference source frequency values, and above-mentioned relation is a dynamic equilibrium, it would be desirable in Fig. 1 Central processor coordinates the work of whole system, and temporarily defining this task parameters at this is X, after can elaborate.

2, time constant

The setting of formula (5) and above-mentioned X parameter is theoretical, because in the PLL phase-locked loop that actual Fig. 1 is constituted, Owing in the frequency difference of the steady reference source of height self and PLL loop, the error of each several part exists, the output frequency of Fig. 1 is total with its nominal value There is certain deviation.The deviation of simulation excitation generator end and aging, integrator null offset, doubler phase place change etc. all may Produce this deviation.AllThe long term drift of item is all likely to result in the catabiosis of output frequency, becomes additional noise.

Open-loop gain G (s) should be improved for reducing the error of above-mentioned electronic circuitry part as far as possible.For the sake of convenient simulation, I The most unified by Fig. 1,,,,Every error is set to fixed value.Imitate for improving Fig. 1 The performance of true system, should make open-loop gain G (s) become big theoretically as far as possible, make the molecule in formula (2)Become big, but actually G0 should have the limit.It is generally acknowledged that the damped coefficient of system is no less than 0.5, then

(6)

For the sake of so convenient, we set G0=1, make Th=Ti simultaneously.The method realized is:

(1), it is respectively provided with detector amplifier, simulation excitation generator, doubler by the central controller in Fig. 1、, M, makeEqual to 1；

(2), be respectively provided with detector amplifier by the central controller in Fig. 1, time constant Th=that integrator is corresponding Ti。

After above-mentioned setting, the open-loop gain of Fig. 1 analogue system that formula (2) is stated is:

(7)

3, analogue system Q-value

Reducing time constant Th, really increase the open-loop gain of analogue system according to formula (7), this is advantageous for systematicness Can, this increases loop filter bandwidth fh the most simultaneously.Fig. 1 is high, and steady reference source is equivalent to a descriminator, when its long term drift When can ignore, it is assumed that its power-law noise formula is:

(8)

Fig. 1 loop work under theoretical case is at linear condition, if it is believed that simulation excitation generator and the steady reference of height Source power spectrum density (Sy (f) OSC with Sy (f) REF) is the most uncorrelated, then Fig. 1 system output power spectrum density is permissible It is expressed as:

(9)

According to definition, Wo Menyou, therefore, (8) formula substitute into (9) formula it is seen that, When emulation average period the most in short-term,, have

(10)

When the average period of emulation is the longest, have

(11)

Obviously, whole loop is a high pass filter for simulation excitation generator；For reference source steady with height It it is a low pass filter；Its filtering characteristic is determined by the high end cut-off frequencies fh of loop filter.(10) extreme case of formula It is, the extreme case of (11) formula is.It can be seen that fh crosses senior general makes Fig. 1's Analogue system output signal short-term stability is deteriorated；Fh is too small to be deteriorated the analogue system output signal long-term stability making Fig. 1. After Fig. 1 system closed loop, we are the loop bandwidth i.e. high end cut-off frequencies fh that cannot learn system, and we carry out table with Q-value Levy the stabilization signal of the analogue system output signal of Fig. 1, and draw sign system Q by the frequency stabilization tester measurement in Fig. 1 The simulation results of value, thus indirectly the value of the i.e. high end cut-off frequencies fh of reaction loop bandwidth selects quality.

Compared with prior art, the beneficial effects of the utility model are: this utility model simple in construction, reasonable in design, Can be effectively improved simulation calculation precision, use programme-control simultaneously, automaticity is higher, uses more convenient, improves imitative The simulated performance of true system.

Accompanying drawing explanation

Fig. 1 is structural representation of the present utility model；

Fig. 2 is this utility model analogue system circuit diagram；

Fig. 3 is analogue system signal judgement figure in this utility model；

Fig. 4 is analogue system strategy anticipation trendgram in this utility model embodiment；

Fig. 5 is analogue system strategy anticipation trendgram in another embodiment of this utility model.

Detailed description of the invention

In order to make the purpose of this utility model, technical scheme and advantage clearer, below in conjunction with accompanying drawing and enforcement Example, is further elaborated to this utility model.Should be appreciated that specific embodiment described herein is only in order to explain This utility model, is not used to limit this utility model.

Referring to Fig. 1-5, Fig. 1 is structural representation of the present utility model, and Fig. 2 is this utility model analogue system circuit Figure, Fig. 3 is analogue system signal judgement figure in this utility model, and Fig. 4 is that in this utility model embodiment, analogue system strategy is pre- Sentencing trendgram, Fig. 5 is optical frequency shift-light intensity test curve in another embodiment of this utility model.

Bounce-back high q-factor digital P LL phaselocked loop analogue system, including central processing unit, time constant generator, frequency dividing Device, detector amplifier, integrator, simulation excitation source generator, frequency stabilization tester and doubler；Described frequency divider connects detection Amplifier, described detector amplifier connects integrator, and described integrator connects central controller；Described central controller is even It is connected to simulation excitation source generator, doubler, frequency stabilization tester and time constant generator；Described simulation excitation source generator is even Being connected to frequency stabilization tester, described doubler connects simulation excitation source generator and frequency divider；Described time constant generator is divided Do not connect with detector amplifier, integrator.

The mode realizing parameters employing in this utility model is:

Multiple proportion strategy:

In Fig. 1 system, the frequency range that our Simulation Model pre-sets is as follows:

(1), for realizing the simulated response of high band, we select the high steady reference source that frequency is higher, at the frequency dividing of Fig. 1 The signal frequency obtained after reason is 50.****MHz.Wherein * * * * (remaining into four) of decimal place is random, for convenience of saying Seeing from tomorrow, in this patent is implemented, we take * * * *=1234, i.e. in Fig. 1For 50.1234MHz；

(2) the initialization simulation excitation generator output 10MHz frequency signal that, central controller is arranged；

(3), central controller arrange initialization doubler output signal frequency withTheoretical value is identical, is the most also 50.1234MHz；

(4), simulation excitation generator output signal frequency and doubler output signal frequency have linkage connection.

Realize the circuit structure of above-mentioned model as shown in Figure 2:

In central controller module during wherein processor is positioned at Fig. 1, and DDS1 in processor XTAL end and Fig. 2, The RefClk of DDS2 terminates the frequency signal into same clock source, from synchronization during to ensure.Processor is at outside input end of clock (XTAL), on the basis of as clock reference during work, the three adjustable square-wave signals of road phase relation, Qi Zhongyi are produced respectively Road keying FM signal is delivered to the FSK keying frequency modulation input port of DDS1 and is realized frequency modulation, a road synchronous reference signal as synchronizing Phase demodulation, a road judgement are used as the lock-in detection of Fig. 1 phaselocked loop with signal.DDS1 makees outside clock reference input (RefClk) On the basis of reference clock during work, by the serial sequential communication between processor and DDS1, DDS1 is according to FSK end processor The high and low level state of the square wave keying frequency modulation square-wave signal sent here is chosen internal frequency respectively and is controlled in depositor (F1, F0) The multiple-frequency modulation data presetting frequency of processor input as output, thus produce the frequency signal 50.1234MHz of band modulation ± △ f exports.Preset frequency-splitting △ f is determined by the numerical value in two frequency control register F1, F0, concrete in view of penetrating Frequently the 4th precision after signal is 50.1234MHz(arithmetic point), we take △ f=100Hz.Control DDS1 with above-mentioned processor to produce The principle of raw multiple-frequency modulation signal is similar to, and processor passes through serial communication sequential, and same frequency dividing numerical value is passed to DDS2, produces The raw 50.1234MHz frequency signal output without modulation.The 50.1234MHz frequency signal obtained by DDS2 is sent into outside DDS3 Portion's clock reference input (RefClk), reference clock when working as DDS3.Processor is according to serial sequential communication, by phase Initialization output frequency (10MHz) numerical value answered passes to DDS3, thus obtains the output of simulation excitation source generator frequency signal. Owing to during the external reference of DDS3, base uses the frequency-doubled signal that DDS2 produces, therefore in this programme, when in the closed circuit in Fig. 1 Central controller obtain corresponding phase discrimination signal information after, the frequency of the multiple-frequency modulation signal of corresponding DDS2 can be revised, this Sample also can cause the frequency of DDS3 output signal to change, and i.e. instead of traditional changing by the way of D/A VCXO Become the output frequency value of local oscillator, and then the method changing system output frequency.It should be noted that and output frequency signal is adopted Mode with direct digital synthesizers so that act as a higher synthesizer role of degree of stability in certain range of application. User by user input mouth in Fig. 2, can revise the complete machine output letter of DDS3 according to the requirement in reality application easily Number frequency values.

Time constant Provisioning Policy

From aforementioned schemes, we setEqual to 1, make Th=Ti simultaneously.Close according to above-mentioned multiple System's strategy, the frequency after the signal frequency that we make simulation excitation source generator export is 10MHz, high steady reference source divides selects For 50.1234MHz, according to formula (5), M=5 can be obtained.From above-mentioned multiple proportion strategy, we In the analogue system of design drawing 1 and be provided without traditional changing system output frequency value by the way of D/A VCXO Method, so in Fig. 1The voltage-controlled slope of simulation excitation generator cannot be known, we can only pass throughObtain equal to 1 and by M=5*The conclusion of=1/5.In concrete implementation process, according to Fig. 1 Detector amplifier can only be carried out by we by central controllerThe setting of value.Due to the time constant in analogue system only Determined by Th, thus according to Fig. 1 we by central controller to the control realization of time constant generator to detector amplifier, The pickup time constant Th of integrator and the setting of integration time constant Ti, and make Th=Ti.

Analogue system Q-value strategy

We produce three road square-wave signals by processor in fig. 2: synchronous reference signal, keying FM signal, judgement With signal, make synchronous reference signal frequency be equal to keying FM signal frequency, and have certain phase delay poor；Make judgement simultaneously Can be between 8 to 20 by signal frequency N(N value) times synchronous reference signal frequency or keying FM signal frequency, and have Certain phase delay is poor.It is 169Hz that the most concrete we take synchronous reference signal frequency equal to keying FM signal frequency, And both phase contrasts are 160 degree；Take judgement signal frequency N value is 8 times simultaneously, and is 90 with synchronous reference signal phase contrast Degree.

Concrete judgment basis is as shown in Figure 3:

In Fig. 3, judgement signal, synchronous reference signal, keying FM signal are to have the square wave of fixed frequency and phase relation Digital signal；Enable signal to be 1 or be 0, therefore can be regarded as the square wave digital signal without fixed frequency；Phase demodulation is believed Number by Fig. 1 integrator produce, it be one change direct current signal, therefore can be regarded as without fixed frequency simulation letter Number.

Combining Fig. 1 according to the principle of Fig. 3, we set a certain rising edge of judgement signal and start as triggering judgement, Before next rising edge arrives, complete 10 times judge, when then next rising edge arrives, trigger again next group and judge for 10 times.By The frequency of judgement signal in Fig. 3 is known in advance in us, i.e. it is understood that time T between adjacent two rising edges, therefore can With one group of time interval judged for 10 times of mean allocation.

In Fig. 1, central controller is according to above-mentioned triggering Rule of judgment, judges the phase discrimination signal carried by integrator, When its analog DC signal magnitude is positioned at the non-enable banded regions shown in Fig. 3, central controller exports the enable letter in Fig. 3 Number being 0, the steady measuring instrument of frequency in Fig. 1 does not works；When outside the non-enable banded regions that its analog DC signal magnitude is positioned at shown in Fig. 3 Time, the enable signal that central controller exports in Fig. 3 is 1, and the steady measuring instrument of frequency in Fig. 1 is started working；Emulation Q-value is the most just The simulation results value of output when being the work of Fig. 1 intermediate frequency steady measuring instrument, it reflects the property of Fig. 1 analogue system output signal Can,

During whole emulation, central controller, when starting, initializes all of value to be arranged, and these parameters are just No longer change, only has detector amplifier parameter during dynamic simulationBe worth, detector amplifier time constant Th value must be by central authorities Controller module is dynamically arranged, and judges that the two parameter the most reasonably criterion is then emulation Q-value.We giveValue takes scope 1-10, same Th we also take a 1-10.When Fig. 1 system emulates at the beginning, except setting at the beginning of each road Beginning arranges outside value, and we exist in meetingValue and Th value gamut emulation obtain for one time correspondence Q-value, Q-value between L and H, It is defined as L=1 to H=100(Q value to be the bigger the better), we define the Q-value data in this section of simulation time is " modeling district ".

In dynamic simulation process, in most cases system is carried out according to Fig. 3 institute principle.Below additionally we implement " bounce-back " property of two tactful evaluation systems and " high Q " property, first we compress the Q-value of above-mentioned acquisition, take Q-value scope at (L= 25 to L=50) it is defined as strategy value district Q1, central controller is arrangedIt is worth and Th value, and the time of sampling Q-value is to synchronize, And make settingChanging in the opposite direction of value and Th value:

The first situation: next time arrangeValue (being designated as K2) is compared with thisValue (being designated as K1) be to increase (i.e. K2 > K1), then arrange Th value (being designated as T2) then relatively this Th value (being designated as T1) is to reduce (i.e. T2 < T1) next time.

The second situation: next time arrangeValue (being designated as K2) is compared with thisValue (being designated as K1) be reduce (i.e. K2 < K1), then Th value (being designated as T2) (i.e. T2 > T1) that then relatively this Th value (being designated as T1) is to increase is set next time.

It should be noted is that: central controller be at any time carry out emulating according to above-mentioned two kinds of situations.On having had The operating mechanism stated, we have a following two strategy:

Embodiment one: according to above-mentioned emulation, first obtains in " the modeling district " of system q, as shown in Figure 4, then system with Machine ground enters the first situation above-mentioned or the second situation.When the emulation Q-value of system is more than H, i.e. at some O in Fig. 4, no matter Now system is in the first situation or the second situation, and we will put system in the first situation state, i.e. increase Value reduces Th value simultaneously, and makes the parameter of increase trendValue variable quantity increases to original 2 times, arranges the most next timeValue is the above-mentioned 2*(K2-K1 of change in the case of the first), the changing value that arranges of Th value is original (T2-T1) simultaneously, We are defined as the third situation.Analogue system emulates according to the 4th kind of situation always, and as shown in Figure 4, simulation result is managed To judge that Trendline is carried out to a certain H1 in advance along the virtual policy in figure in opinion, until occurring that Q-value declines, then we are extensive Restore the facilities of coming,

Embodiment two: according to above-mentioned emulation, first obtains " the modeling district " of system q, as it is shown in figure 5, then system with Machine ground enters the first situation above-mentioned or the second situation.When system emulation Q-value occurs at L1=25, and continuous print three Rising occurs in secondary Q-value, and rises at more than 33 (at the some O in Fig. 5), and the most now system is in the first situation or the Two kinds of situations, we will put system in the second situation state, i.e. reduceValue increases Th value simultaneously, and makes increase trend Parameter Th value variable quantity increase to original 2 times, arrange Th value is the 2* of change in the case of above-mentioned the second the most next time (T2-T1), simultaneouslyThe changing value that arranges be original (K2-K1), we are defined as the third situation.Analogue system is always Emulate according to the third situation, as it is shown in figure 5, simulation result will judge trend along the virtual policy in figure in theory in advance Line is carried out to a certain H1, until occurring that Q-value declines, then we recover original facilities.

The foregoing is only preferred embodiment of the present utility model, not in order to limit this utility model, all at this Any amendment, equivalent and the improvement etc. made within the spirit of utility model and principle, should be included in this utility model Protection domain within.

Claims (7)

1. bounce-back high q-factor digital P LL phaselocked loop analogue system, it is characterised in that: include that central processing unit, time constant occur Device, frequency divider, detector amplifier, integrator, simulation excitation source generator, frequency stabilization tester and doubler；Described frequency divider is even Being connected to detector amplifier, described detector amplifier connects integrator, and described integrator connects central controller；Described central authorities Controller connects simulation excitation source generator, doubler, frequency stabilization tester and time constant generator；Described simulation excitation source Generator connects frequency stabilization tester, and described doubler connects simulation excitation source generator and frequency divider；Described time constant Generator connects with detector amplifier, integrator respectively.

Bounce-back high q-factor digital P LL phaselocked loop analogue system the most according to claim 1, it is characterised in that: the described time Constant generator is made up of resistance and condenser type multistage connection in series-parallel loop.

Bounce-back high q-factor digital P LL phaselocked loop analogue system the most according to claim 1, it is characterised in that: described central authorities Time constant Th=Ti that controller is respectively provided with detector amplifier, integrator is corresponding.

Bounce-back high q-factor digital P LL phaselocked loop analogue system the most according to claim 1, it is characterised in that: described central authorities Controller is respectively provided with detector amplifier, simulation excitation generator, doubler、, M, make Equal to 1.

Bounce-back high q-factor digital P LL phaselocked loop analogue system the most according to claim 1, it is characterised in that: described central authorities The initialization simulation excitation generator output 10MHz frequency signal that controller is arranged.

Bounce-back high q-factor digital P LL phaselocked loop analogue system the most according to claim 1, it is characterised in that: described central authorities Controller arrange initialization doubler output signal frequency withTheoretical value is identical, is the most also 50.1234MHz.

Bounce-back high q-factor digital P LL phaselocked loop analogue system the most according to claim 1, it is characterised in that: simulation excitation Generator output signal frequency and doubler output signal frequency have linkage connection.