CN105938330A - Rebounding high-Q-value digital PLL simulation system - Google Patents
Rebounding high-Q-value digital PLL simulation system Download PDFInfo
- Publication number
- CN105938330A CN105938330A CN201610228474.0A CN201610228474A CN105938330A CN 105938330 A CN105938330 A CN 105938330A CN 201610228474 A CN201610228474 A CN 201610228474A CN 105938330 A CN105938330 A CN 105938330A
- Authority
- CN
- China
- Prior art keywords
- frequency
- generator
- analogue system
- value
- integrator
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B17/00—Systems involving the use of models or simulators of said systems
- G05B17/02—Systems involving the use of models or simulators of said systems electric
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Automation & Control Theory (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Abstract
The invention relates to a rebounding high-Q-value digital phase-locked loop (PLL) simulation system comprising a central processor, a time constant generator, a frequency divider, a detection amplifier, an integrator, a simulated excitation source generator, a frequency stability tester and a frequency multiplier. Compared with the prior art, the system has the following beneficial effects: the structure is simple; the design is reasonable; the simulation calculation precision can be improved effectively; because of a program control way, the automation degree is high and the system can be used conveniently; and the simulation performance of the simulation system can be improved.
Description
Technical field
The present invention relates to analogue system field, particularly relate to the high q-factor digital P LL phaselocked loop analogue system that rebounds.
Background technology
So-called system emulation (system simulation), it is simply that according to the purpose of systematic analysis, respectively want in the system of analysis
On the basis of disposition matter and mutual relation thereof, set up can descriptive system structure or action process and there is certain logical relation
Or the phantom of quantitative relation, carry out accordingly testing or quantitative analysis, to obtain the various information needed for correct decisions.Phase-locked
Loop is a kind of feedback control circuit, is called for short phaselocked loop (PLL, Phase-Locked Loop).The feature of phaselocked loop is: utilize
The reference signal of outside input controls frequency and the phase place of loop internal oscillation signal.Because phaselocked loop can realize output signal frequency
Rate to frequency input signal from motion tracking, so phaselocked loop is generally used for Closed loop track circuit.Phaselocked loop is in the process of work
In, when the frequency of output signal and the frequency of input signal are equal, output voltage and input voltage keep fixing phase contrast
Value, i.e. output voltage is lockable with the phase place of input voltage, here it is the origin of phaselocked loop title.Phaselocked loop is generally by phase discriminator
(PD, Phase Detector), loop filter (LF, Loop Filter) and voltage controlled oscillator (VCO, Voltage
Controlled Oscillator) three part compositions；Phase discriminator in phaselocked loop is also called phase comparator, and its effect is
Detection input signal and the phase contrast of output signal, and the phase signal detected is converted into uD(t) voltage signal output,
The control voltage uC(t of voltage controlled oscillator is formed after the filtering of this signal low-pass filtered device), the frequency to oscillator output signal
Implement to control.
Existing analogue system computational accuracy is relatively low, and when emulating complication system, the difficulty that circuit realizes is relatively big, essence
Degree is difficult to ensure；When the logic decision part in system is more, emulating relatively difficult, popularity rate is relatively low.
Summary of the invention
The invention aims to overcome the deficiencies in the prior art, it is provided that bounce-back high q-factor digital P LL phaselocked loop is imitated
True system.
The present invention is to be achieved through the following technical solutions:
Bounce-back high q-factor digital P LL phaselocked loop analogue system, including central processing unit, time constant generator, frequency divider, inspection
Twt amplifier, integrator, simulation excitation source generator, frequency stabilization tester and doubler；Described frequency divider connects has detection to amplify
Device, described detector amplifier connects integrator, and described integrator connects central controller；Described central controller connects to be had
Simulation excitation source generator, doubler, frequency stabilization tester and time constant generator；Described simulation excitation source generator connects to be had
Frequency stabilization tester, described doubler connects simulation excitation source generator and frequency divider；Described time constant generator respectively and
Detector amplifier, integrator connect.
Further, in analogue system signal transmission figure F0 be high steady reference source original frequency,,Respectively
For height steady reference source crossover frequency and simulation excitation generator output frequency.,,,,It is respectively
High steady reference source, detector amplifier, integrator, simulation excitation generator and the error of doubler outfan.M is Clock Multiplier Factor,For detector amplifier discrimination gradient,Voltage-controlled slope for simulation excitation generator.1/(1+STh) it is equivalence RC filter
The loop transfer function of ripple device, wherein S is complex Fourier frequency, Th is RC time constant.A and Ti is respectively
The amplification of integrator and time constant, here, for realizing the emulation of Fig. 1, we add time constant generator mould
Block, it is made up of resistance and condenser type multistage connection in series-parallel loop, in order to produce different RC time constants, and is applied in Fig. 1
The Th of detector amplifier and the Ti of integrator.
In the integrator of Fig. 1, for simplifying simulation scenarios, we have a mind to arrange amplification A of integrator is infinity,
The transmission function that can approximate understanding integrator when A is the biggest is 1/STi.Definition:
(1)
Then the analogue system open-loop gain of Fig. 1 is:
(2)
The stable state output frequency of simulation excitation source generator is represented by:
(3)
System, after loop work reaches stable state, generally has G (s) " 1, so (3) formula can be written into:
(4)
From (4) formula, the stable state output frequency of simulation excitation source generator should be equal to high stable reference source in the ideal situation
After frequency dividing, frequency values has a multiple proportion:
(5)
Design parameter in the present invention is:
1, multiple proportion
Should join with high stable for realizing the stable state output frequency of the theoretical simulation excitation source generator expressed in Fig. 1 and formula (5)
Examine the multiple proportion between source frequency value, and above-mentioned relation is a dynamic equilibrium, it would be desirable to by the centre in Fig. 1
The work of whole system coordinated by reason device, and temporarily defining this task parameters at this is X, after can elaborate.
2, time constant
The setting of formula (5) and above-mentioned X parameter is theoretical, because in the PLL phase-locked loop that actual Fig. 1 is constituted, due to
In the frequency difference of high steady reference source self and PLL loop, the error of each several part exists, and the output frequency of Fig. 1 and its nominal value always have one
Determine deviation.The deviation of simulation excitation generator end and aging, integrator null offset, doubler phase place change etc. all may produce
This deviation.AllThe long term drift of item is all likely to result in the catabiosis of output frequency, becomes additional noise.
Open-loop gain G (s) should be improved for reducing the error of above-mentioned electronic circuitry part as far as possible.For the sake of convenient simulation, we
The most unified by Fig. 1,,,,Every error is set to fixed value.Imitate for improving Fig. 1
The performance of true system, should make open-loop gain G (s) become big theoretically as far as possible, make the molecule in formula (2)
Become big, but actually G0 should have the limit.It is generally acknowledged that the damped coefficient of system is no less than 0.5, then
(6)
For the sake of so convenient, we set G0=1, make Th=Ti simultaneously.The method realized is:
(1), it is respectively provided with detector amplifier, simulation excitation generator, doubler by the central controller in Fig. 1、, M, makeEqual to 1；
(2), be respectively provided with detector amplifier by the central controller in Fig. 1, time constant Th=Ti that integrator is corresponding.
After above-mentioned setting, the open-loop gain of Fig. 1 analogue system that formula (2) is stated is:
(7)
3, analogue system Q-value
Reducing time constant Th, really increase the open-loop gain of analogue system according to formula (7), this is advantageous for systematic function
, this increases loop filter bandwidth fh the most simultaneously.Fig. 1 is high, and steady reference source is equivalent to a descriminator, when its long term drift can
During to ignore, it is assumed that its power-law noise formula is:
(8)
Fig. 1 loop work under theoretical case is at linear condition, if it is believed that simulation excitation generator and height steady reference source merit
Rate spectrum density (Sy (f) OSC with Sy (f) REF) is the most uncorrelated, then Fig. 1 system output power spectrum density can represent
For:
(9)
According to definition, Wo Menyou, therefore, (8) formula substitute into (9) formula it is seen that,
When emulation average period the most in short-term,, have
(10)
When the average period of emulation is the longest, have
(11)
Obviously, whole loop is a high pass filter for simulation excitation generator；It is one for reference source steady with height
Individual low pass filter；Its filtering characteristic is determined by the high end cut-off frequencies fh of loop filter.(10) extreme case of formula is, the extreme case of (11) formula is.It can be seen that fh crosses senior general makes Fig. 1's
Analogue system output signal short-term stability is deteriorated；Fh is too small to be deteriorated the analogue system output signal long-term stability making Fig. 1.
After Fig. 1 system closed loop, we are the loop bandwidth i.e. high end cut-off frequencies fh that cannot learn system, and we carry out table with Q-value
Levy the stabilization signal of the analogue system output signal of Fig. 1, and draw sign system Q by the frequency stabilization tester measurement in Fig. 1
The simulation results of value, thus indirectly the value of the i.e. high end cut-off frequencies fh of reaction loop bandwidth selects quality.
Compared with prior art, the invention has the beneficial effects as follows: present configuration is simple, reasonable in design, it is possible to effectively
Improving simulation calculation precision, use programme-control simultaneously, automaticity is higher, uses more convenient, improves analogue system
Simulated performance.
Accompanying drawing explanation
Fig. 1 is the structural representation of the present invention；
Fig. 2 is analogue system circuit diagram of the present invention；
Fig. 3 is analogue system signal judgement figure in the present invention；
Fig. 4 is analogue system strategy anticipation trendgram in the embodiment of the present invention；
Fig. 5 is analogue system strategy anticipation trendgram in another embodiment of the present invention.
Detailed description of the invention
In order to make the purpose of the present invention, technical scheme and advantage clearer, below in conjunction with drawings and Examples, right
The present invention is further elaborated.Should be appreciated that specific embodiment described herein only in order to explain the present invention, and
It is not used in the restriction present invention.
Referring to Fig. 1-5, Fig. 1 is the structural representation of the present invention, and Fig. 2 is analogue system circuit diagram of the present invention, and Fig. 3 is this
In invention, analogue system signal judges figure, and Fig. 4 is analogue system strategy anticipation trendgram in the embodiment of the present invention, and Fig. 5 is this
Optical frequency shift-light intensity test curve in another embodiment bright.
Bounce-back high q-factor digital P LL phaselocked loop analogue system, including central processing unit, time constant generator, frequency dividing
Device, detector amplifier, integrator, simulation excitation source generator, frequency stabilization tester and doubler；Described frequency divider connects detection
Amplifier, described detector amplifier connects integrator, and described integrator connects central controller；Described central controller is even
It is connected to simulation excitation source generator, doubler, frequency stabilization tester and time constant generator；Described simulation excitation source generator is even
Being connected to frequency stabilization tester, described doubler connects simulation excitation source generator and frequency divider；Described time constant generator is divided
Do not connect with detector amplifier, integrator.
The mode realizing parameters employing in the present invention is:
Multiple proportion strategy:
In Fig. 1 system, the frequency range that our Simulation Model pre-sets is as follows:
(1), for realizing the simulated response of high band, we select the high steady reference source that frequency is higher, after the scaling down processing of Fig. 1
The signal frequency obtained is 50.****MHz.Wherein * * * * (remaining into four) of decimal place is random, rises for convenience of description
Seeing, in this patent is implemented, we take * * * *=1234, i.e. in Fig. 1For 50.1234MHz；
(2) the initialization simulation excitation generator output 10MHz frequency signal that, central controller is arranged；
(3), central controller arrange initialization doubler output signal frequency withTheoretical value is identical, is the most also
50.1234MHz；
(4), simulation excitation generator output signal frequency and doubler output signal frequency have linkage connection.
Realize the circuit structure of above-mentioned model as shown in Figure 2:
In central controller module during wherein processor is positioned at Fig. 1, and DDS1, the DDS2 in processor XTAL end and Fig. 2
RefClk terminate the frequency signal into same clock source, from synchronization during to ensure.Processor is at outside input end of clock
(XTAL), on the basis of as clock reference during work, the three adjustable square-wave signals of road phase relation, Qi Zhongyi are produced respectively
Road keying FM signal is delivered to the FSK keying frequency modulation input port of DDS1 and is realized frequency modulation, a road synchronous reference signal as synchronizing
Phase demodulation, a road judgement are used as the lock-in detection of Fig. 1 phaselocked loop with signal.DDS1 makees outside clock reference input (RefClk)
On the basis of reference clock during work, by the serial sequential communication between processor and DDS1, DDS1 is according to FSK end processor
The high and low level state of the square wave keying frequency modulation square-wave signal sent here is chosen internal frequency respectively and is controlled in depositor (F1, F0)
The multiple-frequency modulation data presetting frequency of processor input as output, thus produce the frequency signal 50.1234MHz of band modulation ±
△ f exports.Preset frequency-splitting △ f is determined by the numerical value in two frequency control register F1, F0, concrete in view of penetrating
Frequently the 4th precision after signal is 50.1234MHz(arithmetic point), we take △ f=100Hz.Control DDS1 with above-mentioned processor to produce
The principle of raw multiple-frequency modulation signal is similar to, and processor passes through serial communication sequential, and same frequency dividing numerical value is passed to DDS2, produces
The raw 50.1234MHz frequency signal output without modulation.The 50.1234MHz frequency signal obtained by DDS2 is sent into outside DDS3
Portion's clock reference input (RefClk), reference clock when working as DDS3.Processor is according to serial sequential communication, by phase
Initialization output frequency (10MHz) numerical value answered passes to DDS3, thus obtains the output of simulation excitation source generator frequency signal.
Owing to during the external reference of DDS3, base uses the frequency-doubled signal that DDS2 produces, therefore in this programme, when in the closed circuit in Fig. 1
Central controller obtain corresponding phase discrimination signal information after, the frequency of the multiple-frequency modulation signal of corresponding DDS2 can be revised, this
Sample also can cause the frequency of DDS3 output signal to change, and i.e. instead of traditional changing by the way of D/A VCXO
Become the output frequency value of local oscillator, and then the method changing system output frequency.It should be noted that and output frequency signal is adopted
Mode with direct digital synthesizers so that act as a higher synthesizer role of degree of stability in certain range of application.
User by user input mouth in Fig. 2, can revise the complete machine output letter of DDS3 according to the requirement in reality application easily
Number frequency values.
Time constant Provisioning Policy
From aforementioned schemes, we setEqual to 1, make Th=Ti simultaneously.According to above-mentioned multiple proportion strategy,
Frequency after the signal frequency that we make simulation excitation source generator export is 10MHz, high steady reference source divides is chosen as
50.1234MHz, according to formula (5), M=5 can be obtained.From above-mentioned multiple proportion strategy, we are in design
In the analogue system of Fig. 1 and be provided without traditional changing system output frequency value method, institute by the way of D/A VCXO
With in Fig. 1The voltage-controlled slope of simulation excitation generator cannot be known, we can only pass throughDeng
In 1 and obtained by M=5*The conclusion of=1/5.In concrete implementation process, during according to Fig. 1, we can only pass through
Detector amplifier is carried out by centre controllerThe setting of value.Owing to the time constant in analogue system is only determined by Th, institute
So that according to Fig. 1, we pass through the central controller control realization to time constant generator to detector amplifier, the inspection of integrator
Ripple time constant Th and the setting of integration time constant Ti, and make Th=Ti.
Analogue system Q-value strategy
We produce three road square-wave signals by processor in fig. 2: synchronous reference signal, keying FM signal, judgement are believed
Number, make synchronous reference signal frequency be equal to keying FM signal frequency, and have certain phase delay poor；Make judgement believe simultaneously
Number frequency N(N value can be between 8 to 20) times synchronous reference signal frequency or keying FM signal frequency, and have certain
Phase delay poor.It is 169Hz that the most concrete we take synchronous reference signal frequency equal to keying FM signal frequency, and two
Person's phase contrast is 160 degree；Take judgement signal frequency N value is 8 times simultaneously, and is 90 degree with synchronous reference signal phase contrast.
Concrete judgment basis is as shown in Figure 3:
In Fig. 3, judgement signal, synchronous reference signal, keying FM signal are the square wave numerals having fixed frequency and phase relation
Signal；Enable signal to be 1 or be 0, therefore can be regarded as the square wave digital signal without fixed frequency；Phase discrimination signal by
Integrator in Fig. 1 produces, and it is the direct current signal of a change, therefore can be regarded as the analogue signal without fixed frequency.
Combining Fig. 1 according to the principle of Fig. 3, we set a certain rising edge of judgement signal and start as triggering judgement,
Before next rising edge arrives, complete 10 times judge, when then next rising edge arrives, trigger again next group and judge for 10 times.By
The frequency of judgement signal in Fig. 3 is known in advance in us, i.e. it is understood that time T between adjacent two rising edges, therefore can
With one group of time interval judged for 10 times of mean allocation.
In Fig. 1, central controller is according to above-mentioned triggering Rule of judgment, judges the phase discrimination signal carried by integrator,
When its analog DC signal magnitude is positioned at the non-enable banded regions shown in Fig. 3, central controller exports the enable letter in Fig. 3
Number being 0, the steady measuring instrument of frequency in Fig. 1 does not works；When outside the non-enable banded regions that its analog DC signal magnitude is positioned at shown in Fig. 3
Time, the enable signal that central controller exports in Fig. 3 is 1, and the steady measuring instrument of frequency in Fig. 1 is started working；Emulation Q-value is the most just
The simulation results value of output when being the work of Fig. 1 intermediate frequency steady measuring instrument, it reflects the property of Fig. 1 analogue system output signal
Can,
During whole emulation, central controller, when starting, initializes all of value to be arranged, and these parameters are the most no longer
Change, during dynamic simulation, only have detector amplifier parameterValue, detector amplifier time constant Th value must be controlled by central authorities
Device module processed is dynamically arranged, and judges that the two parameter the most reasonably criterion is then emulation Q-value.We giveValue takes scope 1-10, same Th we also take a 1-10.When Fig. 1 system emulates at the beginning, except setting each road
Outside Initialize installation value, we exist in meetingValue and the emulation of Th value gamut obtain the Q-value of correspondence for one time, and Q-value is positioned at L and H
Between, it is defined as L=1 to H=100(Q value and is the bigger the better), we define the Q-value data in this section of simulation time is " modeling district ".
In dynamic simulation process, in most cases system is carried out according to Fig. 3 institute principle.Below additionally we implement
" bounce-back " property of two tactful evaluation systems and " high Q " property, first we compress the Q-value of above-mentioned acquisition, take Q-value scope at (L=
25 to L=50) it is defined as strategy value district Q1, central controller is arrangedIt is worth and Th value, and the time of sampling Q-value is to synchronize
, and make settingChanging in the opposite direction of value and Th value:
The first situation: next time arrangeValue (being designated as K2) is compared with thisValue (being designated as K1) be to increase (i.e. K2 >
K1), then arrange Th value (being designated as T2) then relatively this Th value (being designated as T1) is to reduce (i.e. T2 < T1) next time.
The second situation: next time arrangeValue (being designated as K2) is compared with thisValue (being designated as K1) is to reduce (i.e.
K2<K1), then Th value (being designated as T2) (i.e. T2>T1) that then relatively this Th value (being designated as T1) is to increase is set next time.
It should be noted is that: central controller be at any time carry out emulating according to above-mentioned two kinds of situations.On having had
The operating mechanism stated, we have a following two strategy:
Embodiment one: according to above-mentioned emulation, first obtaining " the modeling district " of system q, as shown in Figure 4, then system is randomly
Enter the first situation above-mentioned or the second situation.When the emulation Q-value of system is more than H, i.e. at some O in Fig. 4, the most now
System is in the first situation or the second situation, and we will put system in the first situation state, i.e. increaseValue is same
Time reduce Th value, and make the parameter of increase trendValue variable quantity increases to original 2 times, arranges the most next timeValue is the above-mentioned 2*(K2-K1 of change in the case of the first), the changing value that arranges of Th value is original (T2-simultaneously
T1), we are defined as the third situation.Analogue system emulates according to the 4th kind of situation always, as shown in Figure 4, and emulation knot
Along the virtual policy in figure, fruit will judge that Trendline is carried out to a certain H1, in theory in advance until occurring that Q-value declines, then I
Recover original facilities,
Embodiment two: according to above-mentioned emulation, first obtains " the modeling district " of system q, as it is shown in figure 5, then system is randomly
Enter the first situation above-mentioned or the second situation.When system emulation Q-value occurs at L1=25, and three Q-value of continuous print
Occurring rising, and rise at more than 33 (at the some O in Fig. 5), the most now system is in the first situation or the second
Situation, we will put system in the second situation state, i.e. reduceValue increases Th value simultaneously, and makes increase trend
Parameter Th value variable quantity increases to original 2 times, and arrange Th value is the 2*(T2-of change in the case of above-mentioned the second the most next time
T1), simultaneouslyThe changing value that arranges be original (K2-K1), we are defined as the third situation.Analogue system is pressed always
Emulate according to the third situation, as it is shown in figure 5, simulation result will judge Trendline along the virtual policy in figure in theory in advance
Carry out to a certain H1, until occurring that Q-value declines, then we recover original facilities.
The foregoing is only presently preferred embodiments of the present invention, not in order to limit the present invention, all essences in the present invention
Any amendment, equivalent and the improvement etc. made within god and principle, should be included within the scope of the present invention.
Claims (7)
1. bounce-back high q-factor digital P LL phaselocked loop analogue system, it is characterised in that: include that central processing unit, time constant occur
Device, frequency divider, detector amplifier, integrator, simulation excitation source generator, frequency stabilization tester and doubler；Described frequency divider is even
Being connected to detector amplifier, described detector amplifier connects integrator, and described integrator connects central controller；Described central authorities
Controller connects simulation excitation source generator, doubler, frequency stabilization tester and time constant generator；Described simulation excitation source
Generator connects frequency stabilization tester, and described doubler connects simulation excitation source generator and frequency divider；Described time constant
Generator connects with detector amplifier, integrator respectively.
Bounce-back high q-factor digital P LL phaselocked loop analogue system the most according to claim 1, it is characterised in that: the described time
Constant generator is made up of resistance and condenser type multistage connection in series-parallel loop.
Bounce-back high q-factor digital P LL phaselocked loop analogue system the most according to claim 1, it is characterised in that: described central authorities
Time constant Th=Ti that controller is respectively provided with detector amplifier, integrator is corresponding.
Bounce-back high q-factor digital P LL phaselocked loop analogue system the most according to claim 1, it is characterised in that: the control of described central authorities
Device processed is respectively provided with detector amplifier, simulation excitation generator, doubler、, M, makeDeng
In 1.
Bounce-back high q-factor digital P LL phaselocked loop analogue system the most according to claim 1, it is characterised in that: described central authorities
The initialization simulation excitation generator output 10MHz frequency signal that controller is arranged.
Bounce-back high q-factor digital P LL phaselocked loop analogue system the most according to claim 1, it is characterised in that: described central authorities
Controller arrange initialization doubler output signal frequency withTheoretical value is identical, is the most also 50.1234MHz.
Bounce-back high q-factor digital P LL phaselocked loop analogue system the most according to claim 1, it is characterised in that: simulation excitation
Generator output signal frequency and doubler output signal frequency have linkage connection.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610228474.0A CN105938330A (en) | 2016-04-13 | 2016-04-13 | Rebounding high-Q-value digital PLL simulation system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610228474.0A CN105938330A (en) | 2016-04-13 | 2016-04-13 | Rebounding high-Q-value digital PLL simulation system |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN105938330A true CN105938330A (en) | 2016-09-14 |
Family
ID=57152012
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610228474.0A Pending CN105938330A (en) | 2016-04-13 | 2016-04-13 | Rebounding high-Q-value digital PLL simulation system |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN105938330A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106941353A (en) * | 2017-02-21 | 2017-07-11 | 江汉大学 | A kind of time-domain signal optimization Simulation system |
| CN106953635A (en) * | 2017-02-21 | 2017-07-14 | 江汉大学 | A kind of frequency source modeling method and system |
| CN107918054A (en) * | 2017-11-01 | 2018-04-17 | 江汉大学 | A kind of time-domain signal optimization system |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN2669485Y (en) * | 2003-11-18 | 2005-01-05 | 港湾网络有限公司 | Apparatus for realizing high-precision three-level clock |
| US20050129099A1 (en) * | 2003-11-21 | 2005-06-16 | Philipp Borker | Arrangement for generating a transmission clock signal and a reception clock signal for a transceiver |
| CN101079630A (en) * | 2006-05-23 | 2007-11-28 | 中兴通讯股份有限公司 | A digital phase lock loop device for smooth switching of clock phase and its method |
| CN101083523A (en) * | 2007-07-27 | 2007-12-05 | 华南理工大学 | Method for realizing integrated time stamp clock synchronous phase-locked loop |
| US7907019B1 (en) * | 2008-10-01 | 2011-03-15 | National Semiconductor Corporation | Method and system for operating a MEMS scanner on a resonant mode frequency |
| CN202026300U (en) * | 2011-04-06 | 2011-11-02 | 江汉大学 | Direct digital synthesizer and synchronous phase discrimination circuit device for direct digital synthesizer |
| US20120256694A1 (en) * | 2011-04-08 | 2012-10-11 | Stephen Fulton Smith | Orthogonally referenced integrated ensemble for navigation and timing |
| CN205563133U (en) * | 2016-04-13 | 2016-09-07 | 江汉大学 | Digital PLL phase -locked loop simulation system of high Q value that rebounds |
-
2016
- 2016-04-13 CN CN201610228474.0A patent/CN105938330A/en active Pending
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN2669485Y (en) * | 2003-11-18 | 2005-01-05 | 港湾网络有限公司 | Apparatus for realizing high-precision three-level clock |
| US20050129099A1 (en) * | 2003-11-21 | 2005-06-16 | Philipp Borker | Arrangement for generating a transmission clock signal and a reception clock signal for a transceiver |
| CN101079630A (en) * | 2006-05-23 | 2007-11-28 | 中兴通讯股份有限公司 | A digital phase lock loop device for smooth switching of clock phase and its method |
| CN101083523A (en) * | 2007-07-27 | 2007-12-05 | 华南理工大学 | Method for realizing integrated time stamp clock synchronous phase-locked loop |
| US7907019B1 (en) * | 2008-10-01 | 2011-03-15 | National Semiconductor Corporation | Method and system for operating a MEMS scanner on a resonant mode frequency |
| CN202026300U (en) * | 2011-04-06 | 2011-11-02 | 江汉大学 | Direct digital synthesizer and synchronous phase discrimination circuit device for direct digital synthesizer |
| US20120256694A1 (en) * | 2011-04-08 | 2012-10-11 | Stephen Fulton Smith | Orthogonally referenced integrated ensemble for navigation and timing |
| CN205563133U (en) * | 2016-04-13 | 2016-09-07 | 江汉大学 | Digital PLL phase -locked loop simulation system of high Q value that rebounds |
Non-Patent Citations (4)
| Title |
|---|
| 何存富: "《超声导波任意波形脉冲激励源的设计与实现》", 《测控技术》 * |
| 吴士云: "《DDS +PLL 高性能频率合成器的设计与实现》", 《现代电子技术》 * |
| 吴士云: "《基于DDS+PLL的高性能微波频率合成器的研制》", 《中国优秀硕士学位论文全文数据库（电子期刊）》 * |
| 陈科等: "《基于DDS+PLL技术频率合成器的设计与实现》", 《国外电子测量技术》 * |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106941353A (en) * | 2017-02-21 | 2017-07-11 | 江汉大学 | A kind of time-domain signal optimization Simulation system |
| CN106953635A (en) * | 2017-02-21 | 2017-07-14 | 江汉大学 | A kind of frequency source modeling method and system |
| CN107918054A (en) * | 2017-11-01 | 2018-04-17 | 江汉大学 | A kind of time-domain signal optimization system |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103957007B (en) | Random waveform weak signal detection method and system under low signal to noise ratio | |
| CN207720116U (en) | A kind of digital delay phase-locked loop of quick lock in | |
| US8629701B2 (en) | PLL bandwidth correction with offset compensation | |
| CN105938330A (en) | Rebounding high-Q-value digital PLL simulation system | |
| EP3931967A1 (en) | Circuit and method for determining the ratio between two frequencies | |
| US20200091922A1 (en) | Device for adjusting the locking of an injection locked frequency multiplier | |
| CN204633753U (en) | Based on HMC835 broadband Low phase noise low spurious frequency hopping synthesizer | |
| CN107896106A (en) | Adjust the phase of digital phase locked loop | |
| CN205563133U (en) | Digital PLL phase -locked loop simulation system of high Q value that rebounds | |
| Jiang et al. | PLL low pass filter design considering unified specification constraints | |
| US8332200B2 (en) | Method and simulator for generating phase noise in system with phase-locked loop | |
| CN104242931B (en) | The all-digital phase-locked loop and implementation method of a kind of quick lock in | |
| CN101567689A (en) | Phase-locked loop based on equivalent phase demodulation frequency | |
| CN106199184A (en) | A kind of spectrum analyzer with quick phase-locked function | |
| CN106941353A (en) | A kind of time-domain signal optimization Simulation system | |
| Kacharmina et al. | Pulse phase-frequency detectors in high-speed frequency synthesizers | |
| Huque et al. | An exact formula for the pull-out frequency of a 2nd-order type II phase lock loop | |
| CN202713275U (en) | Narrowband frequency-adjustable PLL oscillation circuit | |
| CN107918054A (en) | A kind of time-domain signal optimization system | |
| Kavyashree et al. | Implementation of all digital phase locked loop | |
| US4450410A (en) | Phase-lock loop control circuitry | |
| Qingping et al. | ADF4350-based Frequency Modulation transmitter design | |
| CN106953635A (en) | A kind of frequency source modeling method and system | |
| CN104135252B (en) | A kind of any external reference time base circuit of low noise and time base generation method | |
| Li et al. | Design of x-band low phase noise and low spurious frequency source based on HMC778 |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| WD01 | Invention patent application deemed withdrawn after publication | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20160914 |