CN202026300U - Direct digital synthesizer and synchronous phase discrimination circuit device for direct digital synthesizer - Google Patents
Direct digital synthesizer and synchronous phase discrimination circuit device for direct digital synthesizer Download PDFInfo
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- CN202026300U CN202026300U CN2011200979220U CN201120097922U CN202026300U CN 202026300 U CN202026300 U CN 202026300U CN 2011200979220 U CN2011200979220 U CN 2011200979220U CN 201120097922 U CN201120097922 U CN 201120097922U CN 202026300 U CN202026300 U CN 202026300U
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Abstract
The utility model discloses a synchronous phase discrimination circuit device for a DDS (direct digital synthesizer), which comprises a user frequency discrimination loop connected with the output end of the DDS, a voltage controlled crystal oscillator connected with a reference frequency source input end of the DDS and a microprocessor used for generating a synchronous phase discrimination signal and a frequency shift keying modulating signal, wherein the microprocessor is respectively connected with the output end of the user frequency discrimination loop, the frequency control input end and the modulating signal input end of the DDS as well as the control end and the output end of the voltage controlled crystal oscillator. The utility model also discloses a DDS with the synchronous phase discrimination circuit device. With the adoption of the synchronous phase discrimination circuit device for the DDS and the DDS, the stability of a synthesized frequency output by the DDS can be effectively improved.
Description
Technical field
The utility model relates to electronic technology field, relates in particular to a kind of DDS of being used for (Direct Digital Synthesizer, Direct Digital Frequency Synthesizers) and synchronous phase discriminator device thereof.
Background technology
Compare with traditional frequency synthesizer, DDS has advantages such as low cost, low-power consumption, high-resolution and quick change-over time, has been widely used in telecommunications and electronic instrument field.As shown in Figure 1, DDS mainly is made up of reference frequency source, phase accumulator, memory (storage SIN function menu), D/A (D/A) transducer and low pass filter.The operation principle of this DDS is as follows: take a sample according to Nyquist, from the phase place of continuous signal a sinusoidal signal is taken a sample, quantizes, encoded, form described SIN function menu, exist among the EPROM (Erasable Programmable ROM, erasable programmable ROM).During frequency synthesis, by changing the frequency control word of phase accumulator, change phase increment, the phase increment difference will cause the difference of the number of sampling in the week.Because of angular frequency
Under the constant situation of sampling frequency, by changing the frequency control word of phase accumulator, with the digital signal of the phase place/amplitude quantization of this variation, the frequency analog signal of the phase change that can obtain synthesizing by D/A conversion and low pass filter.
From the above description as can be seen, DDS carries out phase-samplomh with the external clock reference frequency to the signal that will synthesize, and sampling amount is big more in the unit interval, and then He Cheng frequency is low more.The size of sampling amount is by program-controlled frequency setting data, promptly aforementioned frequency control word decision, therefore in the DDS system, can realize higher resolution by setting data easily.As previously mentioned, reference frequency source is in order to the work of each parts among the synchronous DDS, so the frequency stability of the composite signal of DDS output is the same with reference frequency source.Like this, for the occasion of ask for something high stability index, DDS just must use the external clock reference frequency source of high stable as the reference clock signal.
The utility model content
The technical problems to be solved in the utility model is to provide high DDS of a kind of stability of frequency synthesis of output and phase discriminator device synchronously thereof.
In order to solve the problems of the technologies described above, the utility model provides the synchronous phase discriminator device of a kind of DDS of being used for, it comprises: the user's frequency discrimination loop that links to each other with the output of described Direct Digital Frequency Synthesizers, the VCXO that links to each other with the reference frequency source input of described Direct Digital Frequency Synthesizers, with the microprocessor that is used to produce synchronous phase discrimination signal and frequency shift keying modulation signal, described microprocessor respectively with the output of described user's frequency discrimination loop, the frequency control word input of described Direct Digital Frequency Synthesizers and modulation signal input, and the control end of described VCXO links to each other with output.
Alternatively, be provided with phase-locked loop in the described DDS, the frequency of the reference frequency source input of described DDS input is higher than 4 times of output of described DDS.
Preferably, two of described DDS phase adjusted end ground connection.
Further, described modulation signal is that duty ratio is 1: 1 a square-wave signal, and described synchronous phase discrimination signal is rectangular signal and with described modulation signal fixed phase relation is arranged.
Preferably, described user's frequency discrimination loop is a phase-locked loop.
The utility model also provides a kind of DDS, comprise the phase accumulator that connects successively, memory, D/A converter and low pass filter, the user's frequency discrimination loop that links to each other with the output of described low pass filter, the VCXO that is connected with D/A converter with described phase accumulator, with the microprocessor that is used to produce synchronous phase discrimination signal and frequency shift keying modulation signal, described microprocessor respectively with the output of described user's frequency discrimination loop, the frequency control word input of described phase accumulator and modulation signal input, and the control end of described VCXO links to each other with output.
In DDS of the present utility model and the synchronous phase discriminator device thereof, the radiofrequency signal of DDS output is finished the frequency discrimination of DDS radiofrequency signal and user side measured signal and is handled through user's frequency discrimination loop, obtains corresponding frequency discrimination signal, is sent to microprocessor; Microprocessor has together the synchronous frequency discrimination signal and the aforementioned frequency discrimination signal of homophase frequently according to the modulation signal with DDS, carry out synchronous phase discrimination processing, obtain corresponding voltage-controlled signal and act on described VCXO, thereby change the frequency signal output of VCXO, just change the frequency of DDS external reference clock, whole system is finished closed loop, thereby can improve the stability of the frequency signal of DDS output.
Description of drawings
Fig. 1 is the theory diagram of DDS;
Fig. 2 is used for the structural representation of an embodiment of the synchronous phase discriminator device of DDS for the utility model;
Fig. 3 is the port schematic diagram of DDS among Fig. 2;
Fig. 4 is microprocessor among Fig. 2 and the communication sequential schematic diagram of DDS;
Fig. 5 is the oscillogram of the modulation signal and the synchronous phase discrimination signal of microprocessor generation among Fig. 2;
Fig. 6 is the structural representation of the embodiment of the utility model DDS.
In order to make the technical solution of the utility model clearer, clear, be described in further detail below in conjunction with accompanying drawing.
Embodiment
The utility model provides a kind of high DDS and synchronous phase discriminator device thereof of stability of frequency synthesis of output.
Fig. 2 is used for the structural representation of an embodiment of the synchronous phase discriminator device of DDS for the utility model, present embodiment is that example illustrates structure of the present utility model with the AD9832 chip.Referring to Fig. 2 and Fig. 3, the synchronous phase discriminator device that is used for DDS of present embodiment comprises user's frequency discrimination loop 21, microprocessor 22 and VCXO 23.Described user's frequency discrimination loop 21 links to each other with the output of described DDS24, described VCXO 23 links to each other with the reference frequency source input MCLK of described DDS24, described microprocessor 22 respectively with frequency control word input FSYNC, SCLK, SDATA and the modulation signal input FSELECT of the output of described user's frequency discrimination loop 21, described DDS, and the control end of described VCXO 23 link to each other with output.Described user's frequency discrimination loop can need the loop of frequency discrimination for PLL (Phase Lock Loop, phase-locked loop) etc., by importing different frequency values, obtains different output valves, such as voltage signal.
Particularly, there are two FREQUENCY CONTROL registers described DDS24 inside, mode by programming is kept at frequency value F 0, the F1 that pre-sets in the register, when modulation signal input FSELECT has the square-wave signal input (electrical level rising edge or trailing edge conversion), the IOUT end of DDS will be read F1 or F0 respectively thereupon from the FREQUENCY CONTROL register value is as output, and the phase place no change of meeting inhibit signal.The sequential of the serial communication of described microprocessor 22 and described DDS24 as shown in Figure 3.When FSYNC was high level, SCLK, SDATA pin were high-impedance state.When FSYNC is low level, DDS will be in communication state, when this moment, pin SCLK had the pulse of a trailing edge, to make the DATA that hangs on the data/address bus SDATA write the DDS data buffer zone, write fashionablely until a final DATA, DDS will select F1 or the F0 output as the IOUT end according to the state on the pin FSELECT.
Preferably, in order to keep F1, the F0 phase place when switching continuous, so direct two phase adjusted end PSEL0, PSEL1 ground connection with DDS.
Alternatively, can be provided with PLL frequency multiplication module among the described DDS, also can not have PLL frequency multiplication module.If be provided with PLL frequency multiplication module among the DDS, the frequency of then described reference frequency source input MLCK input should be higher than 4 times of output signal frequency of described Direct Digital Frequency Synthesizers, as output frequency is 5MHz, the signal frequency of MCLK end should be greater than 20MHz so, obtain better phase noise with expectation, behind the filtered external circuit, can obtain purer signal spectra.And for not having the DDS of PLL frequency multiplication module in inside, the external clock frequency of reference frequency source input MCLK input is the clock frequency of DDS system, is example with output 5MHz frequency signal, and the signal frequency of MCLK end is 20MHz.There are 2 32 bit frequency control registers (F0, F1) DDS inside, and in above-mentioned serial communication sequential, the DATA position should be 32.Hence one can see that, and when this MCLK held outside input clock frequency 20MHz, the frequency resolution of the minimum of DDS was:
During IOUT output 20MHz, the value of 32 corresponding bit frequency control registers is 1 entirely; During output 5MHz, value corresponding is (5MHz/20MHz) * 232, resulting decimal value is converted into the value of the corresponding 32 bit frequency control registers of binary system.According to the serial communication sequential, corresponding 32 place values are written to (as F0) in the correspondent frequency control register by microprocessor.Same principle, another road single-frequency of modulation also can be written to (as F1) in the correspondent frequency control register with 32 place values by similar method.
Further, described modulation signal and synchronously phase discrimination signal relation as shown in Figure 5, described modulation signal A is that duty ratio is 1: 1 a square-wave signal, acts on the FSELECT end of DDS.The signal that wherein changes pin FSELECT level is produced by single-chip microcomputer.Described synchronous phase discrimination signal B and C are that duty ratio is non-1: 1 rectangular pulse and with described modulation signal A fixed phase relation is arranged.The generation of these signals is realized by corresponding clock interruption or branch frequency technology by microprocessor.
When design, can adopt the inner 16 bit timing devices of single-chip microcomputer to realize above-mentioned each road signal, the machine cycle of the actual single-chip microcomputer of selecting for use is 0.2mS.Define a variable T, circulate and realize. P2.0).In like manner, can (P2.2, P2.3) realize B and C two-way square-wave signal on other two pins of single-chip microcomputer, just B and C have certain phase shift with P2.0 on phase place, and duty ratio is not 1: 1 a square wave.The method that realizes is " time-delay ", i.e. digital phase shift." time-delay " is to realize by fixing machine execution cycle statement in single-chip microcomputer, the above-mentioned machine cycle of mentioning is by the decision of the frequency of the external timing signal that is added in the single-chip microcomputer clock end, also the execution cycle can be related in the execution of its tangible each bar statement, different statements can be respectively 1,2,4 machine cycles according to the difference of performed order behavior, but the cycle that same statement is carried out is fixed, and this is just for " " mechanism provides guarantee in time-delay.
The operation principle of the synchronous phase discriminator device that is used for DDS of present embodiment is described below in conjunction with Fig. 2, Fig. 3 and Fig. 4.The radiofrequency signal of DDS24 output is finished the frequency discrimination of DDS radiofrequency signal and user side measured signal and is handled through user's frequency discrimination loop 21, obtains corresponding frequency discrimination signal, is sent to microprocessor 22; Microprocessor 22 according to FSK (the Frequency-Shift Keying of DDS24, frequency shift keying) modulation signal has synchronous frequency discrimination signal and the aforementioned frequency discrimination signal with the frequency homophase, carry out synchronous phase discrimination processing, obtain corresponding voltage-controlled signal and act on described VCXO 21, thereby change the frequency signal output of VCXO 21, just change the frequency of DDS external reference clock, whole system is finished closed loop, thereby can improve the stability of the frequency signal of DDS output.
Fig. 6 is the structural representation of the embodiment of the utility model DDS.As shown in Figure 6, the DDS of present embodiment comprises the phase accumulator 61 that connects successively, memory 62, D/A converter 63 and low pass filter 64, the user's frequency discrimination loop 65 that links to each other with the output of described low pass filter 64, the VCXO 66 that is connected with D/A converter 63 with described phase accumulator 16, with the microprocessor 67 that is used to produce synchronous phase discrimination signal and frequency shift keying modulation signal, described microprocessor 67 respectively with the output of described user's frequency discrimination loop 65, the frequency control word input of described phase accumulator 61 and modulation signal input, and the control end of described VCXO 66 links to each other with output.Particularly, described user's frequency discrimination loop 65 can be phase-locked loop.Further, described modulation signal is that duty ratio is 1: 1 a square-wave signal, and described synchronous phase discrimination signal is rectangular signal and with described modulation signal fixed phase relation is arranged.
The radiofrequency signal of the low pass filter output of the DDS of present embodiment is finished the frequency discrimination of radiofrequency signal and user side measured signal and is handled through user's frequency discrimination loop 65, obtains corresponding frequency discrimination signal, is sent to microprocessor 67; Microprocessor 67 has together the synchronous frequency discrimination signal and the aforementioned frequency discrimination signal of homophase frequently according to the fsk modulated signal with DDS, carry out synchronous phase discrimination processing, obtain corresponding voltage-controlled signal and act on described VCXO 66, thereby change the frequency signal output of VCXO 66, just change the frequency of DDS external reference clock, whole system is finished closed loop, thereby can improve the stability of the frequency signal of DDS output.
Claims (8)
1. a synchronous phase discriminator device that is used for Direct Digital Frequency Synthesizers is characterized in that, comprising:
The user's frequency discrimination loop that links to each other with the output of described Direct Digital Frequency Synthesizers, the VCXO that links to each other with the reference frequency source input of described Direct Digital Frequency Synthesizers and the microprocessor that is used to produce synchronous phase discrimination signal and frequency shift keying modulation signal, described microprocessor link to each other with output with the frequency control word input of the output of described user's frequency discrimination loop, described Direct Digital Frequency Synthesizers and the control end of modulation signal input and described VCXO respectively.
2. synchronous phase discriminator device according to claim 1, it is characterized in that, be provided with phase-locked loop in the described Direct Digital Frequency Synthesizers, the frequency of the reference frequency source input of described Direct Digital Frequency Synthesizers input is higher than 4 times of output signal frequency of described Direct Digital Frequency Synthesizers.
3. synchronous phase discriminator device according to claim 2 is characterized in that, two phase adjusted end ground connection of described Direct Digital Frequency Synthesizers.
4. according to each described synchronous phase discriminator device of claim 1-3, it is characterized in that described modulation signal is that duty ratio is 1: 1 a square-wave signal, described synchronous phase discrimination signal is rectangular signal and with described modulation signal fixed phase relation is arranged.
5. synchronous phase discriminator device according to claim 4 is characterized in that, described user's frequency discrimination loop is a phase-locked loop.
6. Direct Digital Frequency Synthesizers, comprise the phase accumulator that connects successively, memory, D/A converter and low pass filter, it is characterized in that, also comprise the user's frequency discrimination loop that links to each other with the output of described low pass filter, the VCXO that is connected with D/A converter with described phase accumulator, with the microprocessor that is used to produce synchronous phase discrimination signal and frequency shift keying modulation signal, described microprocessor respectively with the output of described user's frequency discrimination loop, the frequency control word input of described phase accumulator and modulation signal input, and the control end of described VCXO links to each other with output.
7. Direct Digital Frequency Synthesizers according to claim 6 is characterized in that, described modulation signal is that duty ratio is 1: 1 a square-wave signal, and described synchronous phase discrimination signal is rectangular signal and with described modulation signal fixed phase relation is arranged.
8. according to claim 6 or 7 described Direct Digital Frequency Synthesizers, it is characterized in that described user's frequency discrimination loop is a phase-locked loop.
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103163401A (en) * | 2013-01-31 | 2013-06-19 | 江汉大学 | Detection method of integrated machine performance suitable for atomic clock |
| CN103281076A (en) * | 2013-05-28 | 2013-09-04 | 中国人民解放军63921部队 | Clock source and signal processing method thereof |
| CN105938330A (en) * | 2016-04-13 | 2016-09-14 | 江汉大学 | Rebounding high-Q-value digital PLL simulation system |
| CN109474272A (en) * | 2017-09-07 | 2019-03-15 | 江汉大学 | A kind of temporal frequency signal source with synchronization signal output |
| CN111585567A (en) * | 2020-01-03 | 2020-08-25 | 石家庄数英仪器有限公司 | Rapid tracking synchronous sampling system with frequency holding function |
| CN116155275A (en) * | 2023-04-19 | 2023-05-23 | 成都世源频控技术股份有限公司 | Broadband fine stepping phase-locked source with repeatable phase |
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2011
- 2011-04-06 CN CN2011200979220U patent/CN202026300U/en not_active Expired - Fee Related
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103163401A (en) * | 2013-01-31 | 2013-06-19 | 江汉大学 | Detection method of integrated machine performance suitable for atomic clock |
| CN103163401B (en) * | 2013-01-31 | 2015-07-08 | 江汉大学 | Detection method of integrated machine performance suitable for atomic clock |
| CN103281076A (en) * | 2013-05-28 | 2013-09-04 | 中国人民解放军63921部队 | Clock source and signal processing method thereof |
| CN103281076B (en) * | 2013-05-28 | 2016-04-13 | 中国人民解放军63921部队 | A kind of method of clock source and signal transacting thereof |
| CN105938330A (en) * | 2016-04-13 | 2016-09-14 | 江汉大学 | Rebounding high-Q-value digital PLL simulation system |
| CN109474272A (en) * | 2017-09-07 | 2019-03-15 | 江汉大学 | A kind of temporal frequency signal source with synchronization signal output |
| CN111585567A (en) * | 2020-01-03 | 2020-08-25 | 石家庄数英仪器有限公司 | Rapid tracking synchronous sampling system with frequency holding function |
| CN116155275A (en) * | 2023-04-19 | 2023-05-23 | 成都世源频控技术股份有限公司 | Broadband fine stepping phase-locked source with repeatable phase |
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Granted publication date: 20111102 Termination date: 20130406 |