CN101276002A - High temperature monolithic phase programmable direct numerical frequency synthetic source - Google Patents
High temperature monolithic phase programmable direct numerical frequency synthetic source Download PDFInfo
- Publication number
- CN101276002A CN101276002A CNA2007100647897A CN200710064789A CN101276002A CN 101276002 A CN101276002 A CN 101276002A CN A2007100647897 A CNA2007100647897 A CN A2007100647897A CN 200710064789 A CN200710064789 A CN 200710064789A CN 101276002 A CN101276002 A CN 101276002A
- Authority
- CN
- China
- Prior art keywords
- phase
- frequency
- generates
- converter
- sampling address
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Abstract
The present invention discloses a high-temperature single-piece phase-programmable direct frequency synthesizing source. A phase accumulator accumulates the frequency data. A first quantitative waveshape memorizer outputs a corresponding waveshape data according to the sampling address and converts the waveshape data to a first local oscillation for outputting. A frequency control word decoding circuit generates the frequency data according to the frequency control code and transmits to the phase accumulator. A first adder receives the frequency accumulation result of the phase accumulator to generate a sampling address and transmits the sampling address to a first quantitative waveshape memorizer. A second adder receives a phase stepping amount and a frequency accumulation result and executes an additive operation a sampling result, and transmits the sampling result to a second quantitative waveshape memorizer. The second quantitative waveshape memorizer generates a corresponding waveshape data according to the sampling address and transmits to a second D/A converter. The second D/A converter and a second low-pass filter execute a digital-analog conversion and a low-pass filtering to the analog signal generated by the second D/A converter, and generates a second local oscillation for outputting.
Description
Technical field
The present invention relates to a kind of array phase induction logging instrument, specifically, relate to a kind of high temperature monolithic phase programmable direct numerical frequency synthetic source.
Background technology
The clock source of array phase induction logging instrument is the device that clock is provided for the receiver of array phase induction instrument aratus.Its function mainly is that the receiver for the array phase induction instrument aratus provides two-way same frequency clock, and wherein clock frequency is variable, and the phase differential of two-way clock signal also can be adjusted.
Induction instrument aratus clock source now usually way has two kinds, and first kind of way adopts the crystal oscillator of a plurality of different frequencies, satisfies the requirement of each Frequency point, the phase differential that obtains expecting by phase-shift circuit.
Second kind of way adopts the DDS chip to produce each Frequency point signal, the phase differential that obtains expecting by phase-shift circuit.Direct Digital formula frequency synthesis (DDS, Direct Digital Synthesis) technology is a kind of new frequency synthesis technique that develops rapidly along with the development of digital integrated circuit and computing machine in recent years.DDS generally is made up of phase accumulator, wave memorizer, digital to analog converter and low-pass filter, its ultimate principle stores Wave data earlier exactly, then under the effect of frequency control word M, from storer, read Wave data by phase accumulator, synthetic through output frequency after D/A switch and the low-pass filtering at last.This frequency combining method can obtain the frequency signal of high precision frequency and phase resolution, fast frequency switching time and low phase noise, and integrated level height simple in structure.
Direct digital frequency synthesis technology adopts digital mode to realize frequency synthesis, compares with traditional frequency synthesis technique, has following characteristics:
(1) frequency inverted is fast.The Direct Digital frequency synthesis is an open cycle system, no feedback element, and its frequency inverted time mainly changes the required time by the frequency control word state and the delay time of each circuit is determined that switching time is very short.
(2) frequency resolution height, frequency number are many.The resolution of DDS output frequency and frequency number are exponential increase with the growth of the figure place of totalizer.Resolution is up to μ Hz.
(3) phase place is continuous.DDS only need change frequency control word (totalizer totalizing step) when changing frequency, and need not change original accumulated value, so phase place is continuous during the change frequency.
(4) phase noise is little.The phase noise of DDS depends primarily on the phase noise of reference source.
(5) control is easy, reliable and stable.High integration, high speed and high reliability are the most tangible characteristics of FPGA/CPLD, and its clock delay can reach nanosecond, in conjunction with its concurrent working mode, aspect ultra-high speed applications field and the observing and controlling in real time boundless application prospect are being arranged.In highly reliable application,, will not exist reset unreliable and PC of similar MCU to run problem such as fly if design is proper.The high reliability of CPLD/FPGA also shows, almost total system can be integrated in the same chip, realizes so-called SOC (system on a chip), thereby has dwindled volume greatly, is easy to management and shielding.
To sum up, adopt FPGA to realize that DDS has tangible benefit, add present main flow fpga chip all integrated the PLL phaselock technique, to use FPGA in the application of DDS and PLL be only choosing so need at the same time to use.
With reference to shown in Figure 1, the DDS local oscillation circuit comprises DDS circuit, PLL circuit and frequency dividing circuit, at the control generation two-way local oscillation signal (local oscillation signal 1 and local oscillation signal 2) of reference clock.
With reference to shown in Figure 2, the principle of work of DDS is that the mode with digital controlled oscillator produces frequency, the controllable sine wave of phase place.The DDS circuit generally comprises reference clock, frequency accumulator, phase accumulator, amplitude/phase change-over circuit, D/A converter and low-pass filter (LPF).Frequency accumulator is carried out accumulating operation to input signal, produces frequency control data X (frequency data or phase step input).Phase accumulator is formed by N position full adder and the accumulator register cascade of N position, and 2 ary codes of representing frequency are carried out accumulating operation, is typical feedback circuit, produces accumulation result Y.The amplitude/phase change-over circuit comes down to a quantized waveform storer, for the use of tabling look-up.The data of reading are sent into D/A converter and low-pass filter.The concrete course of work is as follows: every time clock Fclk, the input end of accumulator register is delivered to the Y as a result after the addition in the phase data addition that adds up that N position totalizer is exported frequency control data X and accumulator register.The new phase data that accumulator register will be produced after a last clock period effects on the one hand feeds back to the input end of totalizer, so that totalizer continues under the effect of next clock and frequency control data X addition; On the other hand this value is sent into amplitude/phase change-over circuit (being the wave memorizer among Fig. 2-14) as the sampling address value, the amplitude/phase change-over circuit is exported corresponding Wave data according to this address.After D/A converter and low-pass filter convert Wave data to needed analog waveform.
Phase accumulator is at reference clock f
cAdd up under the effect, phase-accumulated stepping amplitude is determined by frequency control word M.If phase accumulator is N position (its accumulated value is K), frequency control word is M, and then the value of totalizer is after clock effect each: K
T+1=K
tIf+M is K
T+1＞2
N, then overflowing automatically, N is that the remainder in the totalizer keeps, and participates in and adds up next time.(A＜N) bit data has promptly been lost the address (being called Phase Accumulator Truncation again) of low level (N-A) as the address of wave memorizer, and the output of wave memorizer is exported after D/A conversion output and filtering with the high A in the totalizer output.
With reference to shown in Figure 3, if the precision that sinusoidal waveform navigates on the phase circle of position is the N position, then its resolving power is 1/2
N, promptly with f
cHits to basic waveform one-period is 2
NIf the stepping when phase-accumulated is M (frequency control word), then each clock f
cMake the value of phase accumulator increase M/2
N, promptly
Therefore the number of sampling of phase is 2 weekly
N/ M, then output frequency is f
0=(M/2
N) f
c
Bigger in order to improve waveform phase precision N value generally speaking, if directly with the address of N as wave memorizer, then require the memory span of employing very big, generally cast out the low level of N, the high A position (as high 16) of only getting N makes that as storage address the low level of phase place blocks (being Phase Accumulator Truncation).When phase value changes less than 1/2
NThe time, amplitude can't change, but the resolving power of output frequency can't reduce, and owing to the amplitude error that causes is blocked in the address, is called truncation error.
In the prior art, the method that adopts polycrystalline to shake need customize different frequency point crystal oscillator, cost height, circuit structure complexity; And adopt the DDS chip to produce the method for adjustable frequency signal, and being subjected to the restriction that the DDS chip has only the technical grade device, can not be operated in the hot environment of down-hole.And phase-moving method of the prior art owing to adopted phase-shift circuit, No. one phase-shift circuit can only produce a fixing phase differential, can not satisfy the requirement adjustable to the phase differential of clock source signals of array phase induction instrument aratus.Under first kind of situation, the crystal oscillator of each Frequency point need customize, and phase-shift circuit can only produce fixing phase differential.Under second kind of situation, the DDS chip is the technical grade device, can not satisfy the demand of well logging hot environment, and phase-shift circuit can only produce fixing phase differential.
Summary of the invention
Technical matters solved by the invention provides a kind of high temperature monolithic phase programmable direct numerical frequency synthetic source, can generate two-way same frequency and dephased output signal.
Technical scheme is as follows:
High temperature monolithic phase programmable direct numerical frequency synthetic source, comprise the DDS circuit, described DDS circuit comprises phase accumulator, the first quantized waveform storer, first D/A converter, first low-pass filter, described phase accumulator adds up frequency data, accumulation result is delivered to the described first quantized waveform storer as sampling address, the described first quantized waveform storer is exported corresponding Wave data according to described sampling address, convert described Wave data to needed first local oscillator output through D/A converter and low-pass filter, also comprise:
The frequency control word decoding scheme, the frequency control sign indicating number generated frequency data of root CPU, and send to described phase accumulator;
Phase differential control word decoding scheme, the phase differential of root CPU generates the phase step input, and sends;
First adder receives the frequency accumulation result of described phase accumulator, carries out additive operation and generates sampling address, and described sampling address is sent to the first quantized waveform storer;
Second adder receives the phase step input of described phase differential control word decoding scheme and the frequency accumulation result of described phase accumulator, carries out additive operation and generates sampling address, and described sampling address is sent to the described second quantized waveform storer;
The second quantized waveform storer, the sampling address that generates according to described second adder generates corresponding Wave data, sends to second D/A converter;
Second D/A converter, the Wave data that the described second quantized waveform storer is generated carries out digital-to-analog conversion, and transformation result is sent to second low-pass filter;
Second low-pass filter carries out low-pass filtering with the simulating signal that described second D/A converter generates, and generates the output of second local oscillator.
Preferably, described first adder or second adder are 13 totalizers.
Preferably, the described first quantized waveform storer or the second quantized waveform storer are the amplitude/phase change-over circuit.
This invention has realized that simultaneously the clock source circuit of array phase induction instrument aratus satisfies high-temperature work environment and two adjustable requirements of clock signal frequency, can generate two-way same frequency and dephased output signal.Be compared with the prior art, the clock source circuit in this invention adapts to bad working environment more; Save phase-shift circuit, reduced the scale of clock source circuit largely, improved the reliability of circuit; The clock source of this invention design has realized that the phase differential of output signal is adjustable continuously from the 0-180 degree, and stepping 0.2 is spent, and has greatly improved the dirigibility in array phase induction instrument aratus clock source.
Description of drawings
Fig. 1 is a DDS local oscillation circuit systematic functional structrue synoptic diagram in the prior art;
Fig. 2 is the structure principle chart of DDS;
Fig. 3 is a digit phase circle synoptic diagram;
Fig. 4 is a DDS system architecture schematic diagram among the present invention;
Fig. 5 is the basic structure synoptic diagram of phase accumulator among the present invention;
Fig. 6 is the block diagram that adds up of 40-bit in the preferred embodiment of the present invention;
Fig. 7 is the structural representation of DDS in the preferred embodiment of the present invention;
Fig. 8 is the structural representation of local oscillation signal amplitude adjusting module in the preferred embodiment of the present invention.
Embodiment
The present invention adopts expansion technical grade fpga chip and D/A chip, according to the clock source of the two DDS structures of principle of work design of DDS, adjusts the phase differential of two-way output clock by adjusting initial phase that two DDS circuit read sine lookup table.The present invention can satisfy the requirement of well logging circuit working in hot environment, and the phase differential of the two-way clock signal of output also can be adjusted arbitrarily, can satisfy the requirement of array phase induction instrument aratus to the clock source fully.
Adopt the fpga chip CYCLONE EP1C6T14417 of ALTERA company among the present invention, the FLASH chip (EPSC1) of external ALTERA company.Adopt DAC (AD5447YRU) to realize the function of DDS chip, the speed of adding up is 40MHz, and the figure place of phase accumulator is 40-bit, intercepts the address of high 11-bit as the RAM look-up table, and the Wave data storage depth is 2K*12bit, and the DAC precision is 12-bit.
In the design of DDS of the present invention, frequency control word decoding scheme and phase differential control word decoding scheme on the basis of DDS principle, have been added, can generate the two-way same frequency thus but have the frequency control word of phase differential, use this two-way frequency control word to look into sine table respectively, carry out digital-to-analog conversion and filtering more respectively, then obtain the two-way same frequency and have the sinusoidal signal of phase differential.
With reference to shown in Figure 4, DDS circuit of the present invention comprises phase accumulator, the first quantized waveform storer (adopting the sinusoidal waveform storer), first D/A converter, first low-pass filter, frequency control word decoding scheme, phase differential control word decoding scheme, second adder (adopting 13 totalizers), first adder (adopting 13 totalizers), the second quantized waveform storer (adopting the sinusoidal waveform storer), second D/A converter, second low-pass filter.
The frequency control word decoding scheme is got high 13 and is sent to phase accumulator as frequency control word according to the frequency control sign indicating number generated frequency data of CPU; Phase differential control word decoding scheme, the phase differential of root CPU generates the phase step input, sends to second adder (adopting 13 totalizers).
Phase accumulator adds up frequency data, and accumulation result is delivered to first adder (adopting 13 totalizers) and second adder (adopting 13 totalizers) respectively as sampling address.The frequency accumulation result of first adder receive frequency control word decoding scheme and phase accumulator carries out additive operation and generates sampling address, and sampling address is sent to the first quantized waveform storer.The phase step input of second adder receiving phase difference control word decoding scheme and the frequency accumulation result of phase accumulator carry out additive operation and generate sampling address, and sampling address is sent to the described second quantized waveform storer.
The first quantized waveform storer (adopting the sinusoidal waveform storer) is searched sine table according to sampling address, synthetic binary sinusoidal signal, export corresponding Wave data, this Wave data converts Wave data to needed first local oscillator output through first D/A converter and first low-pass filter.The second quantized waveform storer is searched sine table according to the sampling address that second adder generates, and synthetic binary sinusoidal signal is exported corresponding Wave data, and this Wave data sends to second D/A converter.Second D/A converter carries out digital-to-analog conversion with Wave data, and transformation result is sent to second low-pass filter.Second low-pass filter carries out low-pass filtering with the simulating signal that second D/A converter generates, and generates the output of second local oscillator.
Phase accumulator is the most basic ingredient of DDS, is used to realize adding up and storing its accumulation result of phase place.If the value of current phase accumulator is a ∑
n, through becoming ∑ after the clock period
N+1, then satisfy: ∑
N+1=∑
n+ M.
This shows ∑
nBe an arithmetic progression, be not difficult to draw: ∑
n=nM+ ∑
0
Wherein, ∑
0Prima facies place value for phase accumulator.
With reference to shown in Figure 5, the basic structure of phase accumulator is made of a N-bits totalizer and a N-bits register, and register adopts N d type flip flop to constitute usually.
With reference to shown in Figure 6, the ripple carry adder that uses a 40-bit in invention is as phase accumulator, and its output will feed back conduct input next time.Only carry out the one-accumulate operation in each clock period.
Because there are the needs of two passages and scale in system, produce two-way phase differential amplitude during design than adjustable local oscillation signal.
With reference to shown in Figure 7, wherein among one road DDS, inst11 and inst7 are the first phase control module, make the two-way local oscillation signal produce different phase differential by different phase control words; Inst2 is a frequency module, produces the mould value of corresponding each frequency by different frequency control words; Inst is an accumulator module, and the speed of adding up is 40MHz, and figure place is 40-bit, intercepts the address of high 11-bit as the ROM look-up table; Inst1 is the ROM module, is storing the sine table of normalized one-period, and the Wave data storage depth is 2K*12bit, and the DAC precision is 12-bit.
With reference to shown in Figure 8, local oscillator amplitude modulation module is adjusted the amplitude of local oscillation signal by inst5 division and inst28 multiplier module, by inst36 amplitude is adjusted into signal about the 0V symmetry through the signal of adjusting.
Claims (3)
1. high temperature monolithic phase programmable direct numerical frequency synthetic source, comprise the DDS circuit, described DDS circuit comprises phase accumulator, the first quantized waveform storer, first D/A converter, first low-pass filter, described phase accumulator adds up frequency data, accumulation result is delivered to the described first quantized waveform storer as sampling address, the described first quantized waveform storer is exported corresponding Wave data according to described sampling address, convert described Wave data to needed first local oscillator output through D/A converter and low-pass filter, it is characterized in that, also comprise:
The frequency control word decoding scheme, the frequency control sign indicating number generated frequency data of root CPU, and send to described phase accumulator;
Phase differential control word decoding scheme, the phase differential of root CPU generates the phase step input, and sends;
First adder receives the frequency accumulation result of described phase accumulator, carries out additive operation and generates sampling address, and described sampling address is sent to the first quantized waveform storer;
Second adder receives the phase step input of described phase differential control word decoding scheme and the frequency accumulation result of described phase accumulator, carries out additive operation and generates sampling address, and described sampling address is sent to the described second quantized waveform storer;
The second quantized waveform storer, the sampling address that generates according to described second adder generates corresponding Wave data, sends to second D/A converter;
Second D/A converter, the Wave data that the described second quantized waveform storer is generated carries out digital-to-analog conversion, and transformation result is sent to second low-pass filter;
Second low-pass filter carries out low-pass filtering with the simulating signal that described second D/A converter generates, and generates the output of second local oscillator.
2. high temperature monolithic phase programmable direct numerical frequency synthetic source according to claim 1 is characterized in that, described first adder or second adder are 13 totalizers.
3. high temperature monolithic phase programmable direct numerical frequency synthetic source according to claim 1 is characterized in that, the described first quantized waveform storer or the second quantized waveform storer are the amplitude/phase change-over circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA2007100647897A CN101276002A (en) | 2007-03-26 | 2007-03-26 | High temperature monolithic phase programmable direct numerical frequency synthetic source |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA2007100647897A CN101276002A (en) | 2007-03-26 | 2007-03-26 | High temperature monolithic phase programmable direct numerical frequency synthetic source |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN101276002A true CN101276002A (en) | 2008-10-01 |
Family
ID=39995622
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNA2007100647897A Pending CN101276002A (en) | 2007-03-26 | 2007-03-26 | High temperature monolithic phase programmable direct numerical frequency synthetic source |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101276002A (en) |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101799704A (en) * | 2010-03-23 | 2010-08-11 | 电子科技大学 | Multichannel DDS signal generator with precise phase control function |
| CN102315841A (en) * | 2011-09-01 | 2012-01-11 | 上海电力学院 | Electrical fast transient burst discharge switch driver circuit |
| CN102468845A (en) * | 2010-10-29 | 2012-05-23 | 鼎桥通信技术有限公司 | Method for eliminating frequency deviation of numerically controlled oscillator |
| CN106817082A (en) * | 2016-12-07 | 2017-06-09 | 四川九洲电器集团有限责任公司 | A kind of Digital Frequency Synthesize circuit |
| CN107956468A (en) * | 2017-12-06 | 2018-04-24 | 中石化石油工程技术服务有限公司 | Oil-base mud electric imaging logging instrument frequency Adaptable System |
| CN108169742A (en) * | 2018-01-04 | 2018-06-15 | 上海微抗电子技术有限公司 | Wideband adaptive frequency-tracking system and method |
| CN109542161A (en) * | 2019-01-30 | 2019-03-29 | 北京昊海雅正科技有限公司 | A kind of clock signal generating apparatus and method |
| CN110988760A (en) * | 2019-12-06 | 2020-04-10 | 天津大学 | Digital signal detection system of Mx type cesium optical pump magnetometer |
| CN113472294A (en) * | 2021-07-02 | 2021-10-01 | 上海航天电子通讯设备研究所 | Device and method for generating linear frequency modulation signals through multiphase DDS |
-
2007
- 2007-03-26 CN CNA2007100647897A patent/CN101276002A/en active Pending
Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101799704A (en) * | 2010-03-23 | 2010-08-11 | 电子科技大学 | Multichannel DDS signal generator with precise phase control function |
| CN101799704B (en) * | 2010-03-23 | 2012-04-25 | 电子科技大学 | Multichannel DDS signal generator with precise phase control function |
| CN102468845A (en) * | 2010-10-29 | 2012-05-23 | 鼎桥通信技术有限公司 | Method for eliminating frequency deviation of numerically controlled oscillator |
| CN102468845B (en) * | 2010-10-29 | 2013-10-16 | 鼎桥通信技术有限公司 | Method for eliminating frequency deviation of numerically controlled oscillator |
| CN102315841A (en) * | 2011-09-01 | 2012-01-11 | 上海电力学院 | Electrical fast transient burst discharge switch driver circuit |
| CN106817082A (en) * | 2016-12-07 | 2017-06-09 | 四川九洲电器集团有限责任公司 | A kind of Digital Frequency Synthesize circuit |
| CN107956468A (en) * | 2017-12-06 | 2018-04-24 | 中石化石油工程技术服务有限公司 | Oil-base mud electric imaging logging instrument frequency Adaptable System |
| CN108169742A (en) * | 2018-01-04 | 2018-06-15 | 上海微抗电子技术有限公司 | Wideband adaptive frequency-tracking system and method |
| CN109542161A (en) * | 2019-01-30 | 2019-03-29 | 北京昊海雅正科技有限公司 | A kind of clock signal generating apparatus and method |
| CN110988760A (en) * | 2019-12-06 | 2020-04-10 | 天津大学 | Digital signal detection system of Mx type cesium optical pump magnetometer |
| CN110988760B (en) * | 2019-12-06 | 2024-05-28 | 天津大学 | Digital signal detection system of Mx cesium light pump magnetometer |
| CN113472294A (en) * | 2021-07-02 | 2021-10-01 | 上海航天电子通讯设备研究所 | Device and method for generating linear frequency modulation signals through multiphase DDS |
| CN113472294B (en) * | 2021-07-02 | 2022-09-02 | 上海航天电子通讯设备研究所 | Device and method for generating linear frequency modulation signals through multiphase DDS |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101276002A (en) | High temperature monolithic phase programmable direct numerical frequency synthetic source | |
| CN107819456B (en) | High-precision delay generator based on FPGA carry chain | |
| CN103472712A (en) | High-precision and high-integrality time-digital converter based on FPGA (Field Programmable Gate Array), and implementation method | |
| US11101806B2 (en) | Frequency regulator and frequency regulating method thereof, and electronic device | |
| CN104300970A (en) | Voltage-control ring vibration type two-section type time digital conversion circuit based on DLL | |
| CN103488245B (en) | Phase amplitude conversion method in DDS and device | |
| CN102437852A (en) | Realization of 2.5 GSa/s data collection circuit by utilizing low speed ADC and method thereof | |
| CN109085879A (en) | A kind of high-precision DDS frequency synthesizer for the multi-functional calibration platform of electricity | |
| CN101359909B (en) | Flexible waveform generator with extended range capability | |
| CN202026300U (en) | Direct digital synthesizer and synchronous phase discrimination circuit device for direct digital synthesizer | |
| US6657573B2 (en) | Phase to sine amplitude conversion system and method | |
| CN1951014B (en) | Apparatus and method for a programmable clock generator | |
| Fang et al. | Design and simulation of DDS based on Quartus II | |
| Shan et al. | Design and implementation of a FPGA-based direct digital synthesizer | |
| CN206524751U (en) | A kind of high-frequency digital Switching Power Supply based on FPGA | |
| CN115001485A (en) | Direct digital frequency synthesizer based on Taylor polynomial approximation | |
| CN100392976C (en) | High order sigmatriangle noise shaping interpolator for direct digital frequency synthesis | |
| CN205121246U (en) | FPGA -based DDS signal generator | |
| CN104660218A (en) | Arbitrary waveform synthesizer | |
| US11012080B2 (en) | Frequency locked loop, electronic device, and frequency generation method | |
| CN102231629B (en) | DDS (direct digital synthesizer) system with phase offset modulation function realized by time sharing alternation | |
| Gujjula et al. | Design and analysis of dual-mode numerically controlled oscillators based controlled oscillator frequency modulation | |
| Wang et al. | Design and Simulation of an Optimized DDS | |
| Bashkirov et al. | Design of direct digital synthesizers signal generator | |
| Suganthi et al. | Design and implementation of numerically controlled oscillator |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C02 | Deemed withdrawal of patent application after publication (patent law 2001) | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Open date: 20081001 |