CN206524751U - A kind of high-frequency digital Switching Power Supply based on FPGA - Google Patents
A kind of high-frequency digital Switching Power Supply based on FPGA Download PDFInfo
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- CN206524751U CN206524751U CN201720150789.8U CN201720150789U CN206524751U CN 206524751 U CN206524751 U CN 206524751U CN 201720150789 U CN201720150789 U CN 201720150789U CN 206524751 U CN206524751 U CN 206524751U
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Abstract
The utility model is related to digital switch power supply, and in particular to a kind of high-frequency digital Switching Power Supply based on FPGA, including the reference voltage module being sequentially connected, FPGA control modules, drive module, is depressured modular converter, load；FPGA control modules include clock control circuit, A/D change-over circuits, digital PI control circuits and DPWM circuits, A/D change-over circuits are changed using hierarchical parallel, A/D change-over circuits include the one or eight bit pad being sequentially connected, the second parallel A/D converter and the 3rd parallel A/D conversions.Using hybrid PWM so that the resolution ratio of the simple in construction and pwm signal dutycycle of Switching Power Supply is improved.
Description
Technical field
The utility model is related to a kind of Switching Power Supply, more particularly to a kind of high-frequency digital Switching Power Supply based on FPGA.
Background technology
At present, Switching Power Supply mainly includes three classes：Analog switched power supply, based on monolithic processor controlled Switching Power Supply, is based on
The Switching Power Supply of DSP controls；In Power Electronic Circuit, single-chip microcomputer is mainly for the treatment of data acquisition and computing, regulation voltage
In terms of electric current, generation pwm signal, monitoring system state, failure self-diagnosis, as the main control chip of whole circuit, complete
A variety of comprehensive functions.Singlechip controller is mainly made up of single-chip microcomputer and periphery A/D, D/A converter, PWM chip etc..Its each portion
Point function is：A/D converter is sampled to voltage, the electric current of power system, and single-chip microcomputer receives and handles the signal after sampling,
Signal is adjusted inside it, the signal regulated is then passed through into the incoming PWM chip of D/A converter, the chip is responsible for
Produce PWM waveform to control power switch, reach control electric power coversion system.The quasi-controller realizes analog controller to number
The transformation of word controller, improves control accuracy, also controller is flexibly adjusted to a certain extent.It is numerically controlled
Superiority causes many laboratories in colleges and universities and scientific research institution in the world actively carrying out digital control switch truly
The research of power supply, but be due to have used multiple control chips, circuit is more complicated, and by multiple signal conversion,
Signal delay is added, the further raising of control accuracy and stability is limited.Single-chip microcomputer working frequency is relatively low simultaneously, this
The bottleneck developed as power system to high frequency, high-precision direction.
Dsp chip has higher arithmetic speed, can produce pwm signal, can quickly and accurately realize various controls,
Therefore the working frequency and precision of controller is greatly improved, also achieves and power system device is flexibly and effectively controlled,
Improve the stability of equipment.But the chip belongs to serial process mechanism, calculating process is complicated, and speed is unhappy, limits control
The further raising of device working frequency processed., may and the abnormal conditions such as deadlock, program fleet easily occurs in this kind for the treatment of mechanism
Power system can be caused to break down.Such as need to improve processing speed, then need to increase extremely many elements.
Pulsewidth modulation (PWM) type DC/DC switching power converters are widely used in camera, video camera, PDA, hand-held electric
In the portable type electronic products such as brain.With the increasingly extensive application of portable product, volume and stability to Switching Power Supply are carried
Higher requirement is gone out.PWM type DC/DC converters have analog- and digital- two kinds of frameworks.The small product sizes of analog architectures is small, power consumption
It is low, the main flow in market is accounted for, but it is very sensitive to noise.And Digital Design framework scalability is good, stability is high, making an uproar to external world
Sound relative insensitivity, can just make up the shortcoming of analog architectures.In terms of the growth requirement of DC/DC converters, Digital Control
Technology is necessary.In current digital architecture DC/DC design, the resolution ratio of generally existing pwm signal dutycycle is difficult to improve
Shortcoming.
Current A/D conversion chips have three types：Approach by inchmeal A/D conversions, double integration A/D conversion and parallel A/D conversions.
Approach by inchmeal A/D converter is relevant with its digit and clock pulse frequency the time required to completing once conversion, and digit is fewer, clock
Frequency is higher, shorter the time required to conversion.Approach by inchmeal A/D converter has the advantages that conversion speed is fast, precision is high.Double integrator
The characteristics of A/D is converted is that anti-Hz noise ability is strong, is relatively, to the stability requirement of device not due to integrating twice
Height, easily realizes high accuracy conversion.The principle of parallel A/D converter is introduced exemplified by three parallel-by-bit A/D conversions.Change-over circuit by
Voltage comparator, register and the part of coding circuit three composition.One reference voltage is divided into eight grades with eight resistance, its
In seven grades voltage respectively as seven comparators reference voltage, its numerical value is respectively/15,3/15 ..., 13/15,
Quantization unit X=2/15.Its input voltage is v, and its size determines the output state of each comparator.Then this seven are compared
The input that level is coupled with seven comparators is compared as benchmark.Parallel A/D conversions have following features：
Because conversion is parallel, conversion speed is only limited by comparator, trigger and coding circuit time delay, therefore is speed
Most fast conversion method；With the raising of resolution ratio, component number can be increased by geometric progression.The converter of one n needs to use
Multiple comparators, eight bit pads are accomplished by 255 comparators.Because digit is more, circuit is more complicated, therefore resolution ratio is made
Higher integrated parallel A/D converter is relatively difficult；, can during using this parallel A/D change-over circuits containing register
So that without additional samples holding circuits, because comparator and register have sampling concurrently, keeps function.
The content of the invention
The purpose of this utility model is：For above-mentioned because Switching Power Supply dsp chip is led using serial process mechanism
Element is caused the problem of simply be difficult to take into account with the resolution ratio of dutycycle, the utility model provides that a kind of hardware configuration is simple and PWM
A kind of high-frequency digital Switching Power Supply based on FPGA that the high resolution of signal dutyfactor is taken into account.
The technical solution adopted in the utility model is as follows：
A kind of high-frequency digital Switching Power Supply based on FPGA, including the reference voltage module being sequentially connected, FPGA control moulds
Block, drive module is depressured modular converter, load；FPGA control modules include clock control circuit, A/D change-over circuits, numeral
PI controls circuit and DPWM circuits；Reference voltage module exports constant voltage, and voltage signal is changed into mould by clock control circuit
Intend signal output and arrive A/D change-over circuits, digital PI controls circuit and DPWM circuits, A/D change-over circuits by analog signal with it is constant
Voltage compares conversion and exports closest data signal, and digital PI control circuits lead to according to reference voltage and reference voltage
Cross and compare to obtain error signal, be integrated to be controlled with differential according to error signal and adjust and export, DPWM circuits are according to connecing
The signal received produces waveform, and the width of pulse is exported by adjusting, makes output signal, drive circuit is defeated according to DPWM circuits
Go out requirement of the signal according to its control targe, the signal that can be switched on or off its power supply, decompression modular converter reduction input
Voltage, makes voltage and load matched.A/D change-over circuits are changed using hierarchical parallel, and A/D change-over circuits include the be sequentially connected
One or eight bit pads, the second parallel A/D converter and the 3rd parallel A/D conversions.
Wherein digital PI controller and DPWM are realized on FPGA.Main circuit output voltage feeds back, and is joined after ADC
Examine voltage.Reference voltage obtains output error signal with reference voltage by being compared, and DPWM, output duty cycle are sent to after PI
Signal controls main circuit switch break-make.When input signal changes, the dutycycle of DPWM output pulse signals changes therewith.When making
During with FPGA digitial controllers, the regulative mode of Voltage loop is digitized Pl regulations.It can be repaiied for different load objects
Change pi regulator parameter to meet performance indications requirement.
The input of three parallel-by-bit A/D conversions is with the output transformational relation table of comparisons with reference to shown in following table.
The information of integration (I) accumulation of illustrating over, it can eliminate the static difference of system, improve static system performance；Differential
(D) have controls in advance effect in signal intensity, illustrate the information in future, when process starts, force process accelerate into
OK, overshoot is reduced at the end of process, overcomes vibration, improve the stability of system, the transient process of acceleration system.Take classification simultaneously
The method of row conversion；Such as 8 bit pads can be low 4 through the first order, then carries out parallel A/D conversions by high 4, is simulated
Amount, input voltage is subtracted each other with analog voltage, and obtained difference carries out parallel A/D conversions again, obtains low 4 output.This method
Make a little to sacrifice in speed, but greatly reduced component number, and the resolution ratio of pwm signal dutycycle is higher；Solve
Improve the contradiction of resolution ratio and increase parts number.
Specifically, digital PI controls circuit uses the regulative mode of pressure ring.
Specifically, clock control circuit includes the built-in type phase-locked loop pll for being used to realize frequency multiplication and frequency dividing.
The system clock frequency of selection input is 50MHz, when the counting of DPWM modules is can be obtained by after being divided by PLL
A/D converter outside clock fclk, A/D triggering clock, control.Clock control block diagram clock control circuit includes AD clocks
Control, 3 modules of numeral PI clock controls and DPWM clock controls, they work under the collaboration of synchronised clock, and realization is not related to
The Digital Control FPGA piece built-in types phase-locked loop pll of power supply can be with input clock signal synchronization, it is possible to be used as ginseng
Examine signal and realize lock phase, so that the piece internal clock of one or more synchronizing and frequency doublings or frequency dividing is exported, for flogic system application.With it is straight
Fetch and compared from outside clock, this internal clock can reduce clock delay and clock deformation, reduce in piece and disturb；May be used also
To improve foundation and the retention time of clock.Phaselocked loop can be synchronous independent relative to a certain output clock to the reference clock of input
Be multiplied by or divided by a factor, and provide arbitrary phase shift and output signal dutycycle.
Specifically, DPWM circuits use modularization, including selector, comparator, counter, dead time generator.PWM is handle
Range value is converted into time value, earns the switch on and off of main circuit processed.The working frequency of main circuit is constant, the feedback letter of output voltage
Control circuit number is applied to, modulation (PWM) waveform exports the width of pulse by adjusting, makes output voltage stabilization.In PWM switches
In power supply, the generation of PWM waveform and its accurately modulate most important.The resolution ratio of digital PWM is directly connected to output voltage
Stable state accuracy.DDS (Digital Signal Processing) technology is set up on the basis of sampling thheorem, according to the difference of phase width conversion regime, point
For inquiry table method and calculating method.The corresponding range value of the out of phase that is stored with inquiry table method, is exported by phase accumulator
Phase value is addressed, and exports corresponding amplitude sequence, realizes that phase width is changed.Calculating method is by calculating the phase that phase accumulator is exported
Place value obtains corresponding range value, realizes that phase width is changed.Circuit design based on inquiry table method is very conventional, and circuit is typically by phase
Bit accumulator, phase shift accumulator, waveform table memory composition.Its operation principle is to complete the tired of phase bit address by phase accumulator
Plus, a cumulative side is the length that phase changes every time, the opposing party is on accumulator~value of feedback of secondary output result.Phase is tired out
Plus on the one hand the output of device feed back to input as a next time accumulative input, it is reasonable on the other hand to carry out as needed
Block, address after blocking feeding phase shift accumulator.The mainly as needed of phase shift accumulator changes the initial of waveform
Phase, a cumulative side is the data for changing initial phase, and the opposing party is the output after phase accumulator is blocked.Phase shift accumulator
Output as addressing of address ROM waveform table memories, inquire about and export corresponding waveforms amplitude data.DDS structured flowcharts are joined
According to shown in accompanying drawing 3.
The design of DPWM modules contains 5 main logical blocks and related peripheral circuit.The precision of 8 is realized,
DPWM reads 8 PI codes d [7:0] as control signal, corresponding dutycycle is then exported according to corresponding PI codes.
d[7:0] input range is 00000000~11111111, is translated into decimal number, when d is n, output
Dutycycle for (n+1)/256, DPWM in switching frequency fsWorked under=1MHZ, using 3 digit counters and 5 digit selector (nc
=3, nd=5), crystal oscillator frequency isfsyn_clk=8MHZ as system synchronised clock frequency.DPWM is read
Take 8 PI codes d [7:0] as control signal, corresponding duty cycle signals are exported according to PI codes.RS when one switch periods starts
Set, DPWM output high level.Clock signal is produced by pulse-series generatorIndividual pulse signal, the frequency of pulse signal
ForHave 2 within a PWM output cycle8=256 blocks.Eight duty cycle signals d [7 of input:0], it is divided into two
Branch, wherein d [4:0], i.e. nd=5 enter MUX.In order to eliminate competition and the burr between signal in design, multichannel is selected
Select device useIndividual ring retard.Input of the ring retard output signal as counter and with door, high 3 signal d [7:5] 3 are sent into
Bit comparator a input, ncDigit counter obtains cnt [2:0] it is compared with high-order portion, if equal be output as ' 1 ', no
Equal to be output as ' 0 ', the Reset ends for controlling R-S triggers, cnt is equal to be output as ' l ' compared with ' 0 ', unequal
It is output as ' 0 ' control Set ends.When counter exports cnt and ndHigh-order portion is equal, according to ncSelected by the decimal number of representative
Pulse signal there is high level, rest-set flip-flop resets, and PWM is output as low level, realizes pulsewidth modulation.
In summary, by adopting the above-described technical solution, the beneficial effects of the utility model are：
1. the information of integration (I) accumulation of illustrating over, it can eliminate the static difference of system, improve static system performance；It is micro-
Point (D) has controls in advance effect in signal intensity, illustrates the information in future, when process starts, force process accelerate into
OK, overshoot is reduced at the end of process, overcomes vibration, improve the stability of system, the transient process of acceleration system.Take classification simultaneously
The method of row conversion；Such as 8 bit pads can be low 4 through the first order, then carries out parallel A/D conversions by high 4, is simulated
Amount, input voltage is subtracted each other with analog voltage, and obtained difference carries out parallel A/D conversions again, obtains low 4 output.This method
Component number is not only greatly reduced, and the resolution ratio of pwm signal dutycycle is higher；Solve raising resolution ratio and increase member
The contradiction of number of packages.
2. clock control block diagram clock control circuit includes AD clock controls, numeral PI clock controls and DPWM clock controls
3 modules, they work under the collaboration of synchronised clock, realize the Digital Control FPGA pieces built-in type lock for being not related to power supply
Phase ring PLL can be with input clock signal synchronization, it is possible to as reference signal realize lock phase so that it is same to export one or more
The piece internal clock of frequency multiplication or frequency dividing is walked, for flogic system application.Compared with directly from outside clock, this internal clock
Clock delay and clock deformation can be reduced, reduces in piece and disturbs；Foundation and the retention time of clock can also be improved.Phaselocked loop
The reference clock of input synchronously can be independently multiplied by relative to a certain output clock or divided by a factor, and provide arbitrary phase
Move and output signal dutycycle.
3. using DDS, cost, reduction power consumption, raising PWM dutycycle high-resolution and fast conversion times are reduced excellent
Point.
Brief description of the drawings
Fig. 1 is the structure chart of the utility model high-frequency digital Switching Power Supply；
Fig. 2 is the structure chart of FPGA controls；
Fig. 3 is DDS structured flowcharts；
Marked in figure：1- reference voltage modules；2-FPGA control modules；3- drive modules；4- is depressured modular converter；5- is born
Carry；6-DPWM circuits；7- numerals PI controls circuit；8-A/D change-over circuits, 9- clock control circuits.
Embodiment
All features disclosed in this specification, can be with any in addition to mutually exclusive feature and/or step
Mode is combined.
The application is elaborated with reference to Fig. 1, Fig. 2, Fig. 3.
Embodiment 1
A kind of high-frequency digital Switching Power Supply based on FPGA, including the reference voltage module 1 being sequentially connected, FPGA control moulds
Block 2, drive module 3 is depressured modular converter 4, load 5；FPGA control modules include clock control circuit 9, A/D change-over circuits
8, digital PI control circuits 7 and DPWM circuits 6；Reference voltage module 1 exports constant voltage, and clock control circuit 9 believes voltage
Analog signal output number is changed into A/D change-over circuits 8, digital PI control circuits 7 and DPWM circuits 6, A/D change-over circuits 8 will
Analog signal compares conversion with constant voltage and exports closest data signal, and digital PI controls circuit 7 according to reference
Voltage, by being compared to obtain error signal, is integrated according to error signal with reference voltage and is controlled regulation and defeated with differential
Go out, DPWM circuits 6 produce waveform according to the signal received, the width of pulse is exported by adjusting, make output signal, drive mould
Block 3 is according to requirement of the output signal of DPWM circuits 6 according to its control targe, the signal that can be switched on or off its power supply, drop
The reduction input voltage of modular converter 4 is pressed, makes voltage and load matched；A/D change-over circuits 8 are changed using hierarchical parallel, A/D conversions
Circuit 8 includes the one or eight bit pad being sequentially connected, the second parallel A/D converter and the 3rd parallel A/D converter.
Embodiment 2
On the basis of embodiment 1, digital PI controls circuit 7 uses the regulative mode of pressure ring.
Embodiment 3
On the basis of embodiment 1 or 2, clock control circuit 9 includes the built-in type lock for being used to realize frequency multiplication and frequency dividing
Phase ring PLL.
Embodiment 4
On the basis of embodiment 3, DPWM circuits 6 use modularized design, including selector, comparator, counter, dead
Area's generator.
For embodiment 4, simulation waveform experiment is carried out：
Comparator module emulates ripple, and clk100 is comparator clock, and dataa, datab are the input of comparator two, and AeB is
Comparator is exported, and as dataa=datab, high level is output as, otherwise to be low；
The emulation of counter module, clk100 is the clock signal of counter, and q exports for counter.A clock week
In phase, q is continuously increased, and is realized and is counted；
The emulation of dead time generator module, clk100 is the clock signal of dead band counter, and d_set is the dutycycle of input
Signal, pwm_U, pwrn_IU, pwm_V, pwm_IV, pwm_W, pwm_IW is respectively the pwm control signal of input, dpwm_U,
Dpwm_IU, dpwm_V, dpwm_IV, dpwm_W, dpwm_IW are respectively the pwm control signal of dead time generator output.
Simulation waveforms of the PWM within 10 cycles, clk represents system clock, and AD represents that output voltage feeds back, and PWM is to open
Close control pulse.From output waveform it can be seen that with the change of feedback voltage, switching control pulse dutycycle changes therewith.When
When output voltage changes, system is responded rapidly to, and the response time is in a switch periods.
Claims (3)
1. a kind of high-frequency digital Switching Power Supply based on FPGA, it is characterised in that including the reference voltage module being sequentially connected
(1), FPGA control modules (2), drive module (3), decompression modular converter (4) is loaded (5)；FPGA control modules include clock
Control circuit (9), A/D change-over circuits (8), digital PI control circuits (7) and DPWM circuits (6)；Reference voltage module (1) is exported
Voltage signal is changed into analog signal output to A/D change-over circuits (8), digital PI controls by constant voltage, clock control circuit (9)
Analog signal and constant voltage are compared conversion and exported the most by circuit (7) processed and DPWM circuits (6), A/D change-over circuits (8)
Close data signal, digital PI control circuit (7) according to reference voltage with reference voltage by being compared to obtain error signal, according to
Error signal is integrated to be controlled with differential and adjusts and export, and DPWM circuits (6) produce waveform according to the signal received,
By adjusting the width of output pulse, make output signal, drive module (3) is controlled according to DPWM circuits (6) output signal according to it
The requirement of target processed, the signal that can be switched on or off its power supply, decompression modular converter (4) reduction input voltage makes voltage
With load matched；A/D change-over circuits (8) are changed using hierarchical parallel, and A/D change-over circuits (8) include the one or eight be sequentially connected
Bit pad, the second parallel A/D converter and the 3rd parallel A/D converter.
2. a kind of high-frequency digital Switching Power Supply based on FPGA as claimed in claim 1, it is characterised in that digital PI controls electricity
Road (7) uses the regulative mode of pressure ring.
3. a kind of high-frequency digital Switching Power Supply based on FPGA as claimed in claim 1, it is characterised in that clock control circuit
(9) the built-in type phase-locked loop pll for being used to realize frequency multiplication and frequency dividing is included.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201720150789.8U CN206524751U (en) | 2017-02-20 | 2017-02-20 | A kind of high-frequency digital Switching Power Supply based on FPGA |
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| CN201720150789.8U CN206524751U (en) | 2017-02-20 | 2017-02-20 | A kind of high-frequency digital Switching Power Supply based on FPGA |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112019056A (en) * | 2019-05-30 | 2020-12-01 | 雅达电子国际有限公司 | Switching power converter with adaptively triggered analog-to-digital converter |
| CN112688672A (en) * | 2019-10-17 | 2021-04-20 | 珠海零边界集成电路有限公司 | Apparatus and method for generating PWM wave |
-
2017
- 2017-02-20 CN CN201720150789.8U patent/CN206524751U/en active Active
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112019056A (en) * | 2019-05-30 | 2020-12-01 | 雅达电子国际有限公司 | Switching power converter with adaptively triggered analog-to-digital converter |
| CN112019056B (en) * | 2019-05-30 | 2024-04-05 | 雅达电子国际有限公司 | Switching power supply converter with adaptively triggered analog-to-digital converter |
| CN112688672A (en) * | 2019-10-17 | 2021-04-20 | 珠海零边界集成电路有限公司 | Apparatus and method for generating PWM wave |
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