CN207603614U - A kind of DDS signal sources clock generating circuit and signal source - Google Patents
A kind of DDS signal sources clock generating circuit and signal source Download PDFInfo
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- CN207603614U CN207603614U CN201820071967.2U CN201820071967U CN207603614U CN 207603614 U CN207603614 U CN 207603614U CN 201820071967 U CN201820071967 U CN 201820071967U CN 207603614 U CN207603614 U CN 207603614U
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Abstract
The utility model is related to a kind of DDS signal sources clock generating circuit, the clock generating circuit includes：Arm processor, first DDS module, second DDS module, PLL modules, first DAC module and comparator module, the arm processor calculates the first reference frequency according to waveform output frequency and reference frequency, and it is sent to first DDS module, the sine wave signal of first reference frequency is generated according to the reference frequency by first DDS module and is exported to the first DAC module, it is exported after carrying out digital-to-analogue conversion by first DAC module to comparator module, PLL modules progress frequency multiplication is fed back into sample rate clock signal after generating square-wave signal by the comparator module, the sample rate clock signal is sent to the second DDS module to provide integer clock signal by the PLL modules.Through the above scheme, the waveform of generation is overcome the starting point in each period is inconsistent the shortcomings that.
Description
Technical field
The utility model belongs to signal source domain, and in particular to a kind of DDS signal sources clock generating circuit and signal source.
Background technology
At present, for Direct Digital Synthesizer DDS (Direct Digital Synthesizer) class signal source,
Substantially it is fixed using clock and the fixed mode of sample rate generates required waveform, fixed clock and fixed sample rate advantage are
Realization technology is relatively simple, and cost is relatively low.But shortcoming is when generating periodic signal, due to DDS itself, to work as phase
Position is added to maximum value, there is a situation where phase spilling, leads to the signal in each period cannot be produced since same point simultaneously
It is raw, it is mainly manifested in the most apparent when sample rate and aliquant waveform frequency, what it is when generation is sample rate and waveform frequency
In the case of the aliquant impulse wave of rate, the waveform of the impulse wave of generation is observed on oscillograph, it is observed that impulse wave
Other than triggering edge, there is the shake in a sample rate period in other edges.
Utility model content
In view of the above-mentioned problems, the purpose of this utility model is to provide a kind of DDS signal sources clock generating circuit and signal source,
To overcome the waveform of generation the starting point in each period is inconsistent the shortcomings that.
To achieve the above object, the utility model takes following technical scheme：
A kind of DDS signal sources clock generating circuit in the utility model, including：Arm processor, the first DDS module, the
Two DDS modules, PLL modules, the first DAC module and comparator module, the arm processor according to waveform output frequency and
Reference frequency calculates the first reference frequency, and is sent to first DDS module, by first DDS module according to the ginseng
Frequency is examined to generate the sine wave signal of first reference frequency and export to the first DAC module, by first DAC module into
It is exported after row digital-to-analogue conversion to comparator module, the progress of PLL modules is fed back to after generating square-wave signal by the comparator module
The sample rate clock signal is sent to the second DDS module to provide by frequency multiplication into sample rate clock signal by the PLL modules
Integer clock signal.
Above-mentioned DDS signal sources clock generating circuit, it is preferred that the clock generating circuit includes：Second DAC module is used
In receiving data and digital-to-analogue conversion is carried out according to caused by integer clock signal.
Above-mentioned DDS signal sources clock generating circuit, it is preferred that the duty ratio of the square-wave signal is 50%.
Above-mentioned DDS signal sources clock generating circuit, it is preferred that the first reference that the frequency of the sine wave signal is 1/8
Frequency.
Above-mentioned DDS signal sources clock generating circuit, it is preferred that first DDS module further comprises：It is phase-accumulated
Device, phase-accumulated value register and read-only memory, the phase accumulator add up to frequency control word, the phase
The phase value is fed back to the phase accumulator with next phase that adds up by cumulative value register for caching phase value
Place value, the Wave data being read-only memory for after storage sine wave digitlization.
Above-mentioned DDS signal sources clock generating circuit, it is preferred that the PLL modules are digital phase-locked loop.
A kind of signal source in the utility model, including：DDS signal source clock generating circuits as described above.
A kind of DDS signal sources clock generating circuit and signal source in the utility model meet the waveform of generation in each week
The starting point of phase can be consistent and generate stable data output, final to solve to lack caused by conventional DDS class signal sources
It falls into.
Description of the drawings
Fig. 1 is that the utility model embodiment provides a kind of schematic diagram of DDS signal sources clock generating circuit；
Fig. 2 is the structure diagram of the first DDS module that the utility model embodiment is provided.
Specific embodiment
The utility model is described in detail with reference to the accompanying drawings and examples.
The utility model embodiment provides a kind of DDS signal sources clock generating circuit, as shown in Figure 1, the clock occurs
Circuit includes：ARM (Advanced RISC Machines) processor 1, the first DDS (DirectDigital
Synthesizer) module 21, the second DDS module 22, PLL (Phase Locked Loop) module 23, the first DAC (Digital
Analogue Converter) module 3 and comparator module 4, the arm processor 1 is according to waveform output frequency and ginseng
It examines frequency and calculates the first reference frequency, and be sent to first DDS module 21, by first DDS module 21 according to described
Reference frequency generates the sine wave signal of first reference frequency and exports to the first DAC module 3, by the first DAC moulds
Block 3 is exported after carrying out digital-to-analogue conversion to comparator module 4, and PLL moulds are fed back to after generating square-wave signal by the comparator module 4
Block 23 carries out frequency multiplication into sample rate clock signal, and the sample rate clock signal is sent to the 2nd DDS by the PLL modules 23
Module 22 is to provide integer clock signal.Preferably, the first reference frequency Fref1 is reference frequency Fref and waveform output frequency
The integer part of the Fout ratios product with waveform output frequency Fout again.Specifically as shown in formula 1 and formula 2：
Take the value of D that the first reference frequency Fref1 is calculated：
Fref1=FOut*D formula 2,
Wherein, D is the integer part of reference frequency Fref and waveform output frequency Fout ratios, and d is reference frequency Fref
With the fractional part of waveform output frequency Fout ratios.By the first reference frequency Fref and waveform output frequency being calculated
The condition divided exactly can always be met between Fout.
The sine of the first reference frequency Fref1 is then generated according to the clock of reference frequency Fref by the first DDS module
Wave signal, and the sine wave signal is exported to the first DAC module, the first DAC module carries out digital-to-analogue conversion to sine wave signal,
And it exports to comparator module.Preferably, the comparator module is an analog comparator, it can be according to the first DAC moulds
It is an off-gauge dynamic value that the output of block, which generates TTL square-wave signals a Fref2, Fref2, by Fref2 signals as when
In clock signal feed back input to PLL modules, frequency multiplication is carried out by PLL modules, generates a stable sample rate clock signal
Fsample, the second DDS module 22 to be given to provide integer clock signal.
In preferred embodiment, the first DDS module in above-described embodiment, the second DDS module and PLL modules can be led to
FPGA technology is crossed to realize, to improve the integrated level of clock generating circuit.
DDS signal sources clock generating circuit described in the utility model embodiment by make the first reference frequency Fref1 with
Meet the condition divided exactly between waveform output frequency Fout, waveform caused by guarantee is in the state divided exactly with sample rate, leads to
Analog comparator and the setting of PLL are crossed, to provide stable integer clock signal to the second DDS module so that the 2nd DDS moulds
Block is calculated according to newly generated sample rate clock signal, and the frequency control word of calculating is all the relationship of integral multiple, so as to raw
Into starting point of the waveform in each period can be consistent and generate stable data output, it is final to solve conventional DDS classes
Defect caused by signal source.
The DDS signal source clock generating circuits that the utility model embodiment is provided, preferably, as shown in Figure 1, when described
Clock occurs circuit and further includes：Second DAC module 5 is gone forward side by side line number mould for receiving the data according to caused by integer clock signal
By the integer clock signal for the stabilization that the second DDS module provides, the 2nd DAC moulds are output to so as to generate stable data for conversion
Digital-to-analogue conversion is carried out in block 5.
Preferably, in a kind of DDS signal sources clock generating circuit in the utility model embodiment, the square-wave signal
The duty ratio of TTL is 50%.
The DDS signal source clock generating circuits that the utility model embodiment is provided, preferably, the sine wave signal
Frequency is 1/8 the first reference frequency.Specifically, after the first reference frequency Fref1 is calculated, the first DDS module is used
And the sine wave signal of the first reference frequency Fref1 that reference frequency Fref generation frequencies are 1/8.
The DDS signal source clock generating circuits that the utility model embodiment is provided, preferably, as shown in Fig. 2, described
One DDS module 21 further comprises：Phase accumulator 211, phase-accumulated value register (DFF) 212 and read-only memory
(ROM) 213, the phase accumulator 211 adds up to frequency control word, and the phase-accumulated value register 212 is used to delay
It deposits phase value, while the phase value is fed back into the phase accumulator 211 with next phase value that adds up, it is described read-only to deposit
Reservoir 213 is used to store the Wave data after sine wave digitlization.Specifically, frequency control word Freq_ is calculated by arm processor
Word is simultaneously supplied to phase accumulator 211 to add up；Phase-accumulated value register 212 caches phase value, while by caching
Phase value feeds back to phase accumulator 211 and carries out cumulative phase value next time, and read-only memory 213 stores sine wave number
Wave data after change can read read-only memory 213 by 48 phase datas that phase-accumulated value register 212 exports
The value of Wave data namely sine wave after middle sine wave digitlization.
Preferably, data use the width of 48 in the utility model embodiment, frequency can be as accurate as 0.8uHz,
Meet the application scenarios of the utility model embodiment.Specifically, frequency control word Freq_word bit wides are wider, frequency accuracy is got over
Height is determined according to actual conditions.Namely in other embodiments, the FREQUENCY CONTROL of different bit wides can also be used according to demand
Word.Stored in read-only memory 213 be sine wave digitlization after Wave data, it is defeated by phase-accumulated value register 212
48 phase datas gone out read the value of sine wave in read-only memory 213.Preferably, since ROM sizes are by resource constraint, institute
To need 48 data being truncated before reading, the data of high 10 are taken in the first DDS module 21, in the 2nd DDS
High 16 data are taken in module 22.Specifically, in order to generate the clock Fref2 signals of high frequency in the first DDS module 21, and
Its peripheral circuit has the presence of the first DAC module and comparator module, therefore takes the signal quality of the data of high 10 to generation
Substantially it does not influence, and since the signal frequency range of generation is wider in the second DDS module 22, but the 2nd DAC vertically has
Valid value is 16, and low frequency signal, so taking high 16 data, can ensure signal quality in order to balance, does not also waste hardware money
Source.Sine wave signal is output to the first DAC module 3 from FPGA, then the square-wave signal of Transistor-Transistor Logic level is generated by comparator module 4
Fref2, since the characteristic of 48 high-precision phase positions and analog comparator so that Fref2 shakes are smaller inside the first DDS module.This
Sample is more conducive to the clock source of the output signal Fref2 of comparator module 4 as generation waveform inside FPGA, while by comparator mould
The square-wave signal Fref2 that block 4 exports is connected on the special clock I/O pins of FPGA, in internal one digital phase-locked loop of exampleization,
Since number is big with input dynamic range according to phaselocked loop, the same analog phase-locked look of performance in the case of integral multiple frequency multiplication and frequency dividing
It is close, so carrying out 8 frequencys multiplication to the input square wave of comparator module 4 with 23 module of digital phase-locked loop here, generate the 2nd DDS moulds
Clock Fsample needed for block, the second DDS module 22 are calculated according to newly generated Fsample clock frequencies, the frequency of calculating
Rate word is all the relationship of integral multiple, so as to which the starting point in waveform each period of generation can be consistent, solves conventional DDS bands
The defects of coming.
The utility model embodiment also provides a kind of signal source, specifically, the signal source includes as above any one implementation
DDS signal source clock generating circuits described in example.
A kind of signal source described in the utility model embodiment is outer compared to relatively in the scheme for increasing an analog comparator
The scheme for enclosing increase phaselocked loop is cheap, and the peripheral phaselocked loop response time is slower than FPGA internal digital phaselocked loops, and input
Dynamic range is smaller, is better than the scheme of external phaselocked loop using the scheme of the utility model embodiment in performance, better than
Traditional fixed sample rate and fixed clock mode.Generally speaking in the case that cost almost without it is increased effectively improving performance and
Waveform quality.
In conclusion by a kind of DDS signal sources clock generating circuit and signal source described in the utility model embodiment,
By making to meet the condition divided exactly, waveform caused by guarantee between the first reference frequency Fref1 and waveform output frequency Fout
The state divided exactly is in sample rate, by the setting of analog comparator and PLL, to provide stabilization to the second DDS module
Integer clock signal so that the second DDS module is calculated according to newly generated sample rate clock signal, the FREQUENCY CONTROL of calculating
Word is all the relationship of integral multiple, and starting point of the waveform in each period so as to generate can be consistent and generate stable data
Output, it is final to solve defect caused by conventional DDS class signal sources.
The utility model is not limited to above-mentioned preferred forms, anyone can obtain under the enlightenment of the utility model
Other various forms of products, however, make any variation in its shape or structure, it is every that there is same as the present application or phase
Approximate technical solution, all falls within the scope of protection of the utility model.
Claims (7)
1. a kind of DDS signal sources clock generating circuit, which is characterized in that the clock generating circuit includes：Arm processor, the
One DDS module, the second DDS module, PLL modules, the first DAC module and comparator module, the arm processor is according to waveform
Output frequency and reference frequency calculate the first reference frequency, and be sent to first DDS module, by the first DDS moulds
Root tuber generates the sine wave signal of first reference frequency according to the reference frequency and exports to the first DAC module, by described
First DAC module is exported after carrying out digital-to-analogue conversion to comparator module, is fed back after generating square-wave signal by the comparator module
Frequency multiplication is carried out into sample rate clock signal to PLL modules, and the sample rate clock signal is sent to second by the PLL modules
DDS module is to provide integer clock signal.
2. a kind of DDS signal sources clock generating circuit according to claim 1, which is characterized in that electricity occurs for the clock
Road includes：Second DAC module, for receiving the data according to caused by integer clock signal and carrying out digital-to-analogue conversion.
3. a kind of DDS signal sources clock generating circuit according to claim 1, which is characterized in that the square-wave signal
Duty ratio is 50%.
A kind of 4. DDS signal sources clock generating circuit according to claim 1, which is characterized in that the sine wave signal
Frequency be 1/8 the first reference frequency.
A kind of 5. DDS signal sources clock generating circuit according to claim 1, which is characterized in that first DDS module
Further comprise：Phase accumulator, phase-accumulated value register and read-only memory, the phase accumulator is to FREQUENCY CONTROL
Word adds up, and the phase-accumulated value register is used to cache phase value, while the phase value is fed back to the phase
Accumulator is with next phase value that adds up, the Wave data being read-only memory for after storage sine wave digitlization.
6. a kind of DDS signal sources clock generating circuit according to claim 1, which is characterized in that the PLL modules are number
Word phaselocked loop.
7. a kind of signal source, which is characterized in that the signal source includes：DDS letters as described in any one in claim 1-6
Number source clock generating circuit.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201820071967.2U CN207603614U (en) | 2018-01-17 | 2018-01-17 | A kind of DDS signal sources clock generating circuit and signal source |
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| CN201820071967.2U CN207603614U (en) | 2018-01-17 | 2018-01-17 | A kind of DDS signal sources clock generating circuit and signal source |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108039888A (en) * | 2018-01-17 | 2018-05-15 | 优利德科技(中国)有限公司 | A kind of DDS signal sources clock generating circuit, signal source and its method |
| CN111693837A (en) * | 2020-06-29 | 2020-09-22 | 核动力运行研究所 | Low-voltage signal source |
-
2018
- 2018-01-17 CN CN201820071967.2U patent/CN207603614U/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108039888A (en) * | 2018-01-17 | 2018-05-15 | 优利德科技(中国)有限公司 | A kind of DDS signal sources clock generating circuit, signal source and its method |
| CN111693837A (en) * | 2020-06-29 | 2020-09-22 | 核动力运行研究所 | Low-voltage signal source |
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