CN102447470A - Direct digital frequency synthesis (DDS)-based signal source - Google Patents
Direct digital frequency synthesis (DDS)-based signal source Download PDFInfo
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- CN102447470A CN102447470A CN2010105079990A CN201010507999A CN102447470A CN 102447470 A CN102447470 A CN 102447470A CN 2010105079990 A CN2010105079990 A CN 2010105079990A CN 201010507999 A CN201010507999 A CN 201010507999A CN 102447470 A CN102447470 A CN 102447470A
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Abstract
A direct digital frequency synthesis (DDS)-based signal source relates to a signal source which is based on the DDS technology. The DDS-based signal source comprises a phase-locked loop clock circuit, a key shake-removal interface circuit, a control circuit, a DDS modular circuit and other parts, wherein the DDS generates digital signal through a field programmable gate array (FPGA), the digital signal is converted into a continuous adjustable sine wave with the frequency being between 30-100Hz and the phase being between 0-360 degrees, the control circuit uses a Nios II system, so the core part of the whole system is completed on an FPGA chip. The DDS-based signal source is used for signal simulation, simulates the signal required by electronic equipment with the same characteristics as the practical environment, tests the performance of the equipment, and is used as a standard source to calibrate or compare with the common signal.
Description
Technical field:
A kind of signal source based on Direct Digital frequency synthesis DDS relates to a kind of signal source based on direct digital frequency synthesis technology DDS.
Background technology:
Frequency synthesis technique has experienced nearly 80 years development since proposing the thirties in last century, can be divided into three phases: direct-type frequency synthesis technique, pll frequency synthesizer and direct digital frequency synthesis technology.Directly frequency synthesis technique use frequency multiplication, frequency division, mixting circuit to one or several reference frequency add, subtract, the computing of multiplication and division produces the frequency signal of needs, select through narrow-band filtering again.This is to arrive the synthetic filtering technology that occurs most, and principle is simple and be easy to realize.Its synthetic method can be divided into two kinds of relevant synthetic method and irrelevant synthetic methods; The difference of these two kinds of methods is that the quantity of employed reference frequency source is different: irrelevant synthetic method is used a plurality of crystal reference frequency sources; Synthetic various frequencies are provided by these frequency sources, and it is too high that shortcoming is to make a plurality of crystal reference frequency source grain granite and costs with same frequency stability and precision; Relevant synthetic method is only used a crystal reference frequency source, and required various frequencies obtain after by reference frequency frequency division, mixing, frequency multiplication, and the frequency stability of frequency synthesis is identical with reference frequency with precision.Directly frequency and the wide frequency range of growing up to be a useful person, frequency inverted rapid speed (microsecond level), frequency interval is less, and working stability is reliable, but parasitic output is big, needs a large amount of analog elements, and complex structure, volume is big, cost is high.
To be the beginning of the forties grow up according to the linear servo loop of control theory pll frequency synthesizer; The synchronous scanning circuit that is used for television set the earliest; To reduce noise to synchronous influence; Make the net synchronization capability of TV obtain major improvement, its low noise tracing property also receives people's great attention, has been widely used in the every field of radiotechnics at present.Pll frequency synthesizer is also referred to as the indirect type frequency synthesis technique; Its circuit is simple than the direct-type frequency synthesis; It mainly is that the oscillator that contains noise is placed in the phase-locked loop; Its phase place is locked on the signal of hope, thereby the noise of oscillator itself is suppressed, its output spectrum is purified greatly.
Direct digital frequency synthesis technology (DDS) then is to propose the seventies in last century, but is limited to hardware technology level at that time and fails to be applied, and along with the development of large scale integrated circuit technology, the superiority of DDS technology progressively manifests.The major advantage of DDS be easy to program control, phase place continuously, output stability and resolution is high.
Summary of the invention:
The present invention is exactly to the problems referred to above, and a kind of signal source that frequency inverted speed is fast, output frequency stable, phase place is continuous, resolution is high that has is provided.
For realizing above purpose, the present invention adopts following technical scheme, the system of the present invention includes comprise PLL clock circuit, button go to tremble parts such as interface circuit, control system, DDS modular circuit; Realize that through FPGA DDS produces digital signal; Convert frequency at 30-100Hz through D/A converter; Phase place is at the continuously adjustable sine wave of 0-360 degree, and control system is used the NiosII system, and the core of whole system is all accomplished on a fpga chip.
Beneficial effect of the present invention:
Owing to use fpga chip, therefore simplified circuit and also provided cost savings, shorten the design cycle.
Description of drawings:
Below in conjunction with accompanying drawing the present invention is further specified.
Fig. 1 DDS overall system block diagram
Embodiment:
The system of the present invention includes comprise PLL clock circuit, button go to tremble parts such as interface circuit, control system, DDS modular circuit.The present invention realizes that through FPGA DDS produces digital signal; Convert frequency at 30-100Hz through D/A converter; Phase place is at the continuously adjustable sine wave of 0-360 degree; Control system is used the NiosII system of altera corp, and the core of whole system is all accomplished on a fpga chip.
Frequency control word passes through after the adding up of phase accumulator and the address information of the sine wave that phase control words adds up produces one-period; Therefore sign bit and asynchronous through the data that produce behind the ROM look-up table needs a delay register to guarantee the correctness of dateout.
Requirement according to system has added keystroke interface and liquid crystal interface in NiosII, the output of frequency and phase control words, and the interface that has added FLASH interface and SDRAM is respectively as the place of procedure stores and operation.
The present invention needs three clocks altogether; The 50MHz clock that is respectively the 50MHz system clock that provides to fpga chip, provides to SDRAM and for producing the needed 4KHz clock signal of DDS part of 30-100Hz waveform signal; The output linkage counter of clock, counter outputs to frequency divider.
The present invention need key in the frequency control word and the phase control words (liquid crystal display) of 3 of frequencies; Remove the reset key of system; Also used 4 keys to come the input of control system; 4 buttons are respectively " setting/acknowledgement key ", " frequency/phase options button ", " position options button ", " button adds 1 key ", and 4 keys all will connect pull down resistor and be high level.
Claims (5)
1. signal source based on Direct Digital frequency synthesis DDS, comprise system comprise PLL clock circuit, button go to tremble parts such as interface circuit, control system, DDS modular circuit; Realize that through FPGA DDS produces digital signal; Convert frequency at 30-100Hz through D/A converter; Phase place is at the continuously adjustable sine wave of 0-360 degree, and control system is used the NiosII system, and the core of whole system is all accomplished on a fpga chip.
2. a kind of signal source according to claim 1 based on Direct Digital frequency synthesis DDS; It is characterized in that frequency control word is through the add up address information of the sine wave that produces one-period of add up back and the phase control words of phase accumulator, sign bit and asynchronous through the data that produce behind the ROM look-up table.
3. a kind of signal source according to claim 1 based on Direct Digital frequency synthesis DDS; It is characterized in that in NiosII, having added keystroke interface and liquid crystal interface according to the requirement of system; The output of frequency and phase control words, and the interface that has added FLASH interface and SDRAM is respectively as the place of procedure stores and operation.
4. a kind of signal source according to claim 1 based on Direct Digital frequency synthesis DDS; It is characterized in that three clocks of common needs; The 50MHz clock that is respectively the 50MHz system clock that provides to fpga chip, provides to SDRAM and for producing the needed 4KHz clock signal of DDS part of 30-100Hz waveform signal; The output linkage counter of clock, counter outputs to frequency divider.
5. a kind of signal source according to claim 1 based on Direct Digital frequency synthesis DDS; The frequency control word and the phase control words (liquid crystal display) that it is characterized in that 3 of needs key entry frequencies; Remove the reset key of system; Also used 4 keys to come the input of control system, 4 buttons are respectively " setting/acknowledgement key ", " frequency/phase options button ", " position options button ", " button adds 1 key ", and 4 keys all will connect pull down resistor and be high level.
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| CN2010105079990A CN102447470A (en) | 2010-10-15 | 2010-10-15 | Direct digital frequency synthesis (DDS)-based signal source |
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| CN2010105079990A CN102447470A (en) | 2010-10-15 | 2010-10-15 | Direct digital frequency synthesis (DDS)-based signal source |
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103281076A (en) * | 2013-05-28 | 2013-09-04 | 中国人民解放军63921部队 | Clock source and signal processing method thereof |
| CN104063008A (en) * | 2014-07-05 | 2014-09-24 | 中国船舶重工集团公司第七二四研究所 | Method for generating digital combined pulse signals with continuous phase positions |
| CN104811139A (en) * | 2015-04-20 | 2015-07-29 | 浙江科技学院 | Vector network analysis method based on DDS spurious frequency application |
| CN105846819A (en) * | 2016-03-23 | 2016-08-10 | 上海航天测控通信研究所 | Direct digital frequency synthetic method and synthesizer based on FPGA |
| CN108627809A (en) * | 2017-03-15 | 2018-10-09 | 武汉玉航科技有限公司 | One kind being based on FPGA real-time radar signal generating means and modulator approach |
| CN109542161A (en) * | 2019-01-30 | 2019-03-29 | 北京昊海雅正科技有限公司 | A kind of clock signal generating apparatus and method |
| CN114594825A (en) * | 2022-03-28 | 2022-06-07 | 深圳市爱普泰科电子有限公司 | System and method for generating jittered clock signal |
-
2010
- 2010-10-15 CN CN2010105079990A patent/CN102447470A/en active Pending
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103281076A (en) * | 2013-05-28 | 2013-09-04 | 中国人民解放军63921部队 | Clock source and signal processing method thereof |
| CN104063008A (en) * | 2014-07-05 | 2014-09-24 | 中国船舶重工集团公司第七二四研究所 | Method for generating digital combined pulse signals with continuous phase positions |
| CN104811139A (en) * | 2015-04-20 | 2015-07-29 | 浙江科技学院 | Vector network analysis method based on DDS spurious frequency application |
| CN104811139B (en) * | 2015-04-20 | 2018-06-05 | 浙江科技学院 | Vector network analysis method based on the application of DDS spurious frequencies |
| CN105846819A (en) * | 2016-03-23 | 2016-08-10 | 上海航天测控通信研究所 | Direct digital frequency synthetic method and synthesizer based on FPGA |
| CN108627809A (en) * | 2017-03-15 | 2018-10-09 | 武汉玉航科技有限公司 | One kind being based on FPGA real-time radar signal generating means and modulator approach |
| CN109542161A (en) * | 2019-01-30 | 2019-03-29 | 北京昊海雅正科技有限公司 | A kind of clock signal generating apparatus and method |
| CN114594825A (en) * | 2022-03-28 | 2022-06-07 | 深圳市爱普泰科电子有限公司 | System and method for generating jittered clock signal |
| CN114594825B (en) * | 2022-03-28 | 2024-04-12 | 深圳市爱普泰科电子有限公司 | System and method for generating jittered clock signal |
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Application publication date: 20120509 |