CN203883807U - Digital atomic frequency standard system circuit - Google Patents

Abstract

The utility model belongs to the technical field of atomic frequency standard system circuits, and discloses a digital atomic frequency standard system circuit. The digital atomic frequency standard system circuit comprises a direct digital frequency synthesizer DDS, a clock signal source, an output filter, a register control module and a sequence signal generation module, wherein the direct digital frequency synthesizer DDS is connected with the clock signal source, the output filter, the register control module and the sequence signal generation module. The digital atomic frequency standard system circuit provided by the utility model can avoid a temperature effect brought about by a variable capacitance diode modulation circuit adopted by a traditional frequency standard system, thereby avoiding influences imposed on the stability of the system output frequency by the temperature effect.

Description

A kind of digital atomic frequency standard circuit system

Technical field

The utility model relates to atomic frequency standard circuit system technical field, particularly a kind of digital atomic frequency standard circuit system.

Background technology

In an actual passive Rb atomic frequency, the distribution of C field in chamber can not be that atomic spectral line just there will be asymmetric phenomenon so completely uniformly.If the amplitude of square wave frequency modulation remains unchanged, this frequency shift amount is also constant, thereby can not bring temperature coefficient to rubidium frequency standard, yet owing to having adopted capister modulation circuit in traditional rubidium frequency standard, capister is temperature sensing element, thereby during variation of ambient temperature, inevitably will cause the amplitude of square wave frequency modulation to change. obviously, when the amplitude of square wave frequency modulation increases, additional frequency shift amount increases; When the amplitude of square wave frequency modulation reduces, additional frequency shift amount reduces. and therefore, in rubidium frequency standard, the inhomogeneous spectral line that causes in C field is asymmetric, will to rubidium frequency standard, bring temperature coefficient by modulation circuit.Although the output of frequency marking crystal oscillator accurately equals the crest frequency of the theoretical spectral line calculating through frequency multiplication, frequency after comprehensive, but because actual spectral line is asymmetric. after frequency discrimination, in the output voltage of quantum part, just there is the fundametal compoment of modulation frequency, this fundametal compoment is a pseudo error voltage, by phase detecting circuit, become pseudo-correction electricity doctor, crystal oscillator frequency is drawn partially, causes the stability of output frequency to reduce.

Utility model content

Technical problem to be solved in the utility model is to provide the impact that a kind of stability that can greatly reduce the output frequency that component temperature effect causes reduces.

For solving the problems of the technologies described above, the utility model provides a kind of digital atomic frequency standard circuit system, comprising: Direct Digital Synthesizer DDS, signal source of clock, output filter, register control module and clock signal generation module; Described Direct Digital Synthesizer DDS is connected with described signal source of clock, described output filter, described register control module and described clock signal generation module respectively.

Further, described Direct Digital Synthesizer DDS adopts AD9832 chip.

Further, described signal source of clock adopts clock-signal generator; Described clock-signal generator is connected with the digital dock input MCLK pin of described AD9832 chip.

Further, described signal source of clock is atomic clock or GPS time signal; Described atomic clock or GPS time signal access the digital dock input MCLK pin of described AD9832 chip.

Further, described output filter is band pass filter or low pass filter; Be connected with the IOUT output port of described DDS chip.

Further, described clock signal generation module comprises: microprocessor; Described microprocessor is connected with serial clock signal pin SCLK, serial data input SDATA and the data synchronizing signal input FSYNC of described DDS chip; To described DDS chip write timing control word.

Further, described output filter is crystal filter.

Further, the incoming frequency of the digital dock input MCLK of described DDS chip is greater than 4 times of output frequency of the IOUT output of described DDS chip.

Further, described input clock signal carries out accessing described DDS chip after 3 frequencys multiplication.

Further, two of described DDS chip Selecting phasing control end PSEL0 and PSEL1 ground connection.

The digital atomic frequency standard circuit system that the utility model provides is reformed traditional atomic frequency standard circuit system structure, adopt by digital electric line structure and replace the modulation circuit based on analogue devices such as variable capacitance diodes, greatly improve the puppet correction voltage causing due to component temperature effect, thereby guaranteed the stability of output frequency.

Accompanying drawing explanation

The digital atomic frequency standard circuit system structural representation that Fig. 1 provides for the utility model embodiment;

Fig. 2 is the structural representation of AD9832.

Embodiment

Referring to Fig. 1, Direct Digital Synthesizer DDS(Direct Digital Synthesizer), signal source of clock, output filter, register control module and clock signal generation module a kind of digital atomic frequency standard circuit system that the utility model embodiment provides, comprising:; Described Direct Digital Synthesizer DDS is connected with described signal source of clock, described output filter, described register control module and described clock signal generation module respectively.

The digital atomic frequency standard circuit system that the present embodiment provides is for inactive type rubidium atom frequency scale system, in order better to avoid the impact of device temperature effect answering system output frequency stability, preferably, Direct Digital Synthesizer DDS adopts has the AD9832 chip that high frequency is debated rate, thereby ensures more stable output frequency stability.

Referring to Fig. 2, signal source of clock adopts clock-signal generator, is connected with the digital dock input MCLK pin of AD9832 chip.Meanwhile, signal source of clock can be to be also atomic clock or GPS time signal; Wherein, MCLK pin connects external clock reference, makes the stability of IOUT pin output frequency signal of AD9832 consistent with external clock reference.Because AD9832 inside does not have PLL frequency multiplication link, conventionally the frequency in MCLK end input clock source should be held 4 times of output signal frequency higher than IOUT; For example, when output signal frequency is 5.3125MHz, the signal frequency of MCLK clock end should be greater than 20MHz so, to expect to obtain better phase noise, after filtered external circuit, can obtain purer signal spectra.

Output filter is band pass filter or low pass filter; Be connected with the IOUT output port of DDS chip.In order to improve mutually, to make an uproar, suppress the technical indicator such as spuious, in to the processing of DDS output signal, adopted crystal filter. utilize the squareness factor that crystal filter is good, improve the technical indicator of signal aspect spuious and phase noise.In frequency translation.The noise of introducing in order to reduce as much as possible active device, adopts the logical passive filtering device of low pass and band in a large number.

FSELECT is keying FM signal input, our modulated square wave 79Hz signal input part namely, there are two FREQUENCY CONTROL registers AD9832 inside, mode by programming is kept at the frequency value F pre-setting 0, F1 in register, when FSELECT end has square-wave signal input, i.e. electrical level rising edge or trailing edge conversion; The value that the IOUT end of AD9832 will be read respectively F1 or F0 thereupon from FREQUENCY CONTROL register is as output, and the phase place of meeting inhibit signal is unchanged.

In design in advance, we obtain purer signal spectra, after the output of IOUT end, connect a band pass filter, but due to the passband of band pass filter, to do relatively narrow, cause in final signal output, the inconsistent phenomenon of amplitude that has occurred two frequency signals, in background technology, mention, because the inhomogeneous atomic spectral line causing in C field is inhomogeneous, the frequency discrimination effect of the inconsistent modulation signal spectrum of amplitude throughput subsystem, will certainly produce pseudo-correction voltage, even if we are certain value at the amplitude difference by other measure and ensure two-way modulation signal, but in order to ensure for the purpose of, in synthesizer link, its amplitude is reached to consistent by other filtered version.

PSEL0, PSEL1 are the phase adjusted end of two paths of signals frequency F1, F0, and in application, we intend keeping F1, the F0 phase place when switching continuous, thus in design directly by PSEL0, PSEL1 ground connection.AD9832 is to complete by pin FSYNC, SCLK, SDATA with extraneous main communication (as F1, F0 value) sequential.

When FSYNC is high level, SCLK, SDATA pin is high-impedance state.When FSYNC is low level, AD9832 will be in communication state, when now pin SCLK has the pulse of a trailing edge, the DATA that makes to hang on data/address bus SDATA is write to AD9832 data buffer zone, until that a final DATA writes is fashionable, AD9832 is using the output as IOUT end according to the condition selecting F1 on pin FSELECT or F0.

, without PLL times of frequency module, therefore the external clock frequency of pin MCLK input is the clock frequency of system, take and export 5.3125MHz frequency signal as example in AD9832 inside, the input end of clock signal frequency of MCLK is 20MHz.There are 2 32 bit frequency control registers (F0, F1) AD9832 inside, therefore when serial communication, DATA position should be 32.Hence one can see that, and when the outside input clock frequency 20MHz of this MCLK, the minimum frequency resolution of AD9832 is:

$\frac{20\mathrm{MHz}}{2^{32}}=4.66\mathrm{mHz}(\≈5\mathrm{mHz})$

During IOUT output 20MHz, the value of 32 corresponding bit frequency control registers is 1 entirely; During output 5.3125MHz, corresponding numerical value is (5.3125MHz/20MHz) * 232, resulting decimal value is converted into the value of the corresponding 32 bit frequency control registers of binary system.According to serial sequential, by microprocessor, corresponding 32 place values are write in AD9832 buffering area.

In frequency transform techniques index. the requirement of making an uproar is mutually: during 100Hz≤130dBc, during 1kHz≤140dBc; This index is a more crucial technical indicator in circuit is realized, and he depends on the index of making an uproar mutually of DDS output signal, the performance index of crystal filter, low noise linear amplification and low noise circuit index.When clock 300MHz, adopt the performance that the mode of inner frequency multiplication makes an uproar mutually when departing from 1kHz, during output 5MHz, make an uproar mutually as a 140dBc/Hz; While directly adopting the clock of 300MHz, the performance of making an uproar is mutually when departing from 1kHz. and be a 142dBc/Hz.Therefore, in order to improve the performance of making an uproar mutually of DDS output signal, adopt outside frequency multiplication method, input clock 10MHz is externally carried out being added on DDS after frequency tripling.In the selection of DDS, select the inner AD9852 with 12bitD/A transducer, by selecting the more DDS of D/A conversion figure place.Can further improve the quality of DDS output signal.

The digital atomic frequency standard circuit system that the utility model embodiment proposes is reformed traditional atomic frequency standard circuit system structure, adopt by digital electric line structure and replace the modulation circuit based on analogue devices such as variable capacitance diodes, greatly improve the puppet correction voltage causing due to component temperature effect, thereby guaranteed the stability of output frequency.In frequency-conversion circuit, spuious technical requirement is :≤mono-80dBc.Harmonic wave technical indicator is: second harmonic≤mono-150dBc, other harmonic wave≤mono-60dBc.DDS when clock work frequency is 300MHz, in the situation that DDS output signal frequency is 10MHz, spuious SFDR≤mono-58dBc of DAC output; When clock operating frequency is 300MHz, its SFDR performance will decline, due between output frequency and clock on the cycle without integral multiple relation, in the adjacent periods of output signal, signal sampling value is different, causes the signal SFDR producing after D/A conversion to increase.By experimental test, the SFDR of DDS (AD9852) output is in 50dBc left and right.In order to reach spuious technical requirement, first the signal of DDS output carries out filtering processing through low pass filter or band pass filter, attenuation outside a channel is greater than to 40dB, for relatively having several dB left and right decay near the spuious especially beat component of signal frequency.For to spuious further inhibition, in processing, signal adopted crystal filter, the passband of crystal filter is the bandwidth of 3.8～5.2kHz. there is good squareness factor, attenuation outside a channel is greater than 80dB, signal is spuious can reach consistent with circuit substrate noise with technical indicators such as harmonic waves, is less than 90dB.Meet the desired technical indicator of system.

It should be noted last that, above embodiment is only unrestricted in order to the technical solution of the utility model to be described, although the utility model is had been described in detail with reference to example, those of ordinary skill in the art is to be understood that, can modify or be equal to replacement the technical solution of the utility model, and not departing from the spirit and scope of technical solutions of the utility model, it all should be encompassed in the middle of claim scope of the present utility model.

Claims (10)

1. a digital atomic frequency standard circuit system, is characterized in that, comprising: Direct Digital Synthesizer DDS, signal source of clock, output filter, register control module and clock signal generation module; Described Direct Digital Synthesizer DDS is connected with described signal source of clock, described output filter, described register control module and described clock signal generation module respectively.

2. digital atomic frequency standard circuit system as claimed in claim 1, is characterized in that: described Direct Digital Synthesizer DDS adopts AD9832 chip.

3. digital atomic frequency standard circuit system as claimed in claim 2, is characterized in that: described signal source of clock adopts clock-signal generator; Described clock-signal generator is connected with the digital dock input MCLK pin of described AD9832 chip.

4. digital atomic frequency standard circuit system as claimed in claim 2, is characterized in that: described signal source of clock is atomic clock or GPS time signal; Described atomic clock or GPS time signal access the digital dock input MCLK pin of described AD9832 chip.

5. digital atomic frequency standard circuit system as claimed in claim 1, is characterized in that: described output filter is band pass filter or low pass filter; Be connected with the IOUT output port of described DDS chip.

6. digital atomic frequency standard circuit system as claimed in claim 1, is characterized in that: described clock signal generation module comprises: microprocessor; Described microprocessor is connected with serial clock signal pin SCLK, serial data input SDATA and the data synchronizing signal input FSYNC of described DDS chip; To described DDS chip write timing control word.

7. digital atomic frequency standard circuit system as claimed in claim 1, is characterized in that: described output filter is crystal filter.

8. digital atomic frequency standard circuit system as claimed in claim 1, is characterized in that: the incoming frequency of the digital dock input MCLK of described DDS chip is greater than 4 times of output frequency of the IOUT output of described DDS chip.

9. digital atomic frequency standard circuit system as claimed in claim 1, is characterized in that: described input clock signal carries out accessing described DDS chip after 3 frequencys multiplication.

10. the digital atomic frequency standard circuit system as described in claim 1～9 any one, is characterized in that: two Selecting phasing control end PSEL0 of described DDS chip and PSEL1 ground connection.