CN208026853U - The magnetic resonance signal real time processing system of bandwidth varying based on FPGA - Google Patents
The magnetic resonance signal real time processing system of bandwidth varying based on FPGA Download PDFInfo
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- CN208026853U CN208026853U CN201820448016.2U CN201820448016U CN208026853U CN 208026853 U CN208026853 U CN 208026853U CN 201820448016 U CN201820448016 U CN 201820448016U CN 208026853 U CN208026853 U CN 208026853U
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Abstract
The utility model discloses a kind of magnetic resonance signal real time processing system of the bandwidth varying based on FPGA, which, which establishes, utilizes programmable logic device（FPGA）The magnetic resonance signal processing system of realization realizes high-speed AD real-time data acquisition, with the storage and transmission of data after the digital down conversion system and down coversion of phase and the variable bandwidth and extraction rate of orthogonal channel.The utility model can be configured different parameters by PC machine, modified to Digital Down Convert structure, to adapt to various specific design requirements using the advantages such as the repeatable programming of FPGA, flexibility be strong.
Description
Technical field
The utility model is related to mr techniques, signal processing and data communication, embedded technology.Especially one kind can
The method that the magnetic resonance signal of variable bandwidth is handled in real time.
Background technology
The real time signal processing of magnetic resonance signal includes mainly signal acquisition, digital down-conversion technology and signal transmission.
And digital down-conversion technology is a vital ring in acquisition of magnetic resonance signals processing.Currently, the technology is mainly by dedicated
Digital Down Convert chip is realized, DSP is realized.Special purpose DDC chip is stable and to use difficulty low, but it is expensive, and logical
Road number is restricted, and different customizations can not be carried out according to different demands, and the completion of integral product can be limited to chip
Supply.Although the DSP implementation method energy various digital signals of high speed processing, since the AD sampling rates of prime are higher and higher,
Requirement of the Digital Signal Processing of high speed for DSP is excessively high, and the system that monolithic dsp chip realizes entire DDC can not only be used only.
Utility model content
The purpose of this utility model be in view of the deficiencies of the prior art and provide a kind of bandwidth varying based on FPGA
Magnetic resonance signal real time processing system, this method, which establishes, utilizes programmable logic device（FPGA）At the magnetic resonance signal of realization
Reason system provides the real-time processing scheme of magnetic resonance signal, fills up the bandwidth varying lacked in the market and extracts the number of rate
Down coversion scheme realizes the storage and transmission of data after the high-speed sampling and down coversion of magnetic resonance signal.
Realizing the specific technical solution of the utility model aim is：
A kind of magnetic resonance signal real time processing system of the bandwidth varying based on FPGA, including power module, high speed serialization
A/D chip, high speed serial parallel exchange module, Digital Down Converter Module, programmable logic device（FPGA）, DDR3 memory modules,
PCI9054 chips, pci bridge chip, storage medium, PC machine.Wherein, power module is gone here and there and is turned with high speed serialization A/D chip, high speed
Change the mold block, Digital Down Converter Module, programmable logic device（FPGA）, DDR3 memory modules, PCI9054 chips, pci bridge chip
It is connected；High speed serialization A/D chip is connected with high speed serial parallel exchange module；High speed serial parallel exchange module and Digital Down Convert mould
Block, programmable logic device（FPGA）It is connected；Digital Down Converter Module and high speed serial parallel exchange module, programmable logic device
（FPGA）It is connected；Programmable logic device（FPGA）Mould is stored with high speed serial parallel exchange module, Digital Down Converter Module, DDR3
Block, PCI9054 chips are connected；DDR3 memory modules and programmable logic device（FPGA）It is connected；PCI9054 chips with
Programmable logic device（FPGA）, pci bridge chip, storage medium be connected；Pci bridge chip is connected with PC machine；Storage medium
It is connected with PCI9054 chips；PC machine is connected with pci bridge chip；
Wherein Digital Down Converter Module includes：The frequency mixing module of data-signal, CIC decimation filters module, CIC compensation filters
Wave device module, half-band filter group module, FIR shaping filter modules.Wherein, the frequency mixing module of data-signal is extracted with CIC
Filter module is connected；CIC decimation filters module is connected with CIC compensating filter modules；CIC compensating filter modules
It is connected with half-band filter group module；Half-band filter group module is connected with FIR shaping filter modules.
Above system is realized that the magnetic resonance signal of bandwidth varying is handled in real time and is included the following steps：
Step 1：Carry out acquisition of magnetic resonance signals
1.1：Utilize programmable logic device（FPGA）It controls high speed serial parallel exchange module and exports sampling clock, and send and refer to
The register for enabling change high speed serialization A/D chip is at cycle and generates the pattern for specifying training sequence；
1.2：Utilize programmable logic device（FPGA）The data read under 1.1 patterns are judged, are identified whether
It is consistent with specified training sequence, the integrated mode of serial data is adjusted, until gathered data is consistent with specified training sequence；
1.3：After 1.2 reach, programmable logic device is utilized（FPGA）Instruction is sent, high speed serial parallel exchange module is controlled
The register for changing high speed serialization A/D chip, is at normal sample pattern；
1.4：Utilize programmable logic device（FPGA）It controls high speed serial parallel exchange module and carries out data acquisition and data
Serioparallel exchange；
Step 2：Magnetic resonance signal carries out Digital Down Convert, specifically includes：
2.1：Using PC machine to programmable logic device（FPGA）It is controlled, is obtained according to the bandwidth demand of magnetic resonance signal
Centre frequency, the bandwidth of extraction rate and output data to the carrier wave of resonance signal；
2.2：Utilize programmable logic device（FPGA）To the frequency mixing module of data-signal, CIC decimation filters module,
CIC compensating filters module, half-band filter group module, FIR shaping filter modules carry out parameter configuration, reach bandwidth varying
Purpose；
2.3：Digital Down Convert operation is carried out to MR data using Digital Down Converter Module；
Step 3：Step 2 the data obtained is read out and is stored, is specifically included：
3.1：Utilize programmable logic device（FPGA）Programming software opens the FIFO IP kernels in the IP kernel provided and establishes first
Enter and first goes out storage queue；
3.2：Since pushup storage queue can be written and read operation respectively using different independent clocks, utilize
Data after down coversion are stored in large capacity by the reading rate of pushup storage queue change data output speed and DDR3
DDR3 in, the data volume until storing enough processing；
3.3：Using PCI communication modes, PC machine reading is set to be stored in the data after the down coversion in DDR3, by the data obtained
It is stored in the file in PC machine, in case follow-up data is handled.
Compared with prior art, the utility model has the beneficial effects that：
(1) the utility model uses programmable logic device（FPGA）It realizes, can be carried out according to different project demands
It custom-configures, and can grow with each passing hour, update.It can be changed according to user demand and extract rate and output signal band
Width, flexibility are strong；
(2) down conversion filter structure provided by the utility model can provide high power and extract rate, adapt to various bandwidth
The processing of magnetic resonance signal；
(3) the utility model stores the data after down coversion using the DDR3 of two panels 1G memories, and large capacity is deposited
Storage can make the digital independent of PC machine possess time tolerance.And realize the storage and update of real time data, it is carried out convenient for PC machine follow-up
Processing；
(4) the utility model can be applied not only to magnetic resonance signal processing, can be used for the lower change of institute's number in need
The communication system of frequency processing, universality are extensive.
Description of the drawings
Fig. 1 is the system structure diagram of the utility model；
Fig. 2 is the Digital Down Convert structure chart of the utility model；
Fig. 3 is utility model works flow diagram.
Specific implementation mode
Refering to fig. 1, the acquisition of magnetic resonance signals system of the utility model include power module 1, high speed serialization A/D chip 2,
High speed serial parallel exchange module 3, Digital Down Converter Module 4, programmable logic device（FPGA）5, DDR3 memory modules 6, PCI9054
Chip 7, pci bridge chip 8, storage medium 9, PC machine 10.The utility model is carried out the magnetic resonance of high speed by high speed serialization A/D chip 2
Signal acquisition, wherein be connected with high speed serialization A/D chip 2 signal when：Analog_Data1_in_P and Analog_Data1_
In_N is the Differential Input pin of analog magnetic resonance signal, is input from the outside to high speed serial AD chip 2；High speed serialization AD cores
Piece 2 converts analog signals into digital signal and reaches high speed serial parallel exchange module 3, and wherein high speed serialization A/D chip 2 to high speed is gone here and there
And the signal of 3 direction of conversion module connection is：To be frame synchronization clock output pin, DCO_P and DCO_N are FCO_P and FCO_N
Bit synchronization clock out pin, Data1_out_P and Data1_out_N are serial digital output pin, high speed serial parallel exchange mould
The signal that block 3 is connected to 2 direction of high speed serial AD chip is：Sample_Clk_P and Sample_Clk_N is high speed serial parallel exchange
Module 3 reaches the difference sampling clock pin of high speed serialization A/D chip 2, and SPI control signals are to post high speed serialization A/D chip
The SPI controlling switch that storage 2 is configured.Utilize programmable logic device（FPGA）5 pairs of high speed serial parallel exchange modules 3 are instructed
Practice the judgement of sequence, realize serioparallel exchange, connection signal is that SPI controls signal at this.If wherein high speed serial parallel exchange module 3 is examined
Measure training sequence matching, then 3 correct collecting magnetic resonance signal of high speed serial parallel exchange module, and the high speed serial parallel exchange that will be obtained
The parallel data Adata_in [15 that module 3 to Digital Down Converter Module 4 is connected:0] and Pal_clk parallel clocks reach number
Down conversion module 4, and the conversion of Digital Down Convert is carried out wherein, magnetic resonance letter is obtained according to the bandwidth demand of magnetic resonance signal
Number the centre frequency of carrier wave, parameters, these parameters such as bandwidth for extracting rate and output data pass through by PC machine 10
PCI9054 chips 7, pci bridge chip 8 are to programmable logic device（FPGA）5 are controlled, by programmable logic device（FPGA）
5 pairs of Digital Down Converter Modules 4 carry out parameter configuration, complete the operation of bandwidth varying.Transformed data-signal is passed through later
Digital Down Converter Module 4 is to programmable logic device（FPGA）The data line FIR_out_Q [31 of 5 connections:0] and FIR_out_I
[31:0] it is transmitted to programmable logic device（FPGA）In 5, wherein FIR_out_Q [31:0] and FIR_out_I [31:0] it is IQ
Data pin after two-way Digital Down Convert；Programmable logic device（FPGA）5 deposit Digital Down Convert data obtained above
It stores up into DDR3 memory modules 6, wherein programmable logic device（FPGA）The signal connected between 5 and DDR3 memory modules 6 is：
DDR3_Ctrl is DDR3 memory module controlling switch, DDR3_Addr [29:0] and DDR3_Data [31:0] it is respectively that DDR3 is deposited
Store up the address pin and data pin of module.PCI9054 chips 8 carry out power on configuration by storage medium 9, are stored in DDR3 storages
Data in module 6 are after PC machine 10 sends out and reads signal, by programmable logic device（FPGA）5 by PCI9054 chips 7,
Pci bridge chip 8 is sent to PC machine 10 and carries out data storage, in case follow-up data processing, wherein programmable logic device（FPGA）5
The signal being connected with PCI9054 chips 7 is：PCI_Ctrl,PCI_Addr[31:0] and PCI_Data [31:0], respectively may be used
Programmed logic device（5）With PCI9054 chips（7）Between transmission controlling switch, address pin and data pin.
Referring to Fig.2, the Digital Down Convert structure of the utility model is as follows：Magnetic resonance signal passes through high speed serialization AD and high speed
After serioparallel exchange module carries out the serioparallel exchange of data, the parallel data Adata_in [15 that will obtain:0] and Pal_clk is parallel
Clock sends it to the frequency mixer in the frequency mixing module 21 of data-signal, generated respectively with NCO modules 27 all the way with becoming under phase
Frequency channel data Cosine [15:0] and all the way quadrature frequency conversion channel data sine [15:0] it is multiplied, is carried out in frequency mixer 26
Frequency mixing processing.Later by the data Mix_out_I [31 after mixing:0] and Mix_out_Q [31:0] with CIC decimation filter moulds
Block 22 is connected, and carries out obtaining data CIC_out_I [31 after CIC is filtered:0] and CIC_out_Q [31:0], by its with
CIC compensating filters module 23 is connected, and compensates and is filtered, and obtains data CICcom_out_I [31:0] and
CICcom_out_Q[31:0], it is connected with half-band filter group module 24, data is obtained after carrying out filtering extraction processing
HB_out_I[31:0] and HB_out_Q [31:0], and by it with FIR shaping filters module 25 it is connected, carries out shaping filter
Final down coversion data FIR_out_I [31 is obtained after processing:0] and FIR_out_Q [31:0], programmable logic device is sent it to
Part（FPGA）5 carry out subsequent storage transmission process.
Refering to Fig. 3, after providing power supply for acquisition of magnetic resonance signals system, the access input at high speed serialization A/D chip 2
High-frequency signal.Centre frequency, the data of local oscillation signal in parameter configuration, including the frequency mixing module of data-signal are carried out using PC machine
Extraction yield and data bandwidth are carried out carrying out parameter configuration to Digital Down Converter Module according to given parameters, be obtained to sampling
Signal carry out signal processing, store into DDR3, when PC machine provide read signal after by down coversion after the data obtained be uploaded to PC
Machine is preserved to specified file, in case follow-up data is handled.
Claims (2)
1. a kind of magnetic resonance signal real time processing system of the bandwidth varying based on FPGA, it is characterised in that the system includes：Electricity
Source module（1）, high speed serialization A/D chip（2）, high speed serial parallel exchange module（3）, Digital Down Converter Module（4）, programmable logic
Device FPGA（5）, DDR3 memory modules（6）, PCI9054 chips（7）, pci bridge chip（8）, storage medium（9）And PC machine
（10）, the power module（1）With high speed serialization A/D chip（2）, high speed serial parallel exchange module（3）, Digital Down Converter Module
（4）, programmable logic device FPGA（5）, DDR3 memory modules（6）, PCI9054 chips（7）, pci bridge chip（8）It is connected；
High speed serialization A/D chip（2）With high speed serial parallel exchange module（3）It is connected；High speed serial parallel exchange module（3）With Digital Down Convert
Module（4）, programmable logic device FPGA（5）It is connected；Digital Down Converter Module（4）With high speed serial parallel exchange module（3）, can
Programmed logic device FPGA（5）It is connected；Programmable logic device FPGA（5）With high speed serial parallel exchange module（3）, number is lower becomes
Frequency module（4）, DDR3 memory modules（6）, PCI9054 chips（7）It is connected；DDR3 memory modules（6）With programmable logic device
Part FPGA（5）It is connected；PCI9054 chips（7）With programmable logic device FPGA（5）, pci bridge chip（8）, storage medium
（9）It is connected；Pci bridge chip（8）With PC machine（10）It is connected；Storage medium（9）With PCI9054 chips（7）It is connected；PC machine
（10）With pci bridge chip（8）It is connected.
2. system according to claim 1, the Digital Down Converter Module（4）Including：The frequency mixing module of data-signal
（21）, CIC decimation filter modules（22）, CIC compensating filter modules（23）, half-band filter group module（24）And FIR is whole
Mode filter module（25）, the frequency mixing module of the data-signal（21）With CIC decimation filter modules（22）It is connected；CIC
Decimation filter module（22）With CIC compensating filter modules（23）It is connected；CIC compensating filter modules（23）It is filtered with half band
Wave device group module（24）It is connected；Half-band filter group module（24）With FIR shaping filter modules（25）It is connected.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109633759A (en) * | 2018-12-12 | 2019-04-16 | 吉林大学 | Ground magnetic resonance signal rapidly extracting device and method based on phase lock amplifying technology |
| CN112600574A (en) * | 2020-12-10 | 2021-04-02 | 天津光电通信技术有限公司 | Digital DDC design method of multi-channel direction finding receiver based on FPGA |
-
2018
- 2018-04-02 CN CN201820448016.2U patent/CN208026853U/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109633759A (en) * | 2018-12-12 | 2019-04-16 | 吉林大学 | Ground magnetic resonance signal rapidly extracting device and method based on phase lock amplifying technology |
| CN112600574A (en) * | 2020-12-10 | 2021-04-02 | 天津光电通信技术有限公司 | Digital DDC design method of multi-channel direction finding receiver based on FPGA |
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