CN104242931B - The all-digital phase-locked loop and implementation method of a kind of quick lock in - Google Patents
The all-digital phase-locked loop and implementation method of a kind of quick lock in Download PDFInfo
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Abstract
The all-digital phase-locked loop and implementation method of a kind of quick lock in that the present invention is provided, by controlling phase-locked loop external timing signal, can complete the capture of phaselocked loop in a cycle, realize quick lock in.Phaselocked loop of the present invention includes phase discriminator, phase error counter, frequency divider, impulse controller and except N-counter, and the error signal that incoming frequency and comparison frequency phase demodulation are produced is given phase error counter by phase discriminator；The error signal count value that phase error counter will be produced is to impulse controller；Frequency divider is to external clock 2NfcTwo divided-frequency is carried out, generation frequency is identical, the two-way frequency signal f of 180 ° of phase difference1And f2Also impulse controller is inputed to；Impulse controller according to count value, to frequency signal f1、f2、2NfcSelective output is carried out, except the frequency-doubled signal f that N-counter is exported to impulse controllermulCarry out N times to divide, produce and incoming frequency fiThe comparison frequency that frequency is identical, phase is consistent.
Description
Technical field
The present invention relates to digital circuit technique field, the all-digital phase-locked loop of more particularly to a kind of quick lock in and realization
Method.
Background technology
Phaselocked loop is a kind of circuit that output signal can be made synchronous with input signal in frequency and phase, i.e., system enters
It is zero to be differed after lock-out state, between output signal and input signal, or remains constant.Traditional phaselocked loop all parts
All it is to be realized by analog circuit, generally comprises phase discriminator (PD), loop filter (LF), three bases of voltage controlled oscillator (VCO)
This part.With the development of digital technology, all-digital phase-locked loop ADPLL (AllDigital Phase-Locked Loop) is progressively
Grow up, be widely used in fields such as communication, radar, measurement and Automated condtrols.So-called all-digital phase-locked loop,
It is exactly that loop component is all digitized, phase-locked loop is constituted using digital phase discriminator, digital loop filters, digital controlled oscillator,
And the signal in system is full data signal.All-digital phase-locked loop compared with the phaselocked loop that traditional analog circuit is realized, no
The low advantage of digital circuit reliability high, small volume, price is only absorbed, and due to avoiding the temperature of analog phase-locked look presence
Degree drift and easily by voltage variations affect the shortcomings of, so as to possess reliability high, working stability, it is easy to adjust the advantages of.
Traditional all-digital phase-locked loop is general to become mould forward-backward counter, plus-minus impulse controller by phase discriminator, K, except N is counted
The basic elements of character such as device are constituted, and theory diagram is as shown in Figure 1.Incoming frequency fiWith comparison frequency foPhase is produced to miss by phase discriminator
Difference pulse, mould forward-backward counter is become by K, produces two kinds of pulses；Impulse controller is added and subtracted according to two kinds of pulse signals, to outside
Reference clock frequency is improved or reduced, then by except N-counter, producing feedback signal fo.But with the increase of N values, phaselocked loop
The lock-up cycle on road is elongated；Also, become the operation principle of mould forward-backward counter based on K, it is desirable to which input signal is dutycycle 1:1
Data signal.
The content of the invention
The present invention is for defect or deficiency present in prior art, there is provided a kind of all-digital phase-locked loop of quick lock in and
Implementation method, by controlling phase-locked loop external timing signal, can complete the capture of phaselocked loop in a cycle, realize fast
Speed locking.The all-digital phase-locked loop can be used for the generation to the PGC demodulation and frequency-doubled signal of frequency signal, especially to lock
In phase velocity requirement circuit design high, the present invention has fairly obvious advantage.
Technical scheme is as follows：
A kind of all-digital phase-locked loop of quick lock in, it is characterised in that the phaselocked loop reaches locking in a cycle
State；Including phase discriminator, phase error counter, frequency divider, impulse controller and except N-counter, the phase discriminator will be input into
Frequency fi and comparison frequency fcomPhase demodulation is carried out, the error signal v that will be producedoInput to the phase error counter；The phase
Position error counter is to error signal voCounted, produced count value NxInput to the impulse controller；The frequency divider pair
External clock 2NfcTwo divided-frequency is carried out, generation frequency is identical, the two-way frequency signal f of 180 ° of phase difference1And f2Also institute is inputed to
State impulse controller；The impulse controller is according to count value Nx, to frequency signal f1、f2、2NfcSelective output is carried out, will
The frequency-doubled signal f of generationmulInput to described except N-counter；The frequency-doubled signal exported to impulse controller except N-counter
fmulCarry out N times to divide, produce and incoming frequency fiThe comparison frequency f that frequency is identical, phase is consistentcom；The external clock 2Nfc
In N be divider ratio except N-counter, fcIt is loop center frequency, and fc≈fi,
A kind of implementation method of the all-digital phase-locked loop of quick lock in, it is characterised in that by lasting insertion external clock
Pulse changes the phase size of comparison frequency, comprises the following steps：
1) by phase discriminator to incoming frequency fiWith comparison frequency fcomPhase demodulation is carried out, error signal v is producedo；
2) by phase error counter to error signal voCounted, produced count value Nx；
3) by frequency divider to external clock 2NfcTwo divided-frequency is carried out, generation frequency is identical, the two-way of 180 ° of phase difference
Frequency signal f1And f2；
4) impulse controller is according to count value NxSize and parity, to frequency signal f1、f2、2NfcSelectivity output,
The frequency-doubled signal f of control impulse controller outputmulOutput state, change frequency-doubled signal fmulFrequency size so that point
Comparison frequency f after frequencycomPhase and incoming frequency fiUnanimously；
5) except the frequency-doubled signal f that N-counter is exported to impulse controllermulCarry out N times to divide, produce and incoming frequency fi
The comparison frequency f that frequency is identical, phase is consistentcom；
The external clock 2NfcIn N be the divider ratio in loop except N-counter, fcIt is loop center frequency, and fc≈
fi,
The step 1) in, using edging trigger phase discriminator to incoming frequency fiWith comparison frequency fcomPhase demodulation is carried out, is produced
Error signal vo；The error signal voIt is rising edge trigger signal, in incoming frequency fiWith comparison frequency fcomRising edge enter
Row triggering, i.e., as incoming frequency fiSet, comparison frequency f during for rising edgecomResetted during for rising edge, otherwise its output state
Keep constant.
The step 2) in, by external clock 2NfcTo error signal voSet level counted, obtain count value
Nx, in the range from 0≤Nx<2N, i.e., when loop is in the lock state, count value Nx=0, when loop losing lock, count value NxFor
One positive integer no more than phase error capacitance 2N.
The step 4) in, when loop is lock-out state, Nx=0, the output waveform of impulse controller, i.e. frequency-doubled signal
fmulIt is f1Or and f1Anti-phase f2；After loop losing lock, count value NxIt is a positive integer, the output state of impulse controller
Change, output pulse signal 2Nfc；As output NxAfter individual pulse signal, N is judgedxParity：NxDuring for even number, fmulFor
Output waveform before losing lock, NxDuring for odd number, fmulAnti-phase output waveform before output and losing lock.
The step 5) in, as output waveform fmulInsertion NxAfter individual pulse signal, by Fractional-N frequency, comparison frequency fcom's
Phase is advanced by π Nx/N。
Technique effect of the invention is as follows：
The all-digital phase-locked loop and implementation method of a kind of quick lock in that the present invention is provided, for traditional total letter lock phase
Ring, is improved to forward-backward counter and plus-minus impulse controller part, by controlling phase-locked loop external timing signal, can be with
The capture of phaselocked loop is completed in a cycle, quick lock in is realized, can be used for PGC demodulation and the frequency multiplication letter to frequency signal
Number generation, especially in lock phase velocity requirement circuit design high, the present invention has fairly obvious advantage.
Brief description of the drawings
Fig. 1 is traditional all-digital phase-locked loop principle schematic.
Fig. 2 is a kind of all-digital phase-locked loop principle schematic of quick lock in of the invention.
Fig. 3 is the input and output sequential chart of phase discriminator of the present invention.
Fig. 4 a are that impulse controller of the present invention is f in original state1、NxInput-output wave shape figure during for even number.
Fig. 4 b are that impulse controller of the present invention is f in original state1、NxInput-output wave shape figure during for odd number.
Fig. 4 c are that impulse controller of the present invention is f in original state2、NxInput-output wave shape figure during for even number.
Fig. 4 d are that impulse controller of the present invention is f in original state2、NxInput-output wave shape figure during for odd number.
Fig. 5 a are that the present invention is f in original state except N-counter1、NxInput-output wave shape figure during for even number.
Fig. 5 b are that the present invention is f in original state except N-counter1、NxInput-output wave shape figure during for odd number.
Fig. 5 c are that the present invention is f in original state except N-counter2、NxInput-output wave shape figure during for even number.
Fig. 5 d are that the present invention is f in original state except N-counter2、NxInput-output wave shape figure during for odd number.
Specific embodiment
Embodiments of the invention are further described below in conjunction with accompanying drawing.
As shown in Fig. 2 being a kind of all-digital phase-locked loop principle schematic of quick lock in of the invention.
A kind of all-digital phase-locked loop of quick lock in, including phase discriminator, phase error counter, frequency divider, Pulse Width Control
Device and except N-counter, phase discriminator is by incoming frequency fiWith comparison frequency fcomPhase demodulation is carried out, the error signal v that will be producedoInput to
Phase error counter；Phase error counter is to error signal voCounted, produced count value NxInput to the pulse control
Device processed；Frequency divider is to external clock 2NfcTwo divided-frequency is carried out, generation frequency is identical, the two-way frequency signal f of 180 ° of phase difference1
And f2Also impulse controller is inputed to；Impulse controller is according to count value Nx, to frequency signal f1、f2、2NfcCarry out selectivity defeated
Go out, the frequency-doubled signal f that will be producedmulInput to except N-counter；Except the frequency-doubled signal f that N-counter is exported to impulse controllermul
Carry out N times to divide, produce and incoming frequency fiThe comparison frequency f that frequency is identical, phase is consistentcom；The external clock 2NfcIn
N be the divider ratio in loop except N-counter, fcIt is loop center frequency, and fc≈fi,
The implementation method of the all-digital phase-locked loop of above-mentioned quick lock in, comprises the following steps：
1) by phase discriminator to incoming frequency fiWith comparison frequency fcomPhase demodulation is carried out, error signal v is producedo；
2) by phase error counter to error signal voCounted, produced count value Nx；
3) by frequency divider to external clock 2NfcTwo divided-frequency is carried out, generation frequency is identical, the two-way of 180 ° of phase difference
Frequency signal f1And f2；
4) impulse controller is according to count value NxSize and parity, to frequency signal f1、f2、2NfcSelectivity output,
Control impulse controller output waveform fmulOutput state, change waveform fmulFrequency size, so that comparison frequency after frequency dividing
fcomPhase and incoming frequency fiUnanimously；
5) except N-counter is to the output waveform f of impulse controllermulCarry out N times to divide, produce and incoming frequency fiFrequency
The consistent comparison frequency f of identical, phasecom；
The external clock 2NfcIn N be the divider ratio in loop except N-counter, fcIt is loop center frequency, and fc≈
fi,
Wherein, step 1) in, using edging trigger phase discriminator to incoming frequency fiWith comparison frequency fcomPhase demodulation is carried out, is produced
Raw error signal vo, its input and output sequential chart is as shown in Figure 3.Error signal voIt is rising edge trigger signal, in incoming frequency fi
With comparison frequency fcomRising edge triggered, i.e., as incoming frequency fiSet, comparison frequency f during for rising edgecomTo rise
Along when reset, otherwise its output state keep it is constant.Error signal voSet level and phase error thetaeIt is directly proportional, thus it is logical
Cross error signal voDutycycle, incoming frequency f can be obtainediWith comparison frequency fcomPhase error size.
Step 2) in, by external clock 2NfcTo error signal voSet level counted, obtain count value Nx。
Can be obtained by Fig. 3, after loop losing lock, frequency size and the incoming frequency f of error signaliIdentical, then external clock is to error signal vo
The count value of complete cycle is 2N.Therefore by counting, phase error theta is quantifiede, obtain count value NxWith phase error thetaeRatio
Relation is：
Then count value NxExpression formula be：
Therefore the set level of error signal is counted using counter register, when error signal is reset level
When, the value of counter register is assigned to Nx, while emptying register, restart to count in next set level.Therefore
As incoming frequency fiWith comparison frequency fcomWhen phase difference is about 2 π, error signal dutycycle is close to 1, count value NxAbout 2N；When
During phase lock loop locks, incoming frequency fiWith comparison frequency fcomPhase difference is 0, and now error signal does not exist set level, is counted
Value Nx=0, then count value NxScope is 0≤Nx<2N, i.e., when loop is in the lock state, count value Nx=0, when loop losing lock
When, count value NxFor a positive integer no more than phase error capacitance 2N；And by count value Nx, can obtain incoming frequency with
The phase difference of comparison frequency is π Nx/N.Meanwhile, phase error counter can as the loop filter of all-digital phase-locked loop,
The random noise and interference signal in error signal are filtered, High frequency filter is realized, interference of the effective removal noise to loop.
Step 4) in, impulse controller passes through count value Nx, to f1、f2And 2NfcThree kinds of frequency selection outputs, controlled output
Waveform fmul, so as to change comparison signal fcomOutput frequency, adjust its phase size.When i.e. loop is lock-out state, Nx=
0, the output waveform of impulse controller, i.e. frequency-doubled signal fmulIt is f1Or f2(f1With f2It is anti-phase)；After loop losing lock, count value
NxIt is a positive integer, the output state of impulse controller changes, output pulse signal 2Nfc；As output NxIndividual pulse letter
After number, N is judgedxParity：NxDuring for even number, fmulIt is the output waveform before losing lock, NxDuring for odd number, fmulBefore losing lock
Output waveform is anti-phase.For example, during loop-locking, the output waveform of impulse controller is f1, after loop losing lock, if NxIt is idol
Number, impulse controller output NxAfter individual pulse signal, output waveform is changed into f1；If NxIt is odd number, impulse controller output NxIt is individual
After pulse signal, output waveform is changed into f24 kinds of input-output wave shape figures of impulse controller are as shown in Fig. 4 a, 4b, 4c, 4d.
As shown in fig. 4 a, when loop is lock-out state, the output waveform f of impulse controllermulIt is f1, after loop losing lock, then
The output state of impulse controller changes, and starts output pulse signal 2Nfc；As the count value N of impulse controller inputxFor
Even number (makes Nx=4), then export NxAfter individual pulse signal, output state changes again, fmulOriginal state is returned to, is continued defeated
Go out clock frequency f1；
As shown in Figure 4 b, when loop is lock-out state, the output waveform f of impulse controllermulIt is f1, after loop losing lock, then
The output state of impulse controller changes, and starts output pulse signal 2Nfc；As the count value N of impulse controller inputxFor
Odd number (makes Nx=3), then export NxAfter individual pulse signal, output state changes again, fmulOutput clock frequency f2；
As illustrated in fig. 4 c, when loop is lock-out state, the output waveform f of impulse controllermulIt is f2, after loop losing lock, then
The output state of impulse controller changes, and starts output pulse signal 2Nfc；As the count value N of impulse controller inputxFor
Even number (makes Nx=4), then export NxAfter individual pulse signal, output state changes again, fmulOriginal state is returned to, is continued defeated
Go out clock frequency f2；
As shown in figure 4d, when loop is lock-out state, the output waveform f of impulse controllermulIt is f1, after loop losing lock, then
The output state of impulse controller changes, and starts output pulse signal 2Nfc；As the count value N of impulse controller inputxFor
Odd number (makes Nx=3), then export NxAfter individual pulse signal, output state changes again, fmulOutput clock frequency f1。
Therefore impulse controller passes through count value NxSize and parity, control impulse controller output state, change
Become waveform fmulFrequency size, so that comparison frequency f after frequency dividingcomPhase and incoming frequency fiUnanimously.
Step 5) in, except N-counter is to the output waveform f of impulse controllermulFractional-N frequency is carried out, comparison frequency f is obtainedcom。
As output waveform fmulInsertion NxAfter individual pulse signal, by Fractional-N frequency, comparison frequency fcomPhase be advanced by π Nx/N.Work as loop
During stabilization, comparison frequency fcomWith incoming frequency fiEqual in magnitude, phase it is consistent.Correspondence step 4) in impulse controller 4 in
Output situation, as divider ratio N=16, except the input-output wave shape figure of N-counter is as shown in Fig. 5 a, 5b, 5c, 5d.
As shown in Figure 5 a, as the input waveform f except N-countermulFor Fig. 4 a output state when, by after Fractional-N frequency, its
Output waveform fcomPhase compare f1The phase of/N (except the output waveform of N-counter before losing lock) shifts to an earlier date π/4；As shown in Figure 5 b, when
Except the input waveform f of N-countermulFor Fig. 4 b output state when, by after Fractional-N frequency, its output waveform fcomPhase compare f1/
The phase of N (except the output waveform of N-counter before losing lock) shifts to an earlier date 3 π/16；As shown in Figure 5 c, when the input waveform except N-counter
fmulFor Fig. 4 c output state when, by after Fractional-N frequency, its output waveform fcomPhase compare f2/ N is (except N-counter before losing lock
Output waveform) phase shift to an earlier date π/4；As fig 5d, as the input waveform f except N-countermulFor Fig. 4 d output state when,
By after Fractional-N frequency, its output waveform fcomPhase compare f2The phase of/N the output waveform of N-counter (before losing lock except) shift to an earlier date 3 π/
16。
Therefore, except N-counter is by dividing, obtain and incoming frequency fiThe comparison frequency f of same frequencycom.Meanwhile, pass through
The Pulse Width Control output of impulse controller, makes comparison frequency f after frequency dividingcomPhase shift to an earlier date：
As incoming frequency fiWith comparison frequency fcomPhase difference be θ (0≤θ<2 π) when, by the phase error to both
Counted, adjusted the frequency size of impulse controller output waveform, so that the phase of output frequency shifts to an earlier date θ after frequency dividing, it is real
Existing looped phase locking function.From formula (3), with count value NxChange, comparison frequency f after frequency dividingcomPhase place change scope
It is 0≤Δ θ<2 π, therefore phaselocked loop can realize loop-locking in a cycle.
It is hereby stated that, it is described above to contribute to skilled artisan understands that the invention, but not limit the present invention
The protection domain of creation.It is any equivalent described above, modification are improved without departing from the invention substance
And/or the implementation deleted numerous conforming to the principle of simplicity and carry out, each fall within the protection domain of the invention.
Claims (6)
1. a kind of all-digital phase-locked loop of quick lock in, it is characterised in that the phaselocked loop reaches locking shape in a cycle
State；Including phase discriminator, phase error counter, frequency divider, impulse controller and except N-counter, the phase discriminator will be input into frequency
Rate fiWith comparison frequency fcomPhase demodulation is carried out, the error signal v that will be producedoInput to the phase error counter；The phase
Error counter is to error signal voCounted, produced count value NxInput to the impulse controller；The frequency divider is external
Portion clock 2NfcTwo divided-frequency is carried out, generation frequency is identical, the two-way frequency signal f of 180 ° of phase difference1And f2Also input to described
Impulse controller；The impulse controller is according to count value Nx, to frequency signal f1、f2、2NfcSelective output is carried out, will be produced
Raw frequency-doubled signal fmulInput to described except N-counter；The frequency-doubled signal f exported to impulse controller except N-countermul
Carry out N times to divide, produce and incoming frequency fiThe comparison frequency f that frequency is identical, phase is consistentcom；The external clock 2NfcIn
N be divider ratio except N-counter, fcIt is loop center frequency, and fc≈fi,
2. a kind of implementation method of the all-digital phase-locked loop of quick lock in as claimed in claim 1, it is characterised in that by holding
It is continuous to insert external clock pulse to change the phase size of comparison frequency, comprise the following steps：
1) by phase discriminator to incoming frequency fiWith comparison frequency fcomPhase demodulation is carried out, error signal v is producedo；
2) again by phase error counter to error signal voCounted, produced count value Nx；
3) by frequency divider to external clock 2NfcTwo divided-frequency is carried out, generation frequency is identical, the two-way frequency letter of 180 ° of phase difference
Number f1And f2；
4) impulse controller is according to count value NxSize and parity, to frequency signal f1、f2、2NfcSelectivity output, control
The frequency-doubled signal f of impulse controller outputmulOutput state, change frequency-doubled signal fmulFrequency size so that frequency dividing after
Comparison frequency fcomPhase and incoming frequency fiUnanimously；
5) except the frequency-doubled signal f that N-counter is exported to impulse controllermulCarry out N times to divide, produce and incoming frequency fiFrequency phase
The consistent comparison frequency f of same, phasecom；
The external clock 2NfcIn N be the divider ratio in loop except N-counter, fcIt is loop center frequency, and fc≈fi,
3. the implementation method of the all-digital phase-locked loop of quick lock according to claim 2, it is characterised in that to input frequency
Rate and comparison frequency carry out phase demodulation；The step 1) in, using edging trigger phase discriminator to incoming frequency fiWith comparison frequency fcom
Phase demodulation is carried out, error signal v is producedo；The error signal voIt is rising edge trigger signal, in incoming frequency fiWith comparison frequency
fcomRising edge triggered, i.e., as incoming frequency fiSet, comparison frequency f during for rising edgecomResetted during for rising edge, it is no
Then its output state keeps constant.
4. the implementation method of the all-digital phase-locked loop of quick lock according to claim 3, it is characterised in that to input frequency
The phase difference of rate and comparison frequency is quantified；The step 2) in, by external clock 2NfcTo error signal voSet electricity
It is flat to be counted, obtain count value Nx, in the range from 0≤Nx<2N, i.e., when loop is in the lock state, count value Nx=0, when
During loop losing lock, count value NxFor a positive integer no more than phase error capacitance 2N；And by count value Nx, can obtain defeated
It is π N to enter frequency with the phase difference of comparison frequencyx/N。
5. the implementation method of the all-digital phase-locked loop of quick lock according to claim 4, it is characterised in that by insertion
Pulse signal changes the phase and frequency size of comparison frequency；The step 4) in, when loop is lock-out state, Nx=0, pulse
The output waveform of controller, i.e. frequency-doubled signal fmulIt is f1Or and f1Anti-phase f2；After loop losing lock, count value NxIt is one
Positive integer, the output state of impulse controller changes, output pulse signal 2Nfc；As output NxAfter individual pulse signal, judge
NxParity：NxDuring for even number, fmulIt is the output waveform before losing lock, NxDuring for odd number, fmulExport anti-phase defeated with before losing lock
Go out waveform.
6. the implementation method of the all-digital phase-locked loop of quick lock according to claim 5, it is characterised in that after frequency dividing
The phase of comparison frequency is consistent with incoming frequency；The step 5) in, as output waveform fmulInsertion NxAfter individual pulse signal, warp
Cross Fractional-N frequency, comparison frequency fcomPhase be advanced by π Nx/N。
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| CN104639158B (en) * | 2014-12-30 | 2018-08-14 | 广东大普通信技术有限公司 | Synchronous two phase-locked loop adjusting method |
| CN111446960B (en) * | 2020-04-16 | 2023-05-12 | 浙江大华技术股份有限公司 | Clock output circuit |
| CN111510115B (en) * | 2020-04-17 | 2023-05-09 | 科华数据股份有限公司 | Multi-pulse waveform rectification trigger circuit based on phase-locked loop |
| CN112152611A (en) * | 2020-09-30 | 2020-12-29 | 湖北理工学院 | Digital phase-locked loop |
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