CN105281752A - Clock data recovery system based on digital phase-locked loop - Google Patents
Clock data recovery system based on digital phase-locked loop Download PDFInfo
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- CN105281752A CN105281752A CN201510673804.2A CN201510673804A CN105281752A CN 105281752 A CN105281752 A CN 105281752A CN 201510673804 A CN201510673804 A CN 201510673804A CN 105281752 A CN105281752 A CN 105281752A
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Abstract
The invention belongs to the field of digital signal processing, and in particular relates to a clock data recovery system based on a digital phase-locked loop. The clock data recovery system comprises a phase discriminator, a digital filter, a numerically controlled oscillator and a frequency divider; the phase discriminator is connected with the digital filter; the digital filter is connected with the numerically controlled oscillator; the numerically controlled oscillator is connected with the frequency divider; the frequency divider is connected with the phase discriminator; the phase discriminator is an exclusive or gate phase discriminator; the digital filter is a K variable-modulus add-subtract counter; the numerically controlled oscillator is a pulse add-subtract module; and the frequency divider is an N frequency divider. The clock data recovery system based on the digital phase-locked loop disclosed by the invention overcomes the disadvantages of direct-current zero drift, and device saturation, and being easily influenced by power supply and environment temperature change and the like.
Description
Technical field
The invention belongs to digital processing field, particularly relate to a kind of clock data recovery system realized based on digital phase-locked loop.
Background technology
Along with the lifting of data rate, serial data system transfers structure change in clock signal and transmission channel thereof there occurs some change, mainly concentrate on, in the serial data system of current a new generation, as Ethernet, SATA, SONET/SDH etc., without special clock signal transmission passage, but clock signal has been embedded in data transmits, therefore must at receiving terminal by clock recovery out.
In high-speed serial data test, eye pattern and jitter test are most important two test events.In eye pattern and jitter measurement, tester must recover reference clock from signal to be tested, by this clock synchronous and sampled data.Therefore, the method for recovered clock can directly affect eye pattern and jitter test result.
At the receiving terminal of system, CDR (real-time clock restore circuit) recovers clock from serial data, carrys out synchronous serial data, sample with the clock recovered.Mainly contain two kinds of modes at present and carry out clock recovery, one uses phase interpolator (phaseinterpolator is called for short PI); Another kind of for using phase-locked loop (Phaselockloop is called for short PLL).
Phase interpolator is mainly used in FBDIMM and PCIExpress, this CDR uses PLL or DLL to be used as reference loop, this loop receives the reference frequency signal of input, and produces one group of high-frequency signal as reference phase place, and these phase places are uniformly distributed between 0 ~ 360 degree.Fixed phase will be provided to CDR loop, and this loop inputs insertion phases, to produce the output signal being positioned at intermediate phase to two that are positioned at out of phase.
Phase-locked loop (PLL:Phase-lockedloops) be a kind of utilize feedback control principle to realize frequency and the simultaneous techniques of phase place, its effect is that the clock that circuit exports is kept synchronous with the reference clock of its outside.When the frequency of reference clock or phase place change, phase-locked loop can detect this change, and carrys out regulation output frequency by the reponse system of its inside, until both re-synchronizations, to be thisly synchronously also called " phase-locked ".
PHASE-LOCKED LOOP PLL TECHNIQUE is widely used in radio, communication and computer realm, is often used as and produces stable frequency, restoring signal from noisy communications channel, or for the distributed clock synchronization of microprocessor in Logical Design.Since complete phase-locked loop module can realize in independent integrated circuit, this technology is widely used in modern electronic equipment.
Composition module and the concise and to the point functional description of a phase-locked loop circuit are as follows:
(1) phase frequency detector (PFD) (or phase discriminator: PD): the comparison reference signal of input and the signal of feedback loop being carried out to frequency and phase place, exports the signal of both representatives difference to low pass filter.
(2) low pass filter (LPF): by the radio-frequency component filtering in input signal, retains direct current component and delivers to voltage controlled oscillator.
(3) voltage controlled oscillator (VCO): export the periodic reference signal that has degree of precision and stability, its frequency controlled by input voltage.
(4) feedback loop (usually being realized by a frequency divider (Divider)): the signal that voltage controlled oscillator exports is returned to phase frequency detector.The frequency of the output signal of usual voltage controlled oscillator is greater than the frequency of reference signal, therefore need add frequency divider to reduce frequency at this
Usually the method utilizing PHASE-LOCKED LOOP PLL TECHNIQUE to extract bit synchronization signal from serial data stream is called phase locking technique, be specifically divided into two classes: a class is that error signal in loop can continuous print adjusted position synchronizing signal phase place, and this class belongs to simulation phase locking technique; The oscillator of another kind of employing high stability, that obtain from phase discriminator be not directly used in adjustment oscillator with error signal that is bit synchronization error-proportional, but it is additional or deduct one or several pulse in the pulse train exported at signal clock by a controller, thus reach the phase place that adjustment is added to the bit synchronization pulse train on phase discriminator, to reach bit synchronous object.This kind of circuit can form all-digital phase-lock loop by digital circuit completely.Because the phase place adjustment of this loop to bit synchronization signal is not continuous print, but the unit of adjustment that existence one is minimum, therefore minimum unit of adjustment is existed to the adjustment of bit synchronization signal, therefore this synchronous ring is also called quantification synchronizer.This digital ring forming quantification synchronizer is a kind of typical apply of digital phase-locked loop.
For phase-locked loop, the performance index of most critical are phase noise (Phasenoise) and dynamic property.The overall performance impact on communication system of the phase noise of phase-locked loop is very large, requires concrete and strict index request therefore to phase noise in design.The dynamic property of phase-locked loop determines it can the speed in reference synchronization source and precision, and can track reference source in much scopes.The dynamic property of phase-locked loop comprises: locking time (Locktime), capture range (Capturerange), lock-in range (Holdrange) etc.In addition, the stability indicator of phase-locked loop comprises: loop bandwidth (Loopbandwidth), phase margin (Phasemarge) etc.
The direct current null offset of analog phase-locked look, device is saturated and be subject to the shortcoming such as power supply and variation of ambient temperature, has become the direction of Phase Lock Technique development.
Summary of the invention
The invention provides a kind of clock data recovery system realized based on digital phase-locked loop, to improve null offset, and be subject to the shortcoming such as power supply and variation of ambient temperature, improve overall dynamic property.
To achieve these goals, the present invention adopts following technical scheme: a kind of clock data recovery system realized based on digital phase-locked loop, comprise phase discriminator, digital filter, digital controlled oscillator and frequency divider, described phase discriminator is connected with digital filter, described digital filter is connected with digital controlled oscillator, described digital controlled oscillator is connected with frequency divider, and described frequency divider is connected with phase discriminator; Described phase discriminator adopts XOR gate phase discriminator, and described digital filter adopts K to become the forward-backward counter of mould, and described digital controlled oscillator adopts pulse plus-minus module, and described frequency divider adopts Fractional-N frequency device.
Preferably, described phase discriminator, digital filter, digital controlled oscillator and frequency divider are integrated on one piece of fpga chip.
Preferably, described fpga chip adopts model in Virtex-4 to be the chip of xc4vsx55.
Method for protecting software for pwm signal of the present invention, can improve the reliability of pwm signal, thus improve the reliability of whole inverter.
What the clock data recovery system realized based on digital phase-locked loop of the present invention adopted is all-digital phase-locked loop, and all-digital phase-locked loop (ADPLL) is a kind of phase feedback control system.It is sent in digital loop filters DLF the smoothing filtering of phase error signal according to phase error (the advanced or delayed) signal between input signal and local recovery clock Fout, and the phase place lead-lag adjustment generating control DCO action exports control signal, the instruction that DCO provides according to control signal, utilize plus-minus pulse control circuit control phase, by continuously feedback regulation, make the phase place of the Phase Tracking input signal stream of its output clock Fout.Overcome direct current null offset, device is saturated and be subject to the shortcoming such as power supply and variation of ambient temperature.
Accompanying drawing explanation
Fig. 1 is modular structure schematic diagram of the present invention;
Fig. 2 is the all-digital phase-locked loop circuit based on programmable logic gate array that eda software comprehensively goes out.
Embodiment
Below in conjunction with embodiment, content of the present invention is further described.
A kind of clock data recovery system realized based on digital phase-locked loop, comprise phase discriminator, digital filter, digital controlled oscillator and frequency divider, described phase discriminator is connected with digital filter, described digital filter is connected with digital controlled oscillator, described digital controlled oscillator is connected with frequency divider, and described frequency divider is connected with phase discriminator; Described phase discriminator adopts XOR gate phase discriminator, and described digital filter adopts K to become the forward-backward counter of mould, and described digital controlled oscillator adopts pulse plus-minus module, and described frequency divider adopts Fractional-N frequency device.
Described phase discriminator, digital filter, digital controlled oscillator and frequency divider are integrated on one piece of fpga chip.
Described fpga chip adopts model in Virtex-4 to be the chip of xc4vsx55.
Phase-locked loop is a phase feedback control system, in digital phase-locked loop, because error controling signal is discrete digital signal, instead of analog voltage, the change of thus controlled output voltage is discrete instead of continuous print; In addition, loop building block also uses digital circuit entirely, so this phase-locked loop is just referred to as all-digital phase-locked loop (ADPLL), it is formed primarily of digital phase discriminator DPD, digital loop filters DLF, digital controlled oscillator DCO and frequency divider (controlled change mould N) 4 part, wherein the clock frequency of digital controlled oscillator and digital loop filters is 2NFc, wherein Fc is loop center frequency, differs 180 degree.
All-digital phase-locked loop (ADPLL) is a kind of phase feedback control system.It is sent in digital loop filters DLF the smoothing filtering of phase error signal according to phase error (the advanced or delayed) signal between input signal and local recovery clock F_out, and the phase place lead-lag adjustment generating control DCO action exports control signal, the instruction that DCO provides according to control signal, utilize plus-minus pulse control circuit control phase, by continuously feedback regulation, make the phase place of the Phase Tracking input signal stream of its output clock F_out.
The workflow of all-digital phase-locked loop can be described below:
As shown in Figure 1, (1) when loop losing lock, phase difference between digital phase discriminator (DPD) comparator input signal (F_in) and output signal (F_recover), and the control signal (phase_detect) producing control figure loop filter counting; Conventional digital phase discriminator has three types: JK triggers phase discriminator (JK-flipflopPD) Nyquist phase discriminator (NRPD) and Hilbert transform phase discriminator.XOR gate (XOR) phase discriminator triggering phase discriminator principle based on JK is adopted in the present invention.When using XOR gate phase discriminator, its output error signal phase_detect is as the counting direction signal of digital loop filters.During loop-locking, phase_detect is the square wave of a duty ratio 50%, and absolute phase difference is now 90 °.Therefore the XOR gate phase discriminator phase difference limit is ± 90 °.
(2) digital loop filters (DLF) adjusts internal count value according to counting direction control signal (phase_detect), thus domination number controlled oscillator adjustment phase place.Carry out subtracting counting when phase_detect is high, and when count value arrives 0, output borrow pulse signal (borrow); For low carrying out adds counting, and when count value reaches default K modulus value, output carry pulse signal (carryo); Pulse addition and subtraction circuit then carries out increase and the deduction operation of pulse in circuit output signal (idout) according to carry pulse signal (carryo) and borrow pulse signal (borrow), adjust the frequency of output signal; Repeat adjustment process above, when loop enters lock-out state, the output phase_detect of DPD is the square wave of a duty ratio 50%, K becomes mould forward-backward counter and then periodically produces carry pulse output carry and borrow pulse output borrow, causes the output idout of pulse addition and subtraction circuit periodically add and deduct half pulse.Like this frequency exported is not affected, also just based on this principle, the noise that equiprobability occurs can be removed easily.
The performance impact tracking speed of digital loop filters and the stability of tracking.Advanced and the phase lag signal of the phase place that this module exports can the phase place of control DCO adjust.Its loop bandwidth can regulate according to actual requirement.Phase-locked loop (PLL) bandwidth of clock recovery module decides in input data has how many shake can be transferred in the clock of recovery.The wider shake be transferred in recovered clock of PLL bandwidth is more, thus can reduce the amount of jitter shown in eye pattern.Narrower PLL bandwidth can make clock signal more clean, and the eye pattern of generation also will demonstrate real jitter conditions in input data more accurately.The modulus of DLF internal counter should be set according to system requirements in practical application.
(3) digital controlled oscillator (DCO:DigitalControlledOscillator), is responsible for phase place adjustment, is controlled by the system generated clock of frequency stabilization.What digital controlled oscillator adopted is pulse addition and subtraction circuit.Clock is 2Nfc.When not having carry/borrow signal, its output carries out two divided-frequency to external clock; When there being carry signal increase to input, then in original signal, insert half pulse, to improve the frequency of original signal; When there being borrow signal decrease to input, then deduct half pulse, to reduce the frequency of original signal.
(4) programmable frequency divider: carry out predetermined frequency division to the clock signal that DCO exports, obtains the clock signal that phase place follows input signal stream change.
Claims (3)
1. the clock data recovery system realized based on digital phase-locked loop, it is characterized in that: comprise phase discriminator, digital filter, digital controlled oscillator and frequency divider, described phase discriminator is connected with digital filter, described digital filter is connected with digital controlled oscillator, described digital controlled oscillator is connected with frequency divider, and described frequency divider is connected with phase discriminator; Described phase discriminator adopts XOR gate phase discriminator, and described digital filter adopts K to become the forward-backward counter of mould, and described digital controlled oscillator adopts pulse plus-minus module, and described frequency divider adopts Fractional-N frequency device.
2. the clock data recovery system realized based on digital phase-locked loop according to claim 1, is characterized in that: described phase discriminator, digital filter, digital controlled oscillator and frequency divider are integrated on one piece of fpga chip.
3. the clock data recovery system realized based on digital phase-locked loop according to claim 2, is characterized in that: described fpga chip adopts model in Virtex-4 to be the chip of xc4vsx55.
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| CN106603449A (en) * | 2016-04-29 | 2017-04-26 | 福建先创电子有限公司 | Clock synchronization FPGA structure and clock synchronization method based on GAD timing detection position |
| WO2017152412A1 (en) * | 2016-03-11 | 2017-09-14 | 华为技术有限公司 | Device and method for supporting clock transfer in multiple clock domains |
| CN107786202A (en) * | 2017-11-09 | 2018-03-09 | 上海华力微电子有限公司 | A kind of lock indicator circuit that function is eliminated with error code |
| CN112152611A (en) * | 2020-09-30 | 2020-12-29 | 湖北理工学院 | Digital phase-locked loop |
| CN116846530A (en) * | 2023-06-29 | 2023-10-03 | 北京邮电大学 | Optical switching network based on whole network clock frequency synchronization, data transmitting and receiving method |
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| CN107786202A (en) * | 2017-11-09 | 2018-03-09 | 上海华力微电子有限公司 | A kind of lock indicator circuit that function is eliminated with error code |
| CN107786202B (en) * | 2017-11-09 | 2021-10-01 | 上海华力微电子有限公司 | Locking indicator circuit with error code eliminating function |
| CN112152611A (en) * | 2020-09-30 | 2020-12-29 | 湖北理工学院 | Digital phase-locked loop |
| CN116846530A (en) * | 2023-06-29 | 2023-10-03 | 北京邮电大学 | Optical switching network based on whole network clock frequency synchronization, data transmitting and receiving method |
| CN116846530B (en) * | 2023-06-29 | 2024-03-19 | 北京邮电大学 | Optical switching network based on whole network clock frequency synchronization, data transmitting and receiving method |
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Application publication date: 20160127 |