CN204168277U - A kind of delay phase-locked loop prevents the circuit of wrong lock - Google Patents
A kind of delay phase-locked loop prevents the circuit of wrong lock Download PDFInfo
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- CN204168277U CN204168277U CN201420574507.3U CN201420574507U CN204168277U CN 204168277 U CN204168277 U CN 204168277U CN 201420574507 U CN201420574507 U CN 201420574507U CN 204168277 U CN204168277 U CN 204168277U
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Abstract
A kind of delay phase-locked loop of the utility model prevents the circuit of wrong lock, comprises DLL delay chain, DLL phase discriminator, DLL logic control circuit, FB feedback circuit, input clock frequency divider and feedback clock frequency divider; Input clock exports output clock after DLL delay chain postpones; Output clock is output feedack clock after FB feedback circuit; DLL phase discriminator compares the phase place of input clock through frequency division and feedback clock; The output clock that DLL logic control circuit produces according to the output control DLL delay chain of phase compare; Input clock frequency divider and feedback clock frequency divider are respectively used to input clock and feedback clock two divided-frequency.Respectively scaling down processing is carried out to input clock and feedback clock by input clock frequency divider and feedback clock frequency divider, frequency is reduced by twice, corresponding for trailing edge in the original signal moment is assigned in crest or trough by frequency division, has evaded the locking that DLL makes a mistake at the trailing edge of feedback clock completely.
Description
Technical field
The utility model relates to a kind of integrated circuit, is specially the circuit that a kind of delay phase-locked loop prevents wrong lock.
Background technology
Delay phase-locked loop (Delay-locked Loop is called for short DLL) technology is improved and is obtained, is widely used in sequential field in PLL technology.It inherits the Phase Lock Technique of PLL circuit, but eliminates the oscillator section in PLL circuit, the substitute is a controllable delay line of retardation.Compared with PLL, DLL does not shake cumulative, less locking time, the advantages such as loop filter is easy of integration.
In the middle of prior art, as shown in Figure 1, when input clock enters DLL delay chain, output clock is produced after postponing, output clock produces feedback clock after feedback circuit, the signal that input clock and feedback clock export UP or DN after DLL phase discriminator carries out phase compare goes increase or the minimizing of control DLL delay chain to DLL logic control circuit, until the phase alignment of input clock and feedback clock.Its locking process comprises three states: the state 0 of finite state machine, and as shown in Figure 2: UP=0, feedback clock is relative to Td0=tdll time of delay of input clock
min+ tfb, (wherein tdll
minbe the initial delay time of DLL delay chain, tfb is the time of delay of FB feedback circuit), force tdll time of delay increasing DLL delay chain; The state 1 of finite state machine, as shown in Figure 3: change to UP=1 by UP=0, finite state machine to get the hang of 1, Td1=tdll+tfb from state 0, forces to increase tdll; The state 2 of finite state machine, as shown in Figure 4, changes to UP=0 by UP=1, finite state machine from state 1 get the hang of 2, td2=tdll+tfb=TCK, DLL locking.If DN=1, reduce tdll; If UP=1, increase tdll; Ensure that the rising edge of feedback clock and the rising edge of input clock are alignment always with this.
In the middle of the process that this circuit performs, there is following problem: the condition being jumped to state 2 by state 1 is that UP=1 jumps to UP=0.If the trailing edge of the rising edge of input clock or feedback clock has shake, as shown in Figure 5, what mistake had appearred in UP jumps to 0 by 1, state machine also can mistake jump to state 2 by state 1, be exactly so the rising edge of input clock and the trailing edge alignment of feedback clock, wrong lock occurs, and the target of DLL is the rising edge of input clock and the rising edge alignment of feedback clock.
Utility model content
For problems of the prior art, the utility model provides a kind of structure simple, and wrong lock can not occur, and the delay phase-locked loop of reliable operation prevents the circuit of wrong lock.
The utility model is achieved through the following technical solutions:
A kind of delay phase-locked loop of the utility model prevents the circuit of wrong lock, comprises DLL delay chain, DLL phase discriminator, DLL logic control circuit, FB feedback circuit, input clock frequency divider and feedback clock frequency divider; Input clock exports and obtains output clock after DLL delay chain postpones; Output clock is output feedack clock after FB feedback circuit; DLL phase discriminator compares the phase place through the input clock of input clock frequency divider frequency division and the feedback clock through feedback clock frequency divider frequency division; The output clock that DLL logic control circuit produces according to the output control DLL delay chain of phase compare; Input clock frequency divider and feedback clock frequency divider are respectively used to input clock and feedback clock two divided-frequency.
Preferably, the input clock that exports respectively of input clock frequency divider and feedback clock frequency divider and feedback clock are input in the shift register of DLL phase discriminator; Feedback clock wherein after frequency division is connected to the data terminal of shift register, and the input clock after frequency division is connected to the clock end of shift register.
Compared with prior art, the utility model has following useful technique effect:
The utility model carries out scaling down processing to input clock and feedback clock respectively by the input clock frequency divider that arranges respectively and feedback clock frequency divider, frequency is reduced by twice, namely will increase by twice in the cycle, thus corresponding for the trailing edge in the original signal moment has been assigned in crest or trough by frequency division, each state variation moment corresponding be rising edge in original signal, therefore after the signal after frequency division being entered horizontal phasing control, even if there is shake, also be the rising edge of input clock and the rising edge alignment of feedback clock in its original signal, thus the trailing edge of the rising edge and feedback clock that avoid input clock meets, evade the locking that DLL makes a mistake at the trailing edge of feedback clock completely.
Further, using the data terminal of the feedback clock after frequency division as shift register, the input clock after frequency division is as clock end; Namely to sample the feedback clock after frequency division with the input clock after frequency division, thus the phase relation of the input clock after frequency division and the feedback clock after frequency division can be obtained, provide basis for estimation for DLL phase discriminator sends the signal UP increasing DLL delay chain or the signal DN reducing delay chain.
Accompanying drawing explanation
Fig. 1 is DLL circuit structure diagram in prior art.
Fig. 2 is the working timing figure of the state 0 of finite state machine in prior art DLL locking process.
Fig. 3 is the working timing figure of the state 1 of finite state machine in prior art DLL locking process.
Fig. 4 is the working timing figure of the state 2 of finite state machine in prior art DLL locking process.
Fig. 5 is working state figure when there is wrong lock in prior art DLL locking process.
Fig. 6 is the structure chart of circuit described in the utility model.
Fig. 7 is the working timing figure of the state 0 in the utility model after frequency division.
Fig. 8 is the working timing figure of the state 1 in the utility model after frequency division.
Fig. 9 is the connection diagram of N bit shift register in the utility model.
Embodiment
Below in conjunction with specific embodiment, the utility model is described in further detail, described in be to explanation of the present utility model instead of restriction.
A kind of delay phase-locked loop of the utility model prevents the circuit of wrong lock, as shown in Figure 6, comprises DLL delay chain, DLL phase discriminator, DLL logic control circuit, FB feedback circuit, input clock frequency divider and feedback clock frequency divider, input clock exports and obtains output clock after DLL delay chain postpones, output clock is output feedack clock after FB feedback circuit, DLL phase discriminator compares the phase place through the input clock of input clock frequency divider frequency division and the feedback clock through feedback clock frequency divider frequency division, the output clock that DLL logic control circuit produces according to the output control DLL delay chain of phase compare, input clock frequency divider and feedback clock frequency divider are respectively used to the frequency of input clock and feedback clock to carry out two divided-frequency process, as shown in Figure 7, from the rising edge of each signal, the cycle expands 2 times, corresponding for trailing edge in the original signal moment has been assigned in crest or trough by frequency division, each state variation moment corresponding be rising edge in original signal, therefore after the signal after frequency division being entered horizontal phasing control, even if there is shake, also be the rising edge of input clock and the rising edge alignment of feedback clock in its original signal, thus the trailing edge of the rising edge and feedback clock that avoid input clock meets, evade the locking that DLL makes a mistake at the trailing edge of feedback clock completely.
As shown in Figure 9, the input clock that exports respectively of input clock frequency divider and feedback clock frequency divider and feedback clock are input in the shift register of N position of DLL phase discriminator; Feedback clock wherein after frequency division is connected to the data terminal of shift register, and the input clock after frequency division is connected to the clock end of shift register.Namely to sample the feedback clock after frequency division with the input clock after frequency division, thus the phase relation of the input clock after frequency division and the feedback clock after frequency division can be obtained, namely the output SR<N:0> of shift register embodies this phase relation, as shown in Figure 9, basis for estimation is provided for DLL phase discriminator sends the signal UP increasing DLL delay chain or the signal DN reducing delay chain.
The input clock of DLL phase discriminator access in delay phase-locked loop and feedback clock in use, are carried out scaling down processing by the utility model respectively, and the frequency of original clock signal is the twice of input clock after frequency division and feedback clock frequency; Then DLL phase discriminator exports the signal UP increasing delay chain and the signal DN reducing delay chain according to the output signal of shift register, control to make the rising edge of input clock and the rising edge alignment of feedback clock finally by DLL logic control circuit, obtain the state diagram after alignment as shown in Figure 8.
When a kind of delay phase-locked loop of the utility model prevents the circuit working of wrong lock, the shift register of N position connects as shown in Figure 9, and this example is described for 8 bit shift register.
The output of state 0, the N bit shift register of state machine is 00000000, and forcing increases tdll; As shown in Figure 7.
The state 1 of state machine, the output SR<N:0> of the shift register of N position becomes 00000111 from 00000000, wherein determined by the figure place of filter by the figure place of 0 change 1, Td1=tdll+tfb=tck, wherein Td1 be state 1 time feedback clock relatively and the time of delay of input clock, tdll is the time of delay of DLL delay chain, and tfb is the time of delay of FB feedback circuit, and tck is the frequency of input clock; DLL locks; As shown in Figure 8.The output SR<N:0> of the shift register of N position embodies the phase relation of the input clock after frequency division and the feedback clock after frequency division.
If DN=1, reduce tdll; If UP=1, increase tdll; The rising edge of feedback clock and the rising edge alignment of input clock is ensured with this.
The trailing edge of the rising edge and feedback clock that avoid input clock meets, thus avoids the trailing edge being locked in feedback clock of DLL mistake.
Claims (2)
1. delay phase-locked loop prevents a circuit for wrong lock, it is characterized in that, comprises DLL delay chain, DLL phase discriminator, DLL logic control circuit, FB feedback circuit, input clock frequency divider and feedback clock frequency divider; Input clock exports and obtains output clock after DLL delay chain postpones; Output clock is output feedack clock after FB feedback circuit; DLL phase discriminator compares the phase place through the input clock of input clock frequency divider frequency division and the feedback clock through feedback clock frequency divider frequency division; The output clock that DLL logic control circuit produces according to the output control DLL delay chain of phase compare; Input clock frequency divider and feedback clock frequency divider are respectively used to input clock and feedback clock two divided-frequency.
2. a kind of delay phase-locked loop according to claim 1 prevents the circuit of wrong lock, and it is characterized in that, the input clock that input clock frequency divider and feedback clock frequency divider export respectively and feedback clock are input in the shift register of DLL phase discriminator; Feedback clock wherein after frequency division is connected to the data terminal of shift register, and the input clock after frequency division is connected to the clock end of shift register.
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104253610A (en) * | 2014-09-30 | 2014-12-31 | 山东华芯半导体有限公司 | Circuit and method for preventing false locking of DLL (delay-locked loop) |
| CN105321552A (en) * | 2015-11-17 | 2016-02-10 | 西安华芯半导体有限公司 | Delay locked loop and resetting control method for same |
| CN108566195A (en) * | 2018-03-20 | 2018-09-21 | 上海集成电路研发中心有限公司 | A kind of delay phase-locked loop with broadband input range |
| CN110971230A (en) * | 2018-09-30 | 2020-04-07 | 苏州四方杰芯电子科技有限公司 | High-performance phase-locked loop circuit control system |
| CN113179099A (en) * | 2020-09-18 | 2021-07-27 | 上海司南卫星导航技术股份有限公司 | Phase-locked loop circuit, control method thereof, semiconductor device and electronic equipment |
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2014
- 2014-09-30 CN CN201420574507.3U patent/CN204168277U/en active Active
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104253610A (en) * | 2014-09-30 | 2014-12-31 | 山东华芯半导体有限公司 | Circuit and method for preventing false locking of DLL (delay-locked loop) |
| CN104253610B (en) * | 2014-09-30 | 2018-10-19 | 西安紫光国芯半导体有限公司 | A kind of delay phase-locked loop prevents the circuit and method of wrong lock |
| CN105321552A (en) * | 2015-11-17 | 2016-02-10 | 西安华芯半导体有限公司 | Delay locked loop and resetting control method for same |
| CN105321552B (en) * | 2015-11-17 | 2018-08-10 | 西安紫光国芯半导体有限公司 | A kind of delay phase-locked loop and its reset control method |
| CN108566195A (en) * | 2018-03-20 | 2018-09-21 | 上海集成电路研发中心有限公司 | A kind of delay phase-locked loop with broadband input range |
| CN110971230A (en) * | 2018-09-30 | 2020-04-07 | 苏州四方杰芯电子科技有限公司 | High-performance phase-locked loop circuit control system |
| CN110971230B (en) * | 2018-09-30 | 2023-06-30 | 苏州四方杰芯电子科技有限公司 | High-performance phase-locked loop circuit control system |
| CN113179099A (en) * | 2020-09-18 | 2021-07-27 | 上海司南卫星导航技术股份有限公司 | Phase-locked loop circuit, control method thereof, semiconductor device and electronic equipment |
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Effective date of registration: 20170428 Address after: 710075 Shaanxi City, Xi'an province high tech Road No. 38, innovation center, A, block, floor 4 Patentee after: XI'AN UNIIC SEMICONDUCTORS Co.,Ltd. Address before: Xinluo Avenue high tech Zone of Ji'nan City, Shandong province 250101 No. 1768 Qilu Software Park building B block two layer Patentee before: Shandong Sinochip Semiconductors Co., Ltd. |
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