CN108566195A - A kind of delay phase-locked loop with broadband input range - Google Patents
A kind of delay phase-locked loop with broadband input range Download PDFInfo
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- CN108566195A CN108566195A CN201810230894.1A CN201810230894A CN108566195A CN 108566195 A CN108566195 A CN 108566195A CN 201810230894 A CN201810230894 A CN 201810230894A CN 108566195 A CN108566195 A CN 108566195A
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- Prior art keywords
- module
- delay
- phase
- clock
- locked loop
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Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
- H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
- H03L7/0814—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the phase shifting device being digitally controlled
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
Abstract
The invention discloses a kind of delay phase-locked loops with broadband input range, including phase detecting module, Postponement module, control module, adjustment module and selecting module, two input ports of phase detecting module are separately connected reference clock and feedback clock, and phase state output port connects the input port of the control module；The input port of Postponement module connects the reference clock, and the input port of selecting module is separately connected the output port of control module and Postponement module, and delay cell includes at least one delay chain；Two input ports of the clock after the output port output selection of selecting module, adjustment module are separately connected counting clock and reference clock, and the output port of adjustment module connects the Postponement module.A kind of delay phase-locked loop with broadband input range provided by the invention, automatically selects delay chain so that delay phase-locked loop can work normally always, improve the operating frequency range of delay phase-locked loop by inside.
Description
Technical field
The present invention relates to IC design fields, and in particular to a kind of delay locking phase with broadband input range
Ring.
Background technology
With the development of CMOS integrated circuit technologies, clock circuit all has non-in number and analogue layout
Normal important role.But PLL (Phasel Locked Loop) phaselocked loop is essentially all to be completed using Analog Circuit Design,
The noise problem of circuit is larger, and circuit design difficulty is big, and reusability is poor.DLL (Delay Locked Loop) delay locks
The especially digital DLL circuit in circuit is determined since it is based on Digital Logic completion, circuit noise better performances, and circuit can
Durability is strong, and application is more and more extensive.
And in some circuit designs, not only clock frequency is proposed to be strict with and more the phase of clock is also extremely closed
Note.For example, being a pith for carrying out time measurement in the medium phase difference clocks of TDC；In SDRAM, it is desirable that when input
The phase of clock and output clock is strictly equal.In the field required to phase, the effect of DLL is just more prominent.And for complete
Digital dll causes DLL reusabilities to be deteriorated since the limitation of delay cell number causes DLL operating frequency ranges limited.
Invention content
The technical problems to be solved by the invention are to provide a kind of delay phase-locked loop with broadband input range,
In, Postponement module includes a plurality of delay chain, and delay chain is automatically selected by inside so that DLL can be worked normally always, be improved
The operating frequency range of DLL.
To achieve the goals above, the present invention adopts the following technical scheme that：A kind of delay with broadband input range
Phaselocked loop, including phase detecting module, Postponement module, control module, adjustment module and selecting module, the phase detecting module
Including two input ports and phase state output port, wherein two input ports of the phase detecting module connect respectively
Reference clock and feedback clock are connect, phase state output port connects the input port of the control module；The control module
Output port connect the input port I of the selecting module, for exporting control word to the selecting module；The delay mould
The input port of block connects the reference clock, and the output port of the Postponement module connects the input port of the selecting module
II, for exporting delayed clock to the selecting module, the delay cell includes at least one delay chain；The selection mould
Clock after the output port output selection of block, two input ports of the adjustment module are separately connected counting clock and reference
The output port of clock, the adjustment module connects the Postponement module；The control module is according to the phase detecting module
Output result adjust the corresponding control word of each phase, the control word general that the selecting module export according to the control module
Corresponding delay clock is selected as corresponding structure output.
Further, A delay chain composition of the Postponement module, wherein each delay chain is by identical delay cell string
Join, the delay cell in different delays chain is different, and A is the integer more than or equal to 1.
Further, the adjustment module includes counting unit, storage unit and comparing unit, wherein the counting is single
Two input terminals of member are separately connected reference clock and counting clock, and the output port of the counting unit connects the ratio simultaneously
Compared with unit and storage unit, the output port of the storage unit connects another input port of the comparing unit, the ratio
Compared with the output port that the output port of module is the adjustment module；Wherein, in counting unit, the counting clock and to ginseng
Examine clock to be counted, preserve the last count value in counting unit in storage unit, comparing unit to current count value and
The count value stored in storage unit is compared.
Further, when the work clock of the delay phase-locked loop stablizes constant, the count value in the counting unit
Constant, count value stored in the storage unit is constant, and the adjustment module output control signal controls the delay cell
In delay chain remain unchanged.
Further, when the work clock of the delay phase-locked loop changes, the count value in the counting unit occurs
Variation, count value stored in the storage unit change, and the adjustment module output control signal controls the delay
Mould delay chain in the block changes.
Further, when the count value in the counting unit is more than the storage value of the storage unit, the adjusting
Module output control signal controls the Postponement module selection delay time longer delay chain, wherein delay time is described
The delay time of single delay cell in delay chain.
Further, when the count value in the counting unit is less than the storage value of the storage unit, the adjusting
Module output control signal controls the Postponement module selection delay time shorter delay chain, wherein delay time is described
The delay time of single delay cell in delay chain.
Further, the phase state output port exports three kinds of phase detection results, corresponds to feedback clock respectively and prolongs
Reference clock, feedback clock to be ahead of in reference clock, feedback clock synchronous with reference clock afterwards.
Further, square wave stable period that the counting clock is an externally input, and the period of the counting clock is small
In the period of reference clock.
Further, the feedback clock is 2 π phase clocks.
Beneficial effects of the present invention are：When changing in the prior art due to the working frequency of DLL, it may result in beyond control
The counting of molding block so that DLL can not work normally, and Postponement module includes multiple delay chains in the present invention, and each delay chain
It is connected in series by identical delay cell, the delay cell in different delays chain is different, automatically selects delay chain by inside, makes
Obtaining DLL can work normally always, improve the operating frequency range of DLL.
Description of the drawings
Fig. 1 is a kind of block schematic illustration of the delay phase-locked loop with broadband input range of the present invention.
Fig. 2 is the structural schematic diagram of adjustment module in the present invention.
Fig. 3 is a kind of corresponding structure chart of delay phase-locked loop with broadband input range in the embodiment of the present invention 1.
Specific implementation mode
To make the object, technical solutions and advantages of the present invention clearer, below in conjunction with the accompanying drawings to the specific reality of the present invention
The mode of applying is described in further detail.
As shown in Fig. 1, a kind of delay phase-locked loop with broadband input range provided by the invention, including phase inspection
Module, Postponement module, control module, adjustment module and selecting module are surveyed, phase detecting module includes two input ports and phase
Position state output port, wherein when two input ports of phase detecting module are separately connected reference clock CLK-REF and feedback
Clock CLK-FB, the input port of phase state output port link control module, and phase state output port export three kinds of phases
Position testing result, corresponds to feedback clock and delays and be ahead of reference clock, feedback clock and ginseng in reference clock, feedback clock respectively
Examine clock synchronization；The input port I of the output port connection selecting module of control module, for exporting at least one to selecting module
A control word；The input port of Postponement module connects reference clock, the input of the output port connection selecting module of Postponement module
Port II, for exporting delayed clock to selecting module, delay cell includes at least one delay chain；The output of selecting module
Clock after the output selection of port, two input ports of adjustment module are separately connected counting clock CLK-C and reference clock
CLK-REF, counting clock CLK-C frequencies are higher than reference clock CLK-REF, and it is externally input stable period side to adjust clock
Wave, reference clock CLK-REF are the work clock of DLL, the output port connection delay module of adjustment module；Control module according to
The output result of phase detecting module adjusts the corresponding control word of each phase, the control that selecting module is exported according to control module
Corresponding delay clock is selected as corresponding structure output by word, wherein 2 π phase clocks are feedback clock.
Wherein, A delay chain composition of Postponement module, wherein each delay chain is connected in series by identical delay cell, no
Different with the delay cell in delay chain, A is the integer more than or equal to 1.Which delay chain is final delay module be operated in by adjusting
Save the control signal deciding of module output.
Adjustment module includes counting unit, storage unit and comparing unit, wherein two input terminals of counting unit are distinguished
Reference clock and counting clock are connected, the output port of counting unit connects comparing unit and storage unit, storage unit simultaneously
Output port connection comparing unit another input port, the output port of comparison module is the output port of adjustment module；
Wherein, in counting unit, counting clock and reference clock is counted, upper one in counting unit is preserved in storage unit
Secondary count value, comparing unit are compared the count value stored in current count value and storage unit.
When delay phase-locked loop works, counting clock counts reference clock, counts terminate count value and storage every time
Last storage value in unit is compared.When the work clock of delay phase-locked loop stablizes constant, the meter in counting unit
Numerical value is constant, and the count value stored in storage unit is constant, the delay in adjustment module output control signal control delay cell
Chain remains unchanged.When the variation of the work clock of delay phase-locked loop, the count value in counting unit changes, in storage unit
The count value of storage changes, and the delay chain in adjustment module output control signal control Postponement module changes.If working as
Under preceding delay chain, delay phase-locked loop can work normally, then be not necessarily to adjust delay chain；If under current delay chain, delay phase-locked loop without
Method works normally, then comparing unit judges count results twice and exports control signal, and control signal changes in Postponement module
Delay chain, and replace last counting to deposit in a storage module current count, if this delay phase-locked loop under this delay chain still
It so can not work normally, then continue to adjust delay chain.
Specifically, the current clock count that adjusts of meter is C1, and the last time in memory is counted as C0, if C1>C0 then illustrates
The current reference clock cycle becomes larger, and reference clock frequency reduces, when then needing to increase the delay of the delay cell in delay chain
Between, adjustment module output control signal, the delay chain of selection delay bigger；If C1<C0 then illustrates that the current reference clock cycle becomes
Small, reference clock frequency increases, in the delay time for then needing the delay cell in reduction delay chain, adjustment module output control
Signal, selection postpone smaller delay chain；The above work is repeated, until DLL can be worked normally.
Embodiment 1
Fig. 3 gives an i=1 based on Fig. 1, the delay phase-locked loop structural schematic diagram of 4 phases of k=300, m=7,
The triggering edge of wherein all modules is rising edge, and m+1 indicates the digit of the corresponding binary system statements of Ci.
The final clock of delay phase-locked loop locking is CLK_OUT, and the corresponding control word of this clock is followed successively by C [7:0],
CLK_OUT is feedback clock CLK_FB.
The input and output of wherein selecting module remain following relationship：
CLK_OUT_OUT=CLK_D [a], a=C [7:0]；And a ∈ [0,300].
Wherein, CLK_C is counting clock, and CLK_REF is reference clock, and the period of CLK_C is denoted as Tc, the week of CLK_REF
Phase is denoted as Tr, and clock meets Tc<Tr. the counting preserved in memory module is denoted as C0, and current count is denoted as C1.
In delay phase-locked loop normal work and constant CLK_REF frequencies, C0=C1, Postponement module keeps work at present to prolong
Slow chain works on；
When CLK_REF changes, then C0 ≠ C1, phase detecting module, selecting module and the control module weight of delay phase-locked loop
It is new to adjust.
If delay phase-locked loop can work normally in the control range of control module, delay phase-locked loop, which continues to operate in, works as
Preceding delay chain, and the value of C0 is changed to C1, continue to preserve；
If delay phase-locked loop can not work normally in the control range of control module, need to change delay chain.
Comparing unit in adjustment module is started to work, and comparing unit compares the size of C0 and C1.
If C1>C0 then illustrates the reference clock cycle before the current reference clock cycle of delay phase-locked loop is more than, then needs
Delay is increased, comparing unit output comparison result, the delay chain of Postponement module selection delay bigger, phase detecting module,
Selecting module and control module readjust and C0 at this time are changed to C1；
If C1<C0 then illustrates the reference clock cycle before the current reference clock cycle of delay phase-locked loop is less than, then needs
Delay is reduced, comparison module exports comparison result, phase detecting module, selecting module and control module selection delay smaller
Delay chain, phase detecting module, selecting module and control module readjust and C0 at this time are changed to C1；
Above step is repeated, until delay phase-locked loop energy steady operation.
The foregoing is merely the preferred embodiment of the present invention, the embodiment is not intended to limit the patent protection of the present invention
Range, therefore equivalent structure variation made by every specification and accompanying drawing content with the present invention, similarly should be included in this
In the protection domain of invention appended claims.
Claims (10)
1. a kind of delay phase-locked loop with broadband input range, which is characterized in that including phase detecting module, delay mould
Block, control module, adjustment module and selecting module, the phase detecting module include that two input ports and phase state export
Port, wherein two input ports of the phase detecting module are separately connected reference clock and feedback clock, and phase state is defeated
Exit port connects the input port of the control module；The output port of the control module connects the input of the selecting module
Port I, for exporting control word to the selecting module；The input port of the Postponement module connects the reference clock, institute
The output port for stating Postponement module connects the input port II of the selecting module, when postponing for being exported to the selecting module
Clock, the delay cell include at least one delay chain；Clock after the output port output selection of the selecting module, institute
Two input ports for stating adjustment module are separately connected counting clock and reference clock, the output port connection of the adjustment module
The Postponement module；The control module adjusts the corresponding control of each phase according to the output result of the phase detecting module
Word, it is defeated that corresponding delay clock is selected as corresponding structure by the control word that the selecting module is exported according to the control module
Go out.
2. a kind of delay phase-locked loop with broadband input range according to claim 1, which is characterized in that described to prolong
Slow modules A delay chain composition, wherein each delay chain is connected in series by identical delay cell, prolonging in different delays chain
Slow unit is different, and A is the integer more than or equal to 1.
3. a kind of delay phase-locked loop with broadband input range according to claim 1, which is characterized in that the tune
It includes counting unit, storage unit and comparing unit to save module, wherein two input terminals of the counting unit are separately connected ginseng
Clock and counting clock are examined, the output port of the counting unit connects the comparing unit and storage unit simultaneously, described to deposit
The output port of storage unit connects another input port of the comparing unit, and the output port of the comparison module is the tune
Save the output port of module；Wherein, in counting unit, the counting clock and reference clock is counted, storage unit
Last count value in middle preservation counting unit, comparing unit to the count value that is stored in current count value and storage unit into
Row compares.
4. a kind of delay phase-locked loop with broadband input range according to claim 3, which is characterized in that when described
When the work clock of delay phase-locked loop stablizes constant, the count value in the counting unit is constant, is stored in the storage unit
Count value it is constant, the delay chain that adjustment module output control signal controls in the delay cell remains unchanged.
5. a kind of delay phase-locked loop with broadband input range according to claim 3, which is characterized in that when described
When the work clock variation of delay phase-locked loop, the count value in the counting unit changes, and is stored in the storage unit
Count value change, the delay chain that adjustment module output control signal controls in the Postponement module changes.
6. a kind of delay phase-locked loop with broadband input range according to claim 5, which is characterized in that when described
When count value in counting unit is more than the storage value of the storage unit, described in the adjustment module output control signal control
Postponement module selects delay time longer delay chain, wherein delay time is that single delay cell is prolonged in the delay chain
The slow time.
7. a kind of delay phase-locked loop with broadband input range according to claim 5, which is characterized in that when described
When count value in counting unit is less than the storage value of the storage unit, described in the adjustment module output control signal control
Postponement module selects delay time shorter delay chain, wherein delay time is that single delay cell is prolonged in the delay chain
The slow time.
8. a kind of delay phase-locked loop with broadband input range according to claim 1, which is characterized in that the phase
Position state output port exports three kinds of phase detection results, correspond to feedback clock respectively and delays and surpasses in reference clock, feedback clock
It is preceding synchronous with reference clock in reference clock, feedback clock.
9. a kind of delay phase-locked loop with broadband input range according to claim 1, which is characterized in that the meter
Square wave stable period that number clock is an externally input, and the period of the counting clock is less than the period of reference clock.
10. a kind of delay phase-locked loop with broadband input range according to claim 1, which is characterized in that described
Feedback clock is 2 π phase clocks.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201810230894.1A CN108566195A (en) | 2018-03-20 | 2018-03-20 | A kind of delay phase-locked loop with broadband input range |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201810230894.1A CN108566195A (en) | 2018-03-20 | 2018-03-20 | A kind of delay phase-locked loop with broadband input range |
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| CN201810230894.1A Withdrawn CN108566195A (en) | 2018-03-20 | 2018-03-20 | A kind of delay phase-locked loop with broadband input range |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110581709A (en) * | 2019-08-30 | 2019-12-17 | 浙江大学 | Zero-delay phase-locked loop frequency synthesizer based on multistage synchronization |
| CN111342653A (en) * | 2020-03-24 | 2020-06-26 | 华中科技大学 | Six-phase parallel connection staggered full-integrated buck circuit |
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| CN111342653A (en) * | 2020-03-24 | 2020-06-26 | 华中科技大学 | Six-phase parallel connection staggered full-integrated buck circuit |
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