CN108768387B - Quick-locking delay locking ring - Google Patents
Quick-locking delay locking ring Download PDFInfo
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- CN108768387B CN108768387B CN201711373492.9A CN201711373492A CN108768387B CN 108768387 B CN108768387 B CN 108768387B CN 201711373492 A CN201711373492 A CN 201711373492A CN 108768387 B CN108768387 B CN 108768387B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
- H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
- H03L7/0814—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the phase shifting device being digitally controlled
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
Abstract
The invention discloses a quick-locking delay locking ring, which comprises a phase detection module, a counting module, a delay module, a control module and a selection module, wherein the phase detection module is provided with 2 input ports, a phase state output port and a phase mark output port; the input port of the counting module is connected with the counting clock, and the output port of the counting module is connected with the input port of the control module; the output port of the control module is connected with the input port of the selection module; the input port of the delay module is connected with the reference clock, the output port of the delay module is connected with the input port II of the selection module, and the output port of the selection module outputs a feedback clock signal. The invention has simple structure and greatly improves the working efficiency of the delay locking ring.
Description
Technical Field
The invention relates to the field of CMOS integrated circuit design, in particular to a quick-locking delay locking ring.
Background
With the development of CMOS integrated circuit technology, clock circuits play a very important role in both digital and analog integrated circuit design. However, pll (phase Locked loop) is basically designed by using analog circuits, which causes a problem of circuit noise, and is difficult to design and poor in reusability. The DLL (delay Locked loop), especially the full digital DLL circuit, has better circuit noise performance due to the completion of the DLL circuit based on digital logic, and the circuit has strong reusability and is more and more widely applied.
Also, in some circuit designs, not only are strict requirements placed on clock frequency, but also phase of the clock is of great concern. For example, in TDC, the clock with equal phase difference is an important part of making the time measurement; in SDRAM, the phases of the input clock and the output clock are required to be strictly equal. The role of the DLL is becoming more prominent in areas where phase requirements are imposed. The existing DLL circuit generally adopts a one-by-one adjustment mode and a successive approximation control mode; if the circuit is adjusted one by one, the locking time is long, and the design difficulty is relatively high by adopting a successive approximation control mode.
Disclosure of Invention
The invention aims to solve the technical problem of providing a quick-locking delay locking ring, which can quickly and accurately realize delay locking through the counting value of a counting module, has a simple structure and greatly improves the working efficiency of the delay locking ring.
In order to achieve the purpose, the invention adopts the following technical scheme: a fast-locking delay lock loop comprises a phase detection module, a counting module, a delay module, a control module and a selection module, wherein the phase detection module is provided with 2 input ports, a phase state output port and a phase mark output port; an input port II of the counting module is connected with a counting clock, and an output port of the counting module is connected with an input port II of the control module; the output port of the control module is connected with the input port I of the selection module; the input port of the delay module is connected with a reference clock, the output port of the delay module is connected with the input port II of the selection module, the reference clock is changed into a delay clock through the delay module, and the delay clock is output through the output port of the selection module.
Furthermore, the delay module includes k identical delay units, where k is an integer greater than or equal to T/Td, T is a period of the reference clock, and Td is a delay time of each delay unit.
Furthermore, the number of the phase mark output ports in the phase detection module is two, and the two phase mark output ports respectively output mark signals of the reference clock and the feedback clock in the same phase.
Further, the counting value D of the counting module is equal to the ratio of the time difference of the occurrence of the flag signals of the reference clock and the feedback clock respectively at the same phase to the period of the counting clock.
Furthermore, the phase state output port of the phase detection module outputs three phase detection results, which correspond to the feedback clock delaying the reference clock, the feedback clock advancing the reference clock, and the feedback clock synchronizing with the reference clock.
Furthermore, the output port of the control module outputs i control bits Ci, and Cj is j Ci/i, and Ci corresponds to the number of delay units through which the delay signal CLK-OUT [ i ] output by the selection module in the same reference clock cycle passes, where i is an integer less than or equal to k, and j is an integer greater than or equal to 1 and less than or equal to i.
Further, the control module judges whether to change the current control bit according to the output result of the phase detection state output port, wherein if the feedback clock is synchronous with the reference clock, the current control bit is kept unchanged; the control module changes the control bit if the feedback clock and the reference clock are not synchronized.
Further, if the feedback clock is delayed from the reference clock, the control bits are decreased, and the new control bit Ci is Ci-D Tc/Td; and if the reference clock is delayed from the feedback clock, increasing the control bit, wherein the new control bit Ci is Ci + D Tc/Td, Tc is the period of the counting clock, Td is the delay time of each delay unit in the delay module, and D is the counting value of the counting module.
Further, the selection module selects the delay signal with the largest number of delay units from the delay signals input by the delay module as the feedback signal.
Further, the count clock frequency is higher than the frequency of the reference clock.
The invention has the beneficial effects that: the current general DLL realizes phase alignment by adjusting the delay number in a sequential change or successive approximation mode, and the phase alignment can be completed and the locking can be completed only by changing the control bit of the control module for multiple times in multiple clock cycles.
Drawings
FIG. 1 is a schematic diagram of a frame of a quick lock delay locked loop according to the present invention.
Fig. 2 is a corresponding structural diagram of the delay locked loop of the fast locking in embodiment 1.
Fig. 3 is a timing chart corresponding to the delayed lock loop of the fast lock in embodiment 1.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, embodiments of the present invention are described in detail below with reference to the accompanying drawings.
As shown in fig. 1, the fast-locking delay locked loop provided by the present invention includes a phase detection module PD, a COUNTER module COUNTER, a delay module VCDL, a control module CTRL and a selection module MUX, where the phase detection module PD has 2 input ports, a phase state output port and a phase flag output port, two input ports of the phase detection module are respectively connected to a reference clock CLK-REF and a feedback clock CLK-FB, the phase state output port is connected to an input port i of the control module, and the phase flag output port is connected to an input port i of the COUNTER module COUNTER; an input port II of the counting module COUNTER is connected with a counting clock CLK-S, and an output port of the counting module COUNTER is connected with an input port II of the control module CTRL; the output port of the control module CTRL is connected with the input port I of the selection module; the input port of the delay module VCDL is connected with the reference clock CLK-REF, the output port of the delay module VCDL is connected with the input port II of the selection module MUX, and the output port of the selection module MUX outputs the feedback clock signal CLK-FB.
One input port of two input ports in the phase detection module PD is connected with a reference clock, wherein the parametric clock is a periodic square wave signal with standard stable frequency input from the outside, and one input port is connected with a feedback clock; the phase state output port outputs three phase detection results, wherein the three phase detection results are respectively that the corresponding feedback clock delays behind the reference clock, the feedback clock leads ahead of the reference clock, and the feedback clock is synchronous with the reference clock; the two phase mark output ports respectively output mark signals of the reference clock and the feedback clock in the same phase and are used for determining a counting value D in the counting module, wherein the counting value D is equal to the ratio of the time difference of the mark signals appearing successively in the same phase of the reference clock and the feedback clock to the period of the counting clock.
The input port ii of the COUNTER module COUNTER is connected to a counting clock, wherein the frequency of the counting clock is higher than the input reference clock. The start and end of counting by the counting clock are determined by two counting control signals, i.e. by the flag signals of the reference clock and the feedback clock at the same phase. Because the two counting control signals are mark signals of the reference clock and the feedback clock in the same phase, the counting value of the counting module is represented as D, so that the delay between the reference clock and the feedback clock, namely the phase difference between the reference clock and the feedback clock can be obtained through the counting of the counting clock D. Assuming that the period of the counting clock is Tc, the delay of the reference clock and the feedback clock corresponding to D is D × Tc, where we usually use D [ n:0] to represent the binary representation corresponding to D.
The delay module is composed of A identical delay units, the reference clock is input into the delay module, the frequency of signals passing through the delay units is identical to that of the reference clock, but the signal delays passing through different numbers of delay units are different, namely the signal phases are different, and A is an integer greater than or equal to 1.
Assuming that the delay time of each delay unit is Td, the reference clock passes through a delay units, the delay time is a Td, and assuming that the period of the reference clock is T, the phase of the delay is aTd/T · 2 pi.
Let a be Td and T obtain a be T/Td, that is, the clock signal output by the delay units passing through T/Td is equal in phase to the input reference clock, i.e. both are completely synchronized. The number of delay cells actually designed must be greater than T/Td in consideration of process variation.
The input port I of the control module is connected with three phase detection state results, the input port II of the control module inputs the counting result of the counter in the counting module, and the control module outputs control bits which correspond to the number of delay units in the delay module one by one. The control module judges whether to change the current control bit according to the phase detection state result.
If the feedback clock is synchronous with the reference clock, the current control bit is kept unchanged; if the feedback clock and the reference clock are not synchronized, the control module outputs a new control bit. Since the DLL may need to output multiple phases, the control module may need to output multiple control bits, denoted as the ith control bit by Ci in the present invention.
Assuming that the equal phase difference clock signal is i bits, the signal control bit with the maximum phase is Ci, if the feedback clock is delayed from the reference clock, the control bit is reduced, and the new control bit Ci is Ci-D Tc/Td; if the feedback clock is delayed from the reference clock, the control bits are incremented, and the new control bit Ci is Ci + D Tc/Td. From small to large, the control bit Cj ═ j × Ci/i (j ═ 1,2, …, i) of the j-th bit clock in the equal phase difference clock is usually represented by Ci [ m:0] to represent the binary representation corresponding to Ci.
And the selection module selects the delay signal with the most delay from the delay limit signals output by the delay module as the feedback clock signal to output according to the control bit output by the control module.
The counting module in the invention can be triggered by a rising edge or a falling edge.
The invention is further illustrated by the following specific examples:
example 1:
referring to fig. 2, in this embodiment, a control module outputs four control bits, and fig. 3 is a schematic diagram of a working timing diagram of the feedback clock delayed from the reference clock in fig. 2. Wherein the triggering edges of all modules are rising edges. The clocks with the delay time from large to small are CLK _ OUT [4], CLK _ OUT [3], CLK _ OUT [2] and CLK _ OUT [1] in sequence, and CLK _ OUT [4] is the feedback clock CLK _ FB.
The phase detection results are sequentially recorded as UP, DN and LOCK, UP indicates that CLK _ FB leads CLK _ REF, DN indicates that CLK _ FB lags CLK _ REF, LOCK indicates that CLK _ FB and CLK _ REF are synchronous, the phase mark signals are respectively recorded as start and stop, wherein start is a mark signal which appears first in a same phase corresponding to CLK _ FB and CLK _ REF, and stop is a mark signal which appears later in a corresponding same phase. The initial signals of UP, DN, LOCK, start, and stop are all 0.
The control module outputs 4 control bits C1, C2, C3 and C4, where C1 corresponds to the number of delay cells through which CLK _ OUT [1] passes, C2 corresponds to the number of delay cells through which CLK _ OUT [2] passes, C3 corresponds to the number of delay cells through which CLK _ OUT [3] passes, C4 corresponds to the number of delay cells through which CLK _ OUT [4] passes, and Cj equals j equal to C4/4(j equals 1,2, 3, 4). In this embodiment, Ci [ m:0] is used to represent the binary representation corresponding to Ci, and m +1 represents the number of bits of the binary representation corresponding to Ci. Assuming that the initial value of C4[7:0] is 10000000, it is known from Cj [7:0] ═ j × C4[7:0]/4 that: the initial value of C3[7:0] is 01100000, the initial value of C2[7:0] is 01000000, and the initial value of C1[7:0] is 00100000.
Since all the triggers are triggered by rising edges and the feedback clock CLK _ FB lags the reference clock CLK _ REF, the phase flag signal start changes from an initial value of 0 to 1 when the rising edge of CLK _ REF arrives and the phase flag signal stop changes from an initial value of 0 to 1 when the rising edge of CLK _ FB arrives. Since CLK _ FB comes before CLK _ REF, the transition at start occurs before stop. When the time of the start signal transition is t1 and the time of the stop signal transition is t2, the time period between t1 and t2 counts the time period of the clock CLK _ S, i.e., CLK _ S starts counting from time t1, the time t2 ends counting, and the counting result is D.
In the phase detection module, if CLK _ FB leads CLK _ REF, UP is changed from 0 to 1 when the rising edge of CLK _ REF comes; if CLK _ FB delays at CLK _ REF, then DN changes from 0 to 1 when the rising edge of CLK _ FB arrives; if CLK _ FB and CLK _ REF are synchronized, both rising edges occur simultaneously, and LOCK changes from 0 to 1 at the occurrence of the rising edge. Corresponding to fig. 2, since CLK _ FB lags behind CLK _ REF, UP is always 0, DN changes from initial value 0 to 1 at time t2, which is the arrival of the rising edge of CLK _ FB, and LOCK is always 0 until t 2.
Since DN is 1, UP is 0, and LOCK is 0, the control module output C4 is reduced by D. In this embodiment, D [ n:0] is used to represent the binary representation corresponding to D, and n +1 represents the number of bits of the binary representation corresponding to D, it should be noted that, in the count value D [ n:0] and the control bit Ci [ m:0], n is less than or equal to m, but since the binary system can be complemented before the highest bit to facilitate calculation, for example, we assume that D [7:0] ═ 00010000, and at this time, m ═ n; the virtually identical count value D can also be expressed as D [6:0] ═ 0010000, D [5:0] ═ 010000, D [4:0] ═ 10000, in which case n < m; the above-described counting manners all indicate the same count value D. For convenience of calculation, assuming that D [7:0] ═ 00010000, eventually C4[7:0] ═ 01110000, C3[7:0] ═ 01011100, C2[7:0] ═ 00111000, and C1[7:0] ═ 00011100.
The above description is only a preferred embodiment of the present invention, and the embodiment is not intended to limit the scope of the present invention, so that all equivalent structural changes made by using the contents of the specification and the drawings of the present invention should be included in the scope of the appended claims.
Claims (5)
1. A fast-locking delay lock loop is characterized by comprising a phase detection module, a counting module, a delay module, a control module and a selection module, wherein the phase detection module is provided with 2 input ports, a phase state output port and a phase mark output port; an input port II of the counting module is connected with a counting clock, and an output port of the counting module is connected with an input port II of the control module; the output port of the control module is connected with the input port I of the selection module; the input port of the delay module is connected with a reference clock, the output port of the delay module is connected with the input port II of the selection module, a reference signal sent by the reference clock is changed into a delay signal through the delay module, and the delay signal is output through the output port of the selection module; the delay module comprises k identical delay units, wherein k is an integer greater than or equal to T/Td, T is the period of a reference clock, and Td is the delay time of each delay unit; the selection module selects the delay signal with the largest number of delay units from the delay signals input by the delay module as a feedback signal; the frequency of the counting clock is higher than that of the reference clock; the phase detection module comprises two phase mark output ports, and the two phase mark output ports respectively output mark signals of a reference clock and a feedback clock in the same phase; and the counting value D of the counting module is equal to the ratio of the time difference of the occurrence of the mark signals of the reference clock and the feedback clock respectively under the same phase to the period of the counting clock.
2. The fast lock delay locked loop of claim 1 wherein the phase status output port of the phase detect module outputs three phase detect results corresponding to the feedback clock being delayed from the reference clock, the feedback clock being advanced from the reference clock, and the feedback clock being synchronized with the reference clock.
3. The fast-locking delay locked loop of claim 2, wherein the output port of the control module outputs i control bits Ci, and Cj j Ci/i, and Ci corresponds to the number of delay cells through which the delay signal CLK-OUT [ i ] output by the selection module in the same reference clock cycle passes, where i is an integer less than or equal to k, and j is an integer greater than or equal to 1 and less than or equal to i.
4. A fast locking delay locked loop as claimed in claim 3, wherein the control module determines whether to change the current control bit according to the output result of the phase detection state output port, wherein the current control bit remains unchanged if the feedback clock and the reference clock are synchronized; the control module changes the control bit if the feedback clock and the reference clock are not synchronized.
5. A fast locking delay locked loop as claimed in claim 4, wherein if the feedback clock is delayed from the reference clock, the control bits are decremented, new control bits Ci-D Tc/Td; and if the reference clock is delayed from the feedback clock, increasing the control bit, wherein the new control bit Ci is Ci + D Tc/Td, Tc is the period of the counting clock, Td is the delay time of each delay unit in the delay module, and D is the counting value of the counting module.
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| CN110611950B (en) * | 2019-09-19 | 2021-08-10 | Ut斯达康通讯有限公司 | Phase synchronization method, device and terminal |
| CN110750048B (en) * | 2019-12-04 | 2021-10-26 | 电子科技大学 | DLL system based on successive approximation type PID control algorithm |
| CN111490778A (en) * | 2020-04-03 | 2020-08-04 | 四川知微传感技术有限公司 | Delay phase-locked loop based on PD control and control method thereof |
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| US6509801B1 (en) * | 2001-06-29 | 2003-01-21 | Sierra Monolithics, Inc. | Multi-gigabit-per-sec clock recovery apparatus and method for optical communications |
| US9245605B2 (en) * | 2013-04-17 | 2016-01-26 | Samsung Electronics Co., Ltd. | Clock synchronization circuit and semiconductor memory device including clock synchronization circuit |
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| CN101060328A (en) * | 2006-11-22 | 2007-10-24 | 威盛电子股份有限公司 | Delay device and its method |
| CN101764608A (en) * | 2008-12-25 | 2010-06-30 | 北京芯技佳易微电子科技有限公司 | Bit-by-bit approaching delay phase-locked loop circuit and method for regulating input clock signal |
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