CN108521277B - Delay-locked loop capable of automatically adjusting precision and adjusting method thereof - Google Patents
Delay-locked loop capable of automatically adjusting precision and adjusting method thereof Download PDFInfo
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- CN108521277B CN108521277B CN201810230905.6A CN201810230905A CN108521277B CN 108521277 B CN108521277 B CN 108521277B CN 201810230905 A CN201810230905 A CN 201810230905A CN 108521277 B CN108521277 B CN 108521277B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
- H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
Abstract
The invention discloses a delay phase-locked loop capable of automatically adjusting precision, which comprises a phase detection module, a delay module, a control module and a selection module, wherein the phase detection module is used for detecting the phase of a phase signal; 2 input ports of the phase detection module are respectively connected with a reference clock and a feedback clock, and a phase state output port is connected with an input port of the control module; the output port of the control module is connected with the input port I of the selection module; the input port of the delay module is connected with the reference clock, and the output port of the delay module is connected with the input port II of the selection module; the output port of the selection module outputs the selected clock; the phase detection module comprises a phase detection unit, a storage unit, a judgment unit and a phase control unit. According to the delay locked loop capable of automatically adjusting the precision, the precision of the phase detection module is repeatedly adjusted for multiple times, so that the DLL works under the condition of minimum precision, and the working reliability of the DLL is ensured.
Description
Technical Field
The invention relates to the field of integrated circuits, in particular to a delay-locked loop capable of automatically adjusting precision and an adjusting method thereof.
Background
With the development of CMOS integrated circuit technology, clock circuits play a very important role in both digital and analog integrated circuit design. However, pll (phase Locked loop) is basically designed by using analog circuits, which causes a problem of circuit noise, and is difficult to design and poor in reusability. The DLL (delay Locked loop), especially the full digital DLL circuit, has better circuit noise performance due to the completion of the DLL circuit based on digital logic, and the circuit has strong reusability and is more and more widely applied.
Also, in some circuit designs, not only are strict requirements placed on clock frequency, but also phase of the clock is of great concern. For example, in TDC, the clock with equal phase difference is an important part of making the time measurement; in SDRAM, the phases of the input clock and the output clock are required to be strictly equal. The role of the DLL is becoming more prominent in areas where phase requirements are imposed. The precision of the phase detection module of the DLL is determined by the precision requirements of the delay unit of the DLL and the whole DLL, and the delay unit of the DLL and the whole DLL are difficult to be matched normally, so that the DLL cannot work.
Disclosure of Invention
The technical problem to be solved by the invention is to provide a delay locked loop capable of automatically adjusting the precision, and the DLL works under the condition of minimum precision and ensures the working reliability of the DLL by repeatedly adjusting the precision of a phase detection module for many times.
In order to achieve the purpose, the invention adopts the following technical scheme: a delay phase-locked loop capable of automatically adjusting precision comprises a phase detection module, a delay module, a control module and a selection module; the phase detection module comprises 2 input ports and a phase state output port, wherein the 2 input ports of the phase detection module are respectively connected with a reference clock and a feedback clock, and the phase state output port is connected with the input port of the control module; the output port of the control module is connected with the input port I of the selection module and used for outputting control words to the selection module; the input port of the delay module is connected with the reference clock, and the output port of the delay module is connected with the input port II of the selection module and used for outputting the delay clock to the selection module; the output port of the selection module outputs the selected clock; the phase detection module comprises a phase detection unit, a storage unit, a judgment unit and a phase control unit, wherein the phase detection unit is used for comparing the phase states of a feedback clock and a reference clock, the storage unit is used for storing the detection result of the last phase detection, the judgment unit compares the last phase detection result with the current phase detection result to obtain the adjustment direction of the phase detection unit, and the phase control unit adjusts the detection precision of the phase detection unit according to the output result of the judgment unit.
Furthermore, the phase detection unit includes two input ends and an output end, the two input ends of the phase detection unit are respectively connected to the reference clock and the feedback clock, an output port of the phase detection unit is used for outputting a phase detection result, the output port is respectively connected to the storage unit and the judgment unit, the judgment unit is simultaneously connected to the storage unit and the phase control unit, and the phase control unit is connected to the phase detection unit and is used for controlling and adjusting the detection precision of the phase detection unit.
Furthermore, the phase state output port outputs three phase detection results, which correspond to the feedback clock delaying the reference clock, the feedback clock advancing the reference clock, and the feedback clock synchronizing with the reference clock.
Further, the reference clock is a periodic square wave signal with a standard stable frequency and input externally.
Further, the feedback clock is a2 pi phase clock.
Further, the output port of the control module outputs i control words Cj, and Cj is j Ci/i, and Cj corresponds to the delay clocks output by the delay module one by one, where i is an integer greater than 1, and j is an integer greater than or equal to 1 and less than or equal to i.
The invention provides a method for adjusting the precision of a delay locked loop, which comprises the following steps:
s01: adjusting the precision of the phase detection unit to a maximum value;
s02: the delay phase-locked loop works under the maximum precision of the phase detection unit until the delay phase-locked loop is stable, at the moment, the control module does not change any more, the phase detection unit detects that the feedback clock and the reference clock are in the same phase, and the phase detection result at the moment is stored in the storage unit;
s03, reducing the precision of the phase detection unit;
s04: the delay phase-locked loop works until the delay phase-locked loop is stable, the control module does not change any more, and if the phase detection unit detects that the feedback clock and the reference clock are in the same phase at the moment, the steps S03-S04 are repeated; if the phase detection unit detects that the feedback clock and the reference clock are unlocked, the accuracy of the phase detection module is judged to exceed the minimum operable accuracy, and the accuracy of the phase detection unit is adjusted to the previous accuracy and is kept unchanged.
Furthermore, the delay module includes N identical delay units, and the precision adjustment of the phase detection unit can be performed by changing the number of the delay units or adjusting the supply voltage of the delay units, where N is an integer greater than or equal to 1.
The invention provides another method for adjusting the precision of a delay locked loop, which comprises the following steps:
t01: adjusting the precision of the phase detection unit to a minimum value;
t02: the delay phase-locked loop works under the minimum precision of the phase detection unit until the delay phase-locked loop is stable, at the moment, the control module does not change any more, the phase detection unit detects that the feedback clock and the reference clock are unlocked, and the phase detection result at the moment is stored in the storage unit;
t03 increasing the accuracy of the phase detection unit;
t04: the delay phase-locked loop works until the delay phase-locked loop is stable, the control module does not change any more, and if the phase detection unit detects that the feedback clock and the reference clock are unlocked at the moment, the steps T03-T04 are repeated; if the phase detection unit detects that the feedback clock and the reference clock are in the same phase at the moment, the precision of the phase detection module at the moment is judged to be the minimum precision with which the phase detection module can work, and the precision is kept unchanged.
Furthermore, the delay module includes N identical delay units, and the precision adjustment of the phase detection unit can be performed by changing the number of the delay units or adjusting the supply voltage of the delay units, where N is an integer greater than or equal to 1.
The invention has the beneficial effects that: the invention improves the phase detection module, and provides a novel DLL structure with high reliability and automatic adjustment; the phase detection unit in the phase detection module is used for comparing the phase states of the feedback clock and the reference clock, the storage unit is used for storing the detection result of the last phase detection, the judgment unit compares the last phase detection result with the current phase detection result to obtain the adjustment direction of the phase detection unit, and the phase control unit adjusts the detection precision of the phase detection unit according to the output result of the judgment unit. The precision adjusting method provided by the invention ensures that the DLL works under the condition of minimum precision and ensures the working reliability of the DLL by repeatedly adjusting the precision of the phase detection module for many times.
Drawings
Fig. 1 is a schematic diagram of a dll with automatic precision adjustment according to the present invention.
Fig. 2 is a schematic structural diagram of a phase detection module according to the present invention.
Fig. 3 is a structural diagram corresponding to a delay locked loop for automatically adjusting precision in embodiment 1 of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, embodiments of the present invention are described in detail below with reference to the accompanying drawings.
As shown in fig. 1, the delay locked loop capable of automatically adjusting the precision provided by the present invention includes a phase detection module, a delay module, a control module and a selection module; the phase detection module comprises 2 input ports and a phase state output port, wherein the 2 input ports of the phase detection module are respectively connected with a reference clock CLK-REF and a feedback clock CLK-FB, and the phase state output port is connected with the input port of the control module; the output port of the control module is connected with the input port I of the selection module and used for outputting the control word to the selection module. The input port of the delay module is connected with the reference clock, and the output port of the delay module is connected with the input port II of the selection module and used for outputting the delay clock to the selection module; the output port of the selection module outputs the selected clock, and the reference clock is a periodic square wave signal with standard stable frequency input from the outside.
The phase state output port in the phase detection module outputs three phase detection results, corresponding to a feedback clock delayed from a reference clock, a feedback clock advanced from the reference clock, and a feedback clock synchronized with the reference clock, the control module adjusts control words corresponding to each phase according to the output result of the phase detection module, and the selection module selects the corresponding delay clock as the result of the corresponding phase to output according to the control words output by the control module, wherein the 2 pi phase clock is the feedback clock.
The delay module comprises N identical delay units, wherein N is an integer greater than or equal to 1. The output port of the control module outputs i control words Cj, wherein Cj is j Ci/i, and Cj corresponds to the delay clocks output by the delay module one by one, wherein i is an integer larger than 1, and j is an integer larger than or equal to 1 and smaller than or equal to i.
As shown in fig. 2, the phase detection module of the present invention includes a phase detection unit, a storage unit, a determination unit and a phase control unit; the phase detection unit comprises two input ends and an output end, the two input ends of the phase detection unit are respectively connected with the reference clock and the feedback clock, an output port of the phase detection unit is used for outputting a phase detection result, the output port is respectively connected with the storage unit and the judgment unit, the judgment unit is simultaneously connected with the storage unit and the phase control unit, and the phase control unit is connected with the phase detection unit and used for controlling and adjusting the detection precision of the phase detection unit. The phase detection unit is used for comparing the phase states of the feedback clock and the reference clock, the storage unit is used for storing the detection result of the last phase detection, the judgment unit is used for comparing the phase detection result of the last time with the current phase detection result to obtain the adjustment direction of the phase detection unit, and the phase control unit is used for adjusting the detection precision of the phase detection unit according to the output result of the judgment unit.
The invention provides a method for adjusting precision, which comprises the following steps:
s01: adjusting the precision of the phase detection unit to a maximum value;
s02: the delay phase-locked loop works under the maximum precision of the phase detection unit until the delay phase-locked loop is stable, at the moment, the control module does not change any more, the phase detection unit detects that the feedback clock and the reference clock are in the same phase, and the phase detection result at the moment is stored in the storage unit;
s03: reducing the accuracy of the phase detection unit;
s04: the delay phase-locked loop works until the delay phase-locked loop is stable, the control module does not change any more, and if the phase detection unit detects that the feedback clock and the reference clock are in the same phase at the moment, the steps S03-S04 are repeated; if the phase detection unit detects that the feedback clock and the reference clock are unlocked, the accuracy of the phase detection module is judged to exceed the minimum operable accuracy, and the accuracy of the phase detection unit is adjusted to the previous accuracy and is kept unchanged.
The invention provides another method for adjusting the precision, which comprises the following steps:
t01: adjusting the precision of the phase detection unit to a minimum value;
t02: the delay phase-locked loop works under the minimum precision of the phase detection unit until the delay phase-locked loop is stable, at the moment, the control module does not change any more, the phase detection unit detects that the feedback clock and the reference clock are unlocked, and the phase detection result at the moment is stored in the storage unit;
t03 increasing the accuracy of the phase detection unit;
t04: the delay phase-locked loop works until the delay phase-locked loop is stable, the control module does not change any more, and if the phase detection unit detects that the feedback clock and the reference clock are unlocked at the moment, the steps T03-T04 are repeated; if the phase detection unit detects that the feedback clock and the reference clock are in the same phase at the moment, the precision of the phase detection module at the moment is judged to be the minimum precision with which the phase detection module can work, and the precision is kept unchanged.
It should be noted that the accuracy of the phase detection unit in the present invention can be adjusted by changing the number of delay units or adjusting the supply voltage of the delay units. And the phase control unit in the phase detection module can adjust the precision of the phase detection unit through successive approximation or sequential increase.
The invention is further illustrated by the following specific examples:
example 1:
as shown in fig. 2, in this embodiment, we take the control module to output four control words, in this embodiment, we use Ci [ m:0] to represent the binary representation corresponding to Ci, and m +1 to represent the number of bits of the binary representation corresponding to Ci, and when i-4, this embodiment takes m ═ 7. The corresponding clocks with delay time from large to small are CLK _ OUT [4], CLK _ OUT [3], CLK _ OUT [2] and CLK _ OUT [1], the control words corresponding to the 4 clocks are C4[7:0], C3[7:0], C2[7:0] and C1[7:0] in sequence, and CLK [4] is the feedback clock CLK _ FB.
Wherein C4[7:0], C3[7:0], C2[7:0] and C1[7:0] maintain the following relationships throughout:
C1[7:0]＝C4[7:0]/4；
C2[7:0]＝(2*C4[7:0])/4；
C2[7:0]＝(3*C4[7:0])/4。
the input and the output of the selection module always keep the following relation:
CLK_OUT[4]＝CLK_D[a4]；
CLK_OUT[3]＝CLK_D[a3]；
CLK_OUT[2]＝CLK_D[a2]；
CLK_OUT[1]＝CLK_D[a1]；
wherein a4, a3, a2, and a1 consistently satisfy the following relationships:
a1＝C1[7:0]；
a2＝C2[7:0]；
a3＝C3[7:0]；
a4＝C4[7:0]；
and a4, a3, a2 and a1 all satisfy a4, a3, a2 and a1 epsilon [0,300].
Referring to fig. 3, the structure of the phase detection module in this embodiment only stores the last detected latch state 0, and only judges the latch state for 2 times. The phase detection result of the phase detection unit is UP, DN and LOCK in sequence, wherein UP indicates that the feedback clock CLK _ FB lags behind the reference clock CLK _ REF, DN indicates that the feedback clock CLK _ FB leads the reference clock CLK _ REF, and LOCK indicates that the feedback clock CLK _ FB and the reference clock CLK _ REF are in the same phase. When the DLL works, one of UP, DN and LOCK is 1, and the other two are 0.
The specific steps of the precision adjustment in this embodiment are as follows:
s01: the accuracy of the phase detection unit is set to the maximum accuracy:
s02: the phase detection module must LOCK, that is, the feedback clock CLK _ FB and the reference clock CLK _ REF must detect the same phase, that is, the initial LOCK is 1, and then LOCK0 is 1.
S03: the judgment unit outputs a default value of 1 and an increment value of 0. The phase control unit reduces the precision of the phase detection unit according to the output result of the judgment unit, and judges the phase relation between the feedback clock CLK _ FB and the reference clock CLK _ REF again.
S04: if the result LOCK of the re-detection is 1, since LOCK0 is 1, it indicates that the precision DLL can still work normally, at this time, the judgment unit continues to output 1, 0, and LOCK0 continues to keep 1, and the precision of the phase detection unit continues to decrease; repeating the above processes; if the result LOCK of the re-detection is 0, since LOCK0 is 1, the precision DLL can not work normally, at this moment, the output of the judgment unit is 0, increment is 1, the precision of the phase detection unit is restored to the precision of the last phase detection, and then the precision is kept stable and is not changed any more.
Another specific step of adjusting the precision provided in this embodiment is:
t01: the precision of the phase detection unit is set to the minimum precision:
t02: the phase detection module must be unlocked, and the feedback clock CLK _ FB and the reference clock CLK _ REF must detect different phases, i.e., the initial LOCK is 0, and then LOCK0 is 0.
T03: the judging unit outputs a default value of 0 and an increment value of 1, the phase control unit increases the precision of the phase detection unit according to the output result of the judging unit, and the phase relation between the feedback clock CLK _ FB and the reference clock CLK _ REF is judged again.
T04: if the result LOCK of the re-detection is 0, since LOCK0 is 0, it indicates that the precision DLL can still not work normally, at this moment, the judgment unit continues to output default 0, increment 1, and LOCK0 continues to hold 0, and the precision of the phase detection unit continues to increase; repeating the above processes; if the result LOCK of the re-detection is 1, since LOCK0 is 0, it indicates that the precision DLL can work normally, and this precision is the minimum precision of the phase detection that the whole DLL can reach, at this moment, the output of the judgment unit is 0, and 0, the precision of the phase detection unit maintains the precision of this phase detection, and keeps stable and does not change any more.
The above description is only a preferred embodiment of the present invention, and the embodiment is not intended to limit the scope of the present invention, so that all equivalent structural changes made by using the contents of the specification and the drawings of the present invention should be included in the scope of the appended claims.
Claims (10)
1. A delay phase-locked loop capable of automatically adjusting precision is characterized by comprising a phase detection module, a delay module, a control module and a selection module; the phase detection module comprises 2 input ports and a phase state output port, wherein the 2 input ports of the phase detection module are respectively connected with a reference clock and a feedback clock, and the phase state output port is connected with the input port of the control module; the output port of the control module is connected with the input port I of the selection module and used for outputting control words to the selection module; the input port of the delay module is connected with the reference clock, and the output port of the delay module is connected with the input port II of the selection module and used for outputting the delay clock to the selection module; the output port of the selection module outputs the selected clock; the phase detection module comprises a phase detection unit, a storage unit, a judgment unit and a phase control unit, wherein the phase detection unit is used for comparing the phase states of a feedback clock and a reference clock, the storage unit is used for storing the detection result of the last phase detection, the judgment unit compares the last phase detection result with the current phase detection result to obtain the adjustment direction of the phase detection unit, and the phase control unit adjusts the detection precision of the phase detection unit according to the output result of the judgment unit.
2. The dll as claimed in claim 1, wherein the phase detection unit comprises two input terminals and an output terminal, the two input terminals of the phase detection unit are respectively connected to a reference clock and a feedback clock, the output port of the phase detection unit is used for outputting a phase detection result, the output port is respectively connected to the storage unit and the judgment unit, the judgment unit is simultaneously connected to the storage unit and the phase control unit, and the phase control unit is connected to the phase detection unit and is used for controlling and adjusting the detection accuracy of the phase detection unit.
3. The dll of claim 1, wherein the phase state output port outputs three phase detection results, corresponding to the feedback clock delaying the reference clock, the feedback clock advancing the reference clock, and the feedback clock synchronizing with the reference clock.
4. The dll of claim 1, wherein the reference clock is an externally input periodic square wave signal with a standard stable frequency.
5. An automatic precision adjusting delay locked loop as claimed in claim 1, wherein said feedback clock is a2 pi phase clock.
6. The dll of claim 1, wherein the output port of the control module outputs i control words Cj, and Cj is Ci/i, and Cj corresponds to the delay clocks output by the delay module one by one, where i is an integer greater than 1, and j is an integer greater than or equal to 1 and less than or equal to i.
7. A method of performing accuracy adjustment for a delay locked loop as claimed in any one of claims 1 to 6, comprising the steps of:
s01: adjusting the precision of the phase detection unit to a maximum value;
s02: the delay phase-locked loop works under the maximum precision of the phase detection unit until the delay phase-locked loop is stable, at the moment, the control module does not change any more, the phase detection unit detects that the feedback clock and the reference clock are in the same phase, and the phase detection result at the moment is stored in the storage unit;
s03, reducing the precision of the phase detection unit;
s04: the delay phase-locked loop works until the delay phase-locked loop is stable, the control module does not change any more, and if the phase detection unit detects that the feedback clock and the reference clock are in the same phase at the moment, the steps S03-S04 are repeated; if the phase detection unit detects that the feedback clock and the reference clock are unlocked, the accuracy of the phase detection module is judged to exceed the minimum operable accuracy, and the accuracy of the phase detection unit is adjusted to the previous accuracy and is kept unchanged.
8. The method of claim 7, wherein the delay module comprises N identical delay units, and the precision adjustment of the phase detection unit can be adjusted by changing the number of the delay units or adjusting the supply voltage of the delay units, where N is an integer greater than or equal to 1.
9. A method of performing accuracy adjustment for a delay locked loop as claimed in any one of claims 1 to 6, comprising the steps of:
t01: adjusting the precision of the phase detection unit to a minimum value;
t02: the delay phase-locked loop works under the minimum precision of the phase detection unit until the delay phase-locked loop is stable, at the moment, the control module does not change any more, the phase detection unit detects that the feedback clock and the reference clock are unlocked, and the phase detection result at the moment is stored in the storage unit;
t03 increasing the accuracy of the phase detection unit;
t04: the delay phase-locked loop works until the delay phase-locked loop is stable, the control module does not change any more, and if the phase detection unit detects that the feedback clock and the reference clock are unlocked at the moment, the steps T03-T04 are repeated; if the phase detection unit detects that the feedback clock and the reference clock are in the same phase at the moment, the precision of the phase detection module at the moment is judged to be the minimum precision with which the phase detection module can work, and the precision is kept unchanged.
10. The method of claim 9, wherein the delay module comprises N identical delay units, and the precision adjustment of the phase detection unit can be adjusted by changing the number of the delay units or adjusting the supply voltage of the delay units, where N is an integer greater than or equal to 1.
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