CN114866087A - Primary and secondary delay phase-locked loop with double delay lines - Google Patents
Primary and secondary delay phase-locked loop with double delay lines Download PDFInfo
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- 101100499376 Xenopus laevis dll2 gene Proteins 0.000 claims abstract description 9
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- 101150029579 pfd-2 gene Proteins 0.000 description 1
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- H—ELECTRICITY
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- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/07—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop using several loops, e.g. for redundant clock signal generation
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- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
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- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/087—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using at least two phase detectors or a frequency and phase detector in the loop
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Abstract
The invention discloses a primary and secondary delay phase-locked loop with double delay lines, which comprises: the power-on reset module POR, the main-stage delay phase-locked loop DLL1, the secondary delay phase-locked loop DLL2 and the locking indication module LI; the power-on reset module is connected with a reset control module of the primary delay phase-locked loop, an output voltage signal V1 of the primary delay phase-locked loop is connected with a short chain of a secondary double-chain voltage-controlled delay line, an external input clock signal CLK is connected into the primary delay phase-locked loop and the secondary delay phase-locked loop, a total reset signal generated by the primary delay phase-locked loop is connected with a filter module of the secondary delay phase-locked loop, and output signals of the frequency and phase discriminator module PFD1 and the frequency and phase discriminator module PFD2 are respectively connected into the locking indication module. The DLL of the invention has the advantages of accurate locking, small area overhead and the like.
Description
Technical Field
The invention belongs to the digital clock generation technology in the field of integrated circuits, and particularly relates to a primary and secondary delay phase-locked loop with double delay lines.
Background
With the development of semiconductor technology, the technology is continuously improved, and intelligent electronic equipment becomes an integral part of daily life of people. These electronic devices are not powered on, and power supplies are widely used in many aspects of life. Clock generation circuits are important components of Integrated Circuit (IC) systems, and their performance directly affects the overall performance of the system. As the operating frequency of the chip is higher and higher, the requirement for the clock signal is also higher and higher, and the digitization of the switching power supply is a power supply trend. In digitally controlled switching power supplies, Digital Pulse Width Modulation (DPWM) is a very important component.
The mixed DPWM circuit combines a counting-comparing structure and a delay line structure, the front stage uses the counting-comparing structure to carry out coarse adjustment to generate a set signal and a reset signal for controlling the RS trigger, and the rear stage uses the delay line structure to carry out fine adjustment to carry out corresponding phase shift on the reset signal.
The number of Delay units can be reduced by the two-stage Delay line structure, and a Delay Locked Loop (DLL) provides control voltage for the Delay units, so that the Delay units are less affected by the outside. The two DLL modules respectively control the coarse delay line and the fine delay line, but the voltage-controlled delay line inside the DLL for controlling the fine delay line has more delay units and larger layout area.
Disclosure of Invention
In order to overcome the problems in the prior art, the application aims to provide a primary and secondary delay locked loop with double delay lines, the delay locked loop avoids the use of a long delay line when controlling the thick and thin delay lines of the DPWM, and the secondary locked loop is ensured to be locked after the primary delay locked loop is locked.
The technical scheme adopted by the invention for solving the technical problems is as follows:
a primary and secondary delay locked loop with dual delay lines, comprising:
the power-on reset module POR, the main-stage delay phase-locked loop DLL1, the secondary delay phase-locked loop DLL2 and the locking indication module LI; wherein,
the power-on reset module and the external reset signal are used for generating a system work control signal;
the main-stage delay phase-locked loop comprises a phase frequency detector module PFD1, a charge pump module CP1, a reset control module SC, a Filter module Filter1 and a main-stage voltage-controlled delay line module VCDL 1;
the secondary delay phase-locked loop comprises a phase frequency detector module PFD2, a charge pump module CP2, a Filter module Filter2 and a double-chain voltage-controlled delay line module VCDL 2;
the locking indication module is used for judging whether the two phase-locked loops complete locking;
the power-on reset module is connected with a reset control module of the primary delay phase-locked loop, an output voltage signal V1 of the primary delay phase-locked loop is connected with a short chain of a secondary double-chain voltage-controlled delay line, an external input clock signal CLK is connected into the primary delay phase-locked loop and the secondary delay phase-locked loop, a total reset signal generated by the primary delay phase-locked loop is connected with a filter module of the secondary delay phase-locked loop, and output signals of the frequency and phase discriminator module PFD1 and the frequency and phase discriminator module PFD2 are respectively connected into the locking indication module.
The voltage-controlled delay line in the secondary delay phase-locked loop is double-chain, and the delay unit in the first delay chain is the same as the delay unit in the main-stage delay line.
The reset signal of the power-on reset circuit is a ramp signal in the power-on process of a circuit power supply, and is used for avoiding error locking of the phase-locked loop during power-on.
The locking indication module performs exclusive-OR operation on two output signals of the phase frequency detector in the primary delay phase-locked loop, the obtained signals are subjected to AND operation with the signals after being delayed for a short time, the secondary delay phase-locked loop performs the same operation, and finally the obtained two signals are subjected to OR operation.
In the second delay chain of the secondary double-chain voltage-controlled delay line, the delay time of the delay unit is the precision of the digital pulse width modulator, and the total delay time of the delay chain is the delay time after the main-stage delay unit is locked.
According to the double-chain structure of the secondary delay phase-locked loop, after the primary delay phase-locked loop is locked, the total time of the first chain of the secondary delay phase-locked loop is determined, the reference signal is input into the phase frequency detector of the secondary delay line to be determined, and the output signal of the phase frequency detector controls the charge pump to charge and discharge the capacitor to lock the secondary delay phase-locked loop to obtain the locking voltage V2.
The delay time and the number of the delay units of the main-stage delay line delay unit are determined according to the period of the input clock signal, and the number and the delay time of the delay units of the secondary delay line are determined according to the delay precision and the delay units of the main-stage delay line.
The phase frequency detector module PFD1 and the phase frequency detector module PFD2 are provided with parasitic capacitors, and the circuits are precharged before the rising edge of an input signal arrives, so that the working speed of the circuits is increased, and the conduction time of the phase frequency detector is shortened by adopting smaller channel length and large width-to-length ratio.
The charge pump module CP1 and the charge pump module CP2 are provided with charge and discharge switches at the source ends, so that charge sharing is reduced.
Delay units are arranged in the main-stage voltage-controlled delay line module VCDL1 and the double-chain voltage-controlled delay line module VCDL2, the voltage control and adjustment characteristic of delay time is realized by adopting a pseudo-differential structure and controlling RC time constant of an output node, and the delay time is increased by controlling voltage.
The invention has the beneficial effects that:
the invention adopts a primary and secondary delay phase-locked loop with double delay lines, adopts a mixed DPWM structure for a digital pulse width modulation system with higher precision, and has 2 × (T/d 2) delay units if a fine tuning part adopts a single delay line structure under the condition of not considering the delay units which keep consistency in each delay line; the primary DLL structure and the secondary DLL structure are adopted, and T/d2+2(T/d1) + d1/d2 delay units can be obtained; the structure provided by the invention needs 2(d1/d2+ T/d1) +4 delay units, wherein T is a clock period, d1 is the delay time of a coarse delay unit, d2 is the delay time of a fine delay unit, namely precision, and T/d2 is larger when the required precision is higher.
Drawings
Fig. 1 is a block diagram of a digital pulse width modulator according to an embodiment of the present invention.
Fig. 2 is a block diagram of a main-stage delay-locked loop and a reset signal structure provided in an embodiment of the present invention.
Fig. 3 is a block diagram of a secondary delay-locked loop structure provided in an embodiment of the present invention.
Fig. 4 is a block diagram of a double-stranded delay line structure of a secondary dll provided in an embodiment of the present invention.
Fig. 5 is a block diagram of a general structure of a primary and secondary delay-locked loop with dual delay lines according to an embodiment of the present invention.
FIG. 6 is a schematic diagram of waveforms provided in an example of the present invention.
Fig. 7 is a block diagram of a system lock indication module provided in an example of the present invention.
In fig. 1, a counter 101, a comparator 102, a coarse voltage-controlled delay line 103, a fine voltage-controlled delay line 104, a frequency divider 105, an RS latch 106, a first data selector (MUX 1) 107, a second data selector (MUX 2) 108, and a primary and secondary delay locked loop 109 with a double delay line;
in fig. 2, a phase frequency detector (PFD 1) 201, a charge pump (CP 1) 202, a Filter (Filter 1) 203, a main stage voltage controlled delay line (VCDL 1) 204, a power-on reset circuit (POR) 205, and a reset circuit (SC) 206;
in fig. 3, a phase frequency detector (PFD 2) 301, a charge pump (CP 2) 302, a Filter (Filter 2) 303, and a double-chain voltage-controlled delay line (VCDL 2) 304;
in fig. 4, coarse delay cell M1X and fine delay cell M2X.
Detailed Description
In order to make the technical solutions better understood by those skilled in the art, the technical solutions in the embodiments of the present application will be clearly described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are partial embodiments of the present application, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
The mixed digital pulse width modulation system comprises a coarse adjustment part consisting of a counter and a comparator, a clock period is used as the adjustment precision, a voltage-controlled delay line enters after the coarse adjustment part is finished to form a fine adjustment part, and the minimum delay time is used as the adjustment precision. The voltage-controlled delay line is provided with a plurality of delay units, a plurality of delay clock signals which are sequentially delayed for a fixed time can be generated according to a clock signal CLK, more specifically, the clock signal CLK can be decomposed into a group of delay clock signals with different phases or sequentially delayed time intervals of t, the delay clock signals are called delay clock signals, and the voltage-controlled delay line output tap voltage access data selector adjusts the output delay time so as to perform digital pulse width modulation.
The Delay Phase-locked loop is composed of a Phase Frequency Detector (PFD), a Charge Pump (CP), and a Voltage Controlled Delay Line (VCDL), wherein the PFD receives a reference clock from a system clock source and a clock fed back by the VCDL, compares the two clocks, generates an UP signal if the reference clock leads the feedback clock signal, generates a DN signal if the reference clock lags the feedback clock signal, transmits corresponding UP and DN signals into the Charge Pump, controls the on and off of a current source and a current sink of the Charge Pump, further charges and discharges a capacitor, and generates corresponding control Voltage V ctrl ，V ctrl And controlling the delay time of a delay unit in the VCDL, feeding back to the phase frequency detector, performing phase adjustment on a feedback clock, entering the PFD again, repeating the steps, and finally generating stable voltage output.
As shown in fig. 1, which is a schematic diagram of a hybrid digital pulse width modulation structure, the hybrid DPWM structure includes a counter circuit 101, a comparator circuit 102, a coarse tuning voltage-controlled delay line 103, a fine tuning voltage-controlled delay line 104, a frequency divider 105, an RS latch 106, a first data selector 107, a second data selector 108, a primary and secondary delay locked loop (DLL circuit) 109, and a signal CLK is input to a counter 101.
CLK is a high-frequency clock, the clock obtains a low-frequency clock through a counter 101 and a comparator 102, the low-frequency clock enters a coarse tuning voltage-controlled delay line 103, a tap of a delay unit of the coarse tuning voltage-controlled delay line 103 is connected with a first data selector 107, an input signal of the first data selector is a high-order signal of a delay control code, an output signal enters a fine tuning delay line 104, a tap of a delay unit of the fine tuning delay line 104 is connected with a second data selector 108, an input signal of the second data selector is a low-order signal of the delay control code, the output delayed signal and the high-frequency clock signal divided by a frequency divider jointly enter a latch, and finally a DPWM signal is obtained.
In this embodiment, as shown in fig. 1, the main stage voltage controlled delay line 103 may be divided into 8 delay units M11-M18, the secondary stage voltage controlled delay line 104 may be divided into 8 delay units M21-M28, the output 8 delayed clock signals M1 are delayed by 1/8 clock cycles per unit, and the output 8 delayed clock signals clk <0>, clk <1> … clk <7>, which are denoted as clk <7:0 >; m2 may be divided into 1/64 clock cycles, outputting 8 delayed clock signals clk <8>, clk <9> … clk <15>, denoted as clk <15:8 >. For example, if the input clock frequency is 80MHz with a period of 12.5ns, the input clock frequency is delayed by 1.56ns through a coarse delay unit and 195ps through a fine delay unit. By analogy, a set of delayed clock signals CLK <15:0> as shown in fig. 1 is derived from the clock signals CLK after passing through the delay circuits.
A primary and secondary delay locked loop 109 with dual delay lines, comprising: the system comprises a power-on reset module POR, a main-stage delay locked loop module DLL1, a secondary-stage delay locked loop module DLL2 and a locking indication module LI; the power-on reset module, the primary delay phase-locked loop module and the secondary delay phase-locked loop module are sequentially connected; and obtaining control voltages V1 and V2 of two delay chain delay units, wherein the control voltages are connected to a delay chain of the DPWM system, and finally obtaining an analog duty cycle signal.
When the main-stage delay phase-locked loop works, an input clock signal passes through the phase frequency detector, the charge pump and the voltage-controlled delayAfter the chain, the signal F1 is obtained div ，F1 div The phase difference of the two signals is judged by the phase frequency detector and UP and DN signals are output, the UP and DN signals are input into a charge pump to control the charge and discharge of a charge pump to a capacitor, the voltage V1 on the capacitor is obtained, and the V1 is input into a voltage-controlled delay unit so as to change an output signal F1 div After the feedback process DLL1 reaches the locked state, the voltage V1 is locked;
as shown in fig. 2, the main stage delay locked loop DLL1 circuit includes a phase frequency detector (PFD 1) 201, a charge pump (CP 1) 202, a Filter (Filter 1) 203, a main stage voltage controlled delay line (VCDL 1) 204, and a reset circuit (SC) 205. Wherein the voltage controlled delay line is formed by a voltage controlled delay cell M1; the clock signal CLK provides a reference clock with a period of T for the whole digital pulse width modulation circuit, the input end of the phase frequency detector is connected with the clock signal CLK, the reference clock generates two signals of UP1 and DN1 through the phase frequency detector 201 and is connected to the charge pump 202 to control the switch of the charge pump, the charge pump 202 obtains V1 by controlling the charging and discharging of a capacitor in the filter circuit 203, the V1 is connected to the voltage-controlled delay line 204, the clock signal of the voltage-controlled delay line is the system clock CLK, the control voltage is the filter output voltage V1, the signal outputs a signal F1 through the voltage-controlled delay line 204 div ，F1 div Feeding back to the other input port of the phase frequency detector, and repeating the steps until the CLK and F1 are stabilized div One cycle apart, i.e. F1 is obtained after a series of delays for a rising edge of CLK div At this time, F1 div Coincident with CLK, but F1 div Lagging CLK by one cycle.
The secondary delay phase-locked loop is composed of a phase frequency detector module, a charge pump module and a double-chain voltage-controlled delay line module. The double-chain voltage-controlled delay line consists of a delay unit M1X of the main-stage voltage-controlled delay line and a delay unit M2X of the secondary voltage-controlled delay line; there are 8 delay cells M1X in the VCDL1 of the main stage DLL, two delay cells M1X and M2X in the secondary VCDL2, and the total delay time M2X of the secondary delay cells is the delay time of the single module M1X of the main stage VCDL 1. The locking state of the secondary delay locked loop DLL2 is determined by the locking voltage V1 of the primary DLL1 and the feedback of the secondary delay locked loop DLL2, so that the DLL2 circuit can be ensured to be locked after the DLL1 circuit is locked.
As shown in the structure diagram of the secondary delay locked loop (DLL 2) in fig. 3, the input signal of the phase frequency detector 301 is the output signal F of the double-chain voltage-controlled delay line 304 ref And F div The output signal of the phase frequency detector 301 is connected to the charge pump 302, the charge pump 302 controls charging and discharging of a capacitor in the filter 303 to obtain a voltage V2, and the voltage V2 is connected to the double-chain voltage-controlled delay line 304.
The first delay chain of the double-chain voltage-controlled delay line is a coarse delay chain, the delay unit of the first delay chain is the delay unit M1X of the main-stage delay phase-locked loop, and the second delay chain is a fine delay chain, and the delay unit of the second delay chain is M2X; when the phase-locked loop is locked, the total delay time of the two chains is the same; the signal returned by the input clock through the first delay chain is F ref As the first input signal of the phase frequency detector, the signal returned by the input clock through the second delay chain is F div As the second input signal of the phase frequency detector.
Referring to FIG. 4, a dual-chain DLL 304 structure of the secondary DLL2 is shown, in which CLK is input through a buffer delay unit M11 and then coupled to the delay line 401 and the delay line 402, respectively, and the CLK output signal through the delay line 401 is F ref The output signal through the delay line 402 is F div . The input signal V1 is the output voltage of the main stage voltage controlled delay line.
The total delay time of 8M 2X in FIG. 4 is 1 delay time of M1X, and the delay times of M21-M28 are equal to the delay time of M12, i.e., the delay time is equal to the delay time of M12
M11+M21+⋯+M28+M15=M11+M12+M13
M21+⋯+M29=M12。
F ref When the primary delay locked loop is unlocked, the delay time of each delay unit in the low-precision delay chain is not fixed, so that the high-precision delay chain cannot be locked, and the DLL2 is ensured to be locked after the DLL 1; after the master DLL is locked, F ref Phase stabilization, phase frequency detector, charge pump, second delay chain start lock of secondary delay phase-locked loopWorking in phase, finally F ref And F div The same phase is reached, so far the secondary delay-locked loop locks with a locking voltage V2.
In this example, V1 is the control voltage of the voltage controlled delay line 401, CLK is the output signal F through the voltage controlled delay line 401 ref CLK outputs a signal F through a voltage controlled delay line 402 div When the main delay phase-locked loop is stabilized, F ref The phase of the secondary delay-locked loop is not changed any more, the system feedback loop of the secondary delay-locked loop can be stabilized, and at this time F ref And F div The periodic phases are all coincident. To ensure consistency with the DPWM circuit, each delay cell at 109 is followed by the same load as the MUX input stage.
As shown in fig. 6 in connection with this example, T =12.5ns, assuming that d1=1.56ns and d2=195ps, that is, the delay time of each M1 after the dll is locked is 1.56ns and the delay time of each M2 is 195ps, then n = T/d1=8 and M = d1/d2=8, if a single delay line structure needs 2mn =128 delay cells, and a primary and secondary dll structure needs mn +2n + M =88 delay cells, and a structure according to the present invention needs 2 (M + n) +4=36 delay cells, the number of delay cells can be effectively reduced.
A POR (Power On Reset) circuit 206, in which the Power-On voltage is a ramp signal to prevent delaying the phase-locked loop from locking when the system operating voltage is not reached, and the Power-On Reset signal and an external Reset signal together form an input signal of the Reset module; the POR circuit ensures that the condition of wrong locking cannot occur in the power-on process; in addition, an off-chip Reset signal and Reset circuit 205 is added to the circuit, and the off-chip Reset signal and the external Reset _ in signal jointly form a Reset signal Reset.
Such as 201 and 301 in fig. 2 and 3, are precharge phase frequency detectors, which precharge a circuit before a rising edge of an input signal due to the presence of parasitic capacitance, increase the operating rate of the circuit, and reduce the on-time of the PFD by using a smaller channel length and a large width-to-length ratio.
As shown in the circuit 205 in fig. 2, the D flip-flop is a core, and when the system is normally started, the Start signal is low to Reset the D flip-flop, and the Reset signal is generated to make the initial values of the control voltages V1 and V2 zero.
As shown in fig. 5, the overall structure 109 is shown, the input signal is the high frequency clock CLK, the output signals are V1 of the voltage controlled delay line 103, and the voltage V2 of the voltage controlled delay line 104.
As shown in fig. 7, the lock indication module 501 (LI) is composed of an exclusive or operation, an and operation, an or operation and a delay module, and performs an exclusive or operation on the output signal of the phase frequency detector in the main-stage delay phase-locked loop to obtain a signal D11; and the output signals of the phase frequency detector in the secondary delay phase-locked loop are subjected to exclusive OR operation to obtain a signal D21.
The D11 signal is processed by a delay module to obtain a signal D12, the D12 and the D11 are processed by AND operation to obtain a signal S1, and when the signal S1 is at low level and keeps unchanged, the locking of the primary delay phase-locked loop is represented; the D21 signal is processed by a delay module to obtain a signal D22, the D22 and the D21 are processed by AND operation to obtain a signal S2, and when the signal S2 is at low level and keeps unchanged, the signal represents locking of the secondary delay phase-locked loop; the signals S1 and S2 are OR' ed to obtain an LI signal, which is low and remains unchanged, indicating that the entire system has completed locking.
The above embodiments are only used for illustrating the embodiments of the present application, and not for limiting the embodiments of the present application, and those skilled in the relevant art can make various changes and modifications without departing from the spirit and scope of the embodiments of the present application, so that all equivalent technical solutions also belong to the scope of the embodiments of the present application, and the scope of patent protection of the embodiments of the present application should be defined by the claims.
Claims (10)
1. A primary and secondary delay-locked loop with dual delay lines, comprising:
the power-on reset module POR, the main-stage delay phase-locked loop DLL1, the secondary delay phase-locked loop DLL2 and the locking indication module LI; wherein,
the power-on reset module and the external reset signal are used for generating a system work control signal;
the main-stage delay phase-locked loop comprises a phase frequency detector module PFD1, a charge pump module CP1, a reset circuit SC, a Filter module Filter1 and a main-stage voltage-controlled delay line module VCDL 1;
the secondary delay phase-locked loop comprises a phase frequency detector module PFD2, a charge pump module CP2, a Filter module Filter2 and a double-chain voltage-controlled delay line module VCDL 2;
the locking indication module is used for judging whether the two phase-locked loops complete locking;
the power-on reset module is connected with a reset control module of the primary delay phase-locked loop, an output voltage signal V1 of the primary delay phase-locked loop is connected with a short chain of a secondary double-chain voltage-controlled delay line, an external input clock signal CLK is connected into the primary delay phase-locked loop and the secondary delay phase-locked loop, a total reset signal generated by the primary delay phase-locked loop is connected with a filter module of the secondary delay phase-locked loop, and output signals of the frequency and phase discriminator module PFD1 and the frequency and phase discriminator module PFD2 are respectively connected into the locking indication module.
2. The primary and secondary delay-locked loops with dual delay lines as claimed in claim 1, wherein the voltage-controlled delay lines in the secondary delay-locked loop are double-chained, and the delay cells in the first delay chain are the same as those in the primary delay line.
3. A primary and secondary delay-locked loop with dual delay lines as claimed in claim 1, wherein the reset signal of the power-on reset circuit and the power-on process of the circuit are ramp signals for avoiding false locking of the phase-locked loop at power-on.
4. The pll with dual delay lines of claim 1, wherein the lock indication module performs xor operation on two output signals of the phase frequency detector in the primary dll, and the obtained signal is then delayed for a short time and then subjected to and operation with the signal itself, and the secondary dll performs the same operation, and finally performs or operation on the obtained two signals.
5. The pll of claim 2, wherein the delay time of the second delay chain of the secondary double-chain voltage-controlled delay line is the precision of the digital pwm, and the total delay time of the delay chain is the delay time after the locking of the primary delay unit.
6. The primary and secondary delay-locked loops with dual delay lines as claimed in claim 2, wherein the secondary delay-locked loop has a double chain structure, when the primary delay-locked loop is locked, the total time of the first chain of the secondary delay-locked loop is determined, the phase frequency detector of the secondary delay line inputs a reference signal to determine, and the output signal of the phase frequency detector controls the charge and discharge of the charge pump to the capacitor to lock the secondary delay-locked loop, so as to obtain the locking voltage V2.
7. A primary and secondary delay locked loop with dual delay lines as claimed in any one of claims 1 to 6,
and determining the delay time and the number of the delay units of the main-stage delay line according to the period of the input clock signal, and determining the number and the delay time of the delay units of the secondary delay line according to the delay precision and the delay units of the main-stage delay line.
8. The secondary dual-delay line primary and secondary delay locked loop of claim 1, wherein the PFD1 and PFD2 have parasitic capacitances to precharge the circuit before the rising edge of the input signal, thereby increasing the operating speed of the circuit, and the circuit uses a smaller channel length and a larger width-to-length ratio to reduce the turn-on time of the phase frequency detector.
9. The phase locked loop of claim 1, wherein the charge pump module CP1 and the charge pump module CP2 have charge and discharge switches at the source end to reduce charge sharing.
10. The primary and secondary delay-locked loops with dual delay lines as claimed in claim 1, wherein the primary voltage-controlled delay line module VCDL1 and the double-chain voltage-controlled delay line module VCDL2 are respectively provided with a delay unit, and a pseudo-differential structure is adopted to control an RC time constant of an output node, thereby realizing a voltage control regulation characteristic of delay time, and increasing the delay time of control voltage.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116089937A (en) * | 2023-04-10 | 2023-05-09 | 灿芯半导体(苏州)有限公司 | All-digital sensor capable of resisting multiple fault injection |
| CN116382420A (en) * | 2023-03-14 | 2023-07-04 | 灿芯半导体(上海)股份有限公司 | System and method for solving problem of small margin of all-digital sensor |
| CN116455389A (en) * | 2023-06-13 | 2023-07-18 | 中科海高(成都)电子技术有限公司 | Delay adjustment method and device, locking indication method and device and electronic equipment |
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2022
- 2022-03-10 CN CN202210229131.1A patent/CN114866087A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116382420A (en) * | 2023-03-14 | 2023-07-04 | 灿芯半导体(上海)股份有限公司 | System and method for solving problem of small margin of all-digital sensor |
| CN116382420B (en) * | 2023-03-14 | 2024-01-23 | 灿芯半导体(上海)股份有限公司 | System and method for solving problem of small margin of all-digital sensor |
| CN116089937A (en) * | 2023-04-10 | 2023-05-09 | 灿芯半导体(苏州)有限公司 | All-digital sensor capable of resisting multiple fault injection |
| CN116455389A (en) * | 2023-06-13 | 2023-07-18 | 中科海高(成都)电子技术有限公司 | Delay adjustment method and device, locking indication method and device and electronic equipment |
| CN116455389B (en) * | 2023-06-13 | 2023-09-08 | 中科海高(成都)电子技术有限公司 | Delay adjustment method and device, locking indication method and device and electronic equipment |
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