CN109696821A - Two-stage digital time converter - Google Patents
Two-stage digital time converter Download PDFInfo
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- CN109696821A CN109696821A CN201811529767.8A CN201811529767A CN109696821A CN 109696821 A CN109696821 A CN 109696821A CN 201811529767 A CN201811529767 A CN 201811529767A CN 109696821 A CN109696821 A CN 109696821A
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- delay
- circuit
- time
- stage digital
- digital time
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- G—PHYSICS
- G04—HOROLOGY
- G04F—TIME-INTERVAL MEASURING
- G04F10/00—Apparatus for measuring unknown time intervals by electric means
- G04F10/005—Time-to-digital converters [TDC]
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
- H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
- H03L7/0814—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the phase shifting device being digitally controlled
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
Abstract
A kind of two-stage digital time converter, it include: the first delay circuit, input gate-control signal and light pulse signal, including the time delay chain using voltage controllable time delay unit composition, for the corresponding delay output of high-order control multiple selector selection of delays time to control word, the corresponding delay time time delay chain is generated；Second delay circuit is connected to the rear end of the first delay circuit, including first order phase inverter, and the first inverter output is connected to multiple parallel unit capacitors, and the first inverter output is also connected with the second phase inverter.The present invention combines more advanced and stable integrated circuit fabrication process by design optimization delay circuit structure, realizes that the delay step value lower than gate delay obtains higher delay resolution.
Description
Technical field
The present invention relates to quantum key communication and photon detector fields, convert further to a kind of two-stage digital time
Device.
Background technique
The most commonly used is door-control type single-photon detectors in current quantum communications key generation device.Door-control type detector one
A key control point is, can only quantum signal light pulse reach detector a very little time window (gating window), visit
Surveying device could respond.In systems in practice, due to signal light, different and Electric signal processing is brought from the light path that synchronizable optical is passed through
The factors such as delay, detector gate-control signal tends not to precisely align at detector with light pulse signal, so in system
Precisely aligning for gate-control signal and light pulse signal is realized with regard to needing a kind of control mode.
In the implementation method of delay circuit, the delay circuit step value based on clock count method depends on the week of reference clock
Phase generally can only achieve nano second class resolution ratio.Prolonged using the minimum that the circuit step value of delay chain structure depends on delay unit
When, there are a lower limits for the minimum gate delay that can be obtained under special process.When the delay precision of delay circuit requires to be less than
When minimum gate delay, required step value has been unable to get using simple delay chain structure.Meanwhile it is dynamic in order to improve delay
State range, it usually needs increase the series of delay unit, increase so as to cause system power dissipation and the linearity declines.Domestic at present
Delay circuit design builds time delay chain using FPGA internal resource come when realizing, resolution ratio also can only achieve hundred picosecond levels.
The size that S.AlAhdab in 2012 proposes a kind of digital control load capacitance realizes the resolution ratio of subpicosecond, nanosecond
Dynamic range, but its input clock frequency is only up to 8MHz.
Input clock signal frequency size in general delay circuit is related with the dynamic range of delay, that is, the dynamic being delayed
Range does not exceed a clock cycle.The present invention be directed to an aperiodic clock signals, when 1.5GHz is the smallest one
Clock signal pulsewidth, as shown in Figure 1, detector gate-control signal (gated control pulse) cannot and light pulse signal
(signal light) is precisely aligned at detector, so needing to design a kind of delayed time system that high-resolution is controllable just to realize
Gate-control signal and light pulse signal precisely align.The dynamic range of the delay of system requirements considerably beyond a clock cycle,
It can aggravate the decaying of narrow pulse signal in this way.C.Chuang devises a kind of delay of the wide dynamic range of heterogeneous output within 2009
Locking ring, delay unit therein can transmit the up to clock frequency of GHz.
In the structure of delay circuit, realize the core component delay unit of delay step value by devices such as metal-oxide-semiconductor, capacitors
Composition, the modes such as the gate delay being made up of metal-oxide-semiconductor, capacitor electric discharge adjust the specific delay output of generation.And these devices
Electrical parameter have certain process deviation, while also be easy influenced by temperature and voltage change, thus cause delay with
PVT variation generate deviation, reduce the linearity of delay circuit and the stability of step value precision.
Summary of the invention
In view of this, the purpose of the present invention is to provide a kind of two-stage digital time converter, at least partly to solve
The technical issues of stating.
The present invention provides a kind of two-stage digital time converter, comprising:
First delay circuit inputs gate-control signal and light pulse signal, including using voltage controllable time delay unit composition
Time delay chain, for the corresponding delay output of high-order control multiple selector selection of delays time to control word, when generating corresponding delay
Between；
Second delay circuit is connected to the rear end of the first delay circuit, including first order phase inverter, the output of the first phase inverter
End is connected to multiple parallel unit capacitors, and the first inverter output is also connected with the second phase inverter.
In a further embodiment, further includes: the first coded conversion device, input control signal are used to form described
The control code of first delay circuit middle rank time delay chain gating switch；Second coded conversion device, input control signal, for controlling the
The size of specific capacitance in two delay circuits.
In a further embodiment, first coded conversion device is Binary Conversion into class thermometer-code coding staff
The converter of formula.
In a further embodiment, second coded conversion device is the conversion that binary system turns standard thermometer code
Device.
In a further embodiment, further includes: the first bias voltage circuit, including delay locked loop, for providing
The bias voltage of first delay circuit；Second bias voltage circuit, including delay locked loop, for providing the first delay circuit
Bias voltage.
In a further embodiment, first bias voltage circuit and the second bias voltage circuit respectively include:
Phase frequency detector, charge pump, loop filter and voltage control delay line.
It in a further embodiment, include multiple thick delay units on the time delay chain, which is base
In the hungry improved extension apparatus of electric current.
In a further embodiment, first delay circuit includes multistage transmission gate switch, on time delay chain
Parallel connection constitutes output stage.
In a further embodiment, the quantity of the thick delay unit is 32, and the load of each thick delay unit
It is identical.
In a further embodiment, the charge pump uses cascode structure.
The present invention combines more advanced and stable IC manufacturing work by design optimization delay circuit structure
Skill realizes that the delay step value lower than gate delay obtains higher delay resolution；
High-resolution delay circuit of the invention simultaneously mostly uses the circuit structure design of optimization, and it is dynamic to take into account biggish delay
The variation of PVT deviation bring is adaptively adjusted in the digit time converter that state range and higher frequency input signal require,
Reduce influence of the PVT deviation to system.
Detailed description of the invention
Fig. 1 is the gate-control signal and light pulse signal schematic diagram being inaccurately aligned in the prior art；
Fig. 2 is the two-stage digital time converter block diagram of the embodiment of the present invention；
Fig. 3 is the first delay circuit (thick switching stage time delay chain (Coarse_stage)) schematic diagram of the embodiment of the present invention；
Fig. 4 is delay unit (VCDU) circuit diagram in the first delay circuit；
Fig. 5 is the second delay circuit (thin transfer delay grade (Fine_stage)) schematic diagram of the embodiment of the present invention；
Fig. 6 provides the delay-locked loop (DLL) of bias voltage for the first delay circuit and the second delay circuit；
Fig. 7 is the first delay circuit and the second delay circuit starting control phase frequency detector (Start_controlled
PFD)
Fig. 8 is the first delay circuit and the second delay circuit charge pump (CP).
Specific embodiment
To make the objectives, technical solutions, and advantages of the present invention clearer, below in conjunction with specific embodiment, and reference
Attached drawing, the present invention is described in further detail.
The embodiment of the present invention provides a kind of circuit with two-stage digital time converter, and delay with higher is differentiated
Rate combines the time-to-digit converter of biggish delay dynamic range and higher frequency input signal requirement.And it adopts
With the adaptive delay-locked loop circuit for adjusting the variation of PVT deviation bring, influence of the PVT deviation to system is reduced.
Under SMIC55nm technique, input clock frequency 1.5GHz, the step value of delay is 10ps, and be delayed dynamic range
For 5ns.For this design objective, the embodiment of the present invention uses two-stage delay circuit framework, as shown in Figure 2.Two-stage delay electricity
Road is respectively low bit (LSB) controlled stage for realizing high-precision step value and the higher bit (MSB) for taking into account Larger Dynamic reference time delay
Controlled stage.First coded conversion device, such as Binary_to_one-hot are a kind of Binary Conversions into similar thermometer-code
A kind of converter of coding mode, the difference of it and thermometer-code is its only only one high-order (1), and other are all low levels
(0), it is generally used to indicate that the state of state machine, and within the system, it is used as the control of thick switching stage time delay chain gating switch
Code processed.Second coded conversion device, such as Binary_to_thermometer are the conversions that a kind of binary system turns standard thermometer code
Device, it is used to control the size of load capacitance in thin switching stage.Thick switching stage (coarse_stage) delay circuit (namely the
One delay circuit) time delay chain (as shown in Figure 3) using voltage controllable time delay unit composition, and the high-order control of delays time to control word
The corresponding delay output of multiple selector selection processed, generates corresponding delay time, resolution ratio is up to several hundred picosecond magnitudes.It is thick to turn
It changes grade delay circuit multistage transmission gate switch parallel connection and constitutes output stage, there is no driving capabilities for transmission gate switch, so needing to have
There is the driving circuit of very big driving capability.Because an only way switch is selected every time selects conducting, race hazard is not present, so
It is four that inventor, which divides output stage one, four tunnels selection conducting switch control output, this ensures that Coarse_stage has foot
Enough big driving capabilities.Thin switching stage (fine_stage) is selected to adjust delay size using the size for adjusting load capacitance,
It can produce the temporal resolution lower than gate delay in this way, break the limitation of technique.
In order to make transmission delay step value and dynamic range not with technique, it is anti-to adjust hunger type for voltage, the influence of temperature
The bias voltage of phase device is provided by reference delay-locked loop, it is the time delay ring of a negative feedback mechanism, can be generated in real time with work
Skill, voltage, temperature change bias voltage, to generate stable delay step value and stable delay dynamic range.Delay
Locking ring, which is also classified into, provides the first bias voltage circuit DLL_ of bias voltage for the first delay circuit (coarse_stage)
Coarse and for the second delay circuit (fine_stage) provide bias voltage the second bias voltage circuit DLL_fine.DLL_
The clock frequency period of the input reference voltage of coarse is the delay dynamic range of system, controls the clock CLK_ of DLL_fine
START and CLK_STOP is two neighbouring output clocks of time delay chain in DLL_coarse, their clock interval size is
The delay dynamic range of fine_stage.
In the design of two-stage delay circuit system architecture, the resolution ratio of coarse_stage is 156.25ps, control word ratio
Special number is 5bit.Thick delay unit (VCDU) is improved based on current-steering phase inverter in Coarse_stage, such as
Shown in Fig. 4, control voltage VC therein generates bias current on M1, to control the rising edge of input clock.Last
The control signal pulsewidth of charge and discharge grade is consistent it is ensured that the duty ratio of output clock signal is close to 50%, so as to avoid defeated
Clock pulses decaying out causes greatly very much not export by the signal of entire time delay chain, so that overall reduce declining for output signal
Subtract.Wherein M2 and M5 is a charge and discharge in order to cooperate charge pump in the delay-locked loop of adaptive adjusting PVT change of error
The control voltage of time delay chain, is moved close to a range of Vref/2 by the electric the smallest control voltage range of current mismatch
It is interior.In order to not influence the regulating power of homophony keyholed back plate, the breadth length ratio of general M2 and M5 are long much smaller than the width of control pipe M1 and M4
Than.
The circuit theory of thin switching stage (fine_stage) (namely the second delay circuit) is as shown in figure 5, M1 and M2 structure
At the output of first order phase inverter be connected to one group of 16 shunt capacitance, each specific capacitance (CL) is two and is connected by source and drain
What the metal-oxide-semiconductor parallel connection being connected together was constituted, grid is connected together and to the output end of first order phase inverter, is applied to leakage
The digital voltage of source determines whether MOS channel forms, so that channel capacitance is inserted into or removed according to drain-source end logic.16 CL
Identical, they are arranged not in accordance with binary weighting group, but are controlled by the thermometer-code of 16 bits, and switch is cut in this way
It changes less, can reduce burr, it is most important that the linearity is improved.Thin switching stage generates 146.48ps's by control word
Be delayed dynamic range, and delay step value is 9.77ps.Wherein bias voltage controls the bias current of entire hunger type phase inverter, it
Automatic adjustment adapts to the change of delay step value and dynamic range caused by the variation of technique, voltage and temperature.Simultaneously be used as than
Phase inverter compared with device is also to increase a control pipe, and the pipe breadth length ratio of M6 is not only smaller than main control pipe M3, but also wants small
In M5, mainly extend the fall time of output pulse, to reduce the decaying of pulsewidth.
Delay-locked loop (DLL) compares traditional phaselocked loop, uses voltage control delay unit, delay jitter is small, is being
There is unrivaled advantage in terms of stability, the bandwidth of uniting.The effect of Variable delay line (VCDL) is to carry out signal centainly
Delay, delay time are determined by control voltage Vctrl.In the ideal case, the delay time of VCDL and control voltage Vctrl at
Linear relationship, the slope of curve are VCDL gain Kvcdl (rad/V).The slope of curve can be positive number, be also possible to negative.I.e.
Delay time reduces with the increase of control voltage.In embodiments of the present invention, the voltage control delay curve of thick converting unit
Slope is positive number, and the voltage control delay slope of a curve of thin TCU transfer control unit is exactly negative.The mathematical model table of VCDL
It is up to formula
Delay=Kvcdl·Vctrl+t0
t0For the inherent delay time of VCDL, t0>0。
DLL_coarse (namely the first bias voltage circuit) and DLL_fine (namely second in the embodiment of the present invention
Bias voltage circuit) bias voltage mainly is provided for thick converting unit and thin TCU transfer control unit, as shown in fig. 6, DLL_
Variable delay line and Variable delay controlled stage in coarse and DLL_fine respectively with the coarse_stage of main time delay chain and
Fine_stage variable delay element having the same, they mainly provide bias voltage, and to adjust, slightly conversion is single in main time delay chain
The driving capability of first and thin converting unit inhibits transmission delay to be influenced by PVT with this.Basic DLL is by phase discriminator (PD), electricity
Lotus pumps (CP), loop filter (LP) and voltage control delay line (VCDL) composition.
VCDL in first bias voltage circuit (DLL_coarse) may include 32 delay units (VCDU), output delay
Signal afterwards is fed back into PD, and PD is used for the phase relation of comparison reference clock and feedback signal, and output indicates that the two phase is closed
The phase signal of system, the phase signal are converted to the variation of the control voltage of VCDL by CP and LP, form negative-feedback.In ring
Under the effect of road, by constantly adjusting the control voltage of VCDL, reference signal and the same phase of feedback signal are realized.In the embodiment of the present invention
The delay-locked loop of thick switching stage be using the period for 200M reference clock as input, reference clock is mentioned by the crystal oscillator of outside
For.So the delay dynamic range of thick switching stage is 5ns, step value 156.25ps.But when the initial time delay of time delay chain is small
In half of input reference clock, or the input reference clock greater than 1.5 times, basic DLL, which can exist to be locked to, to be tended to becoming
Possibility in direction or input reference clock integral multiple for 0, when in view of factors such as technique changes, DLL_coarse hair
A possibility that raw locking mistake, is bigger.The lockout issue of the mistake can be avoided in some designs by additional auxiliary circuit.
Firstly, generally by by phase discriminator can phase of operation expand to ± 2 π, it is such to prolong but if without other control circuits
When locking ring also will can only tend to delay be 0 direction-locking.For high-frequency signal, reference input clock Clk_ref with
A possibility that initial time delay between Clk_out is greater than two clock cycle is bigger, and the probability of error lock is bigger.
Error lock is solved the problems, such as using a kind of phase frequency detector (PFD) in the embodiment of the present invention.It is based on dynamic
The reducible PFD (SC_PFD) by starting control of state DFF.Firstly, by between the outputting and inputting of the VCDL of DLL_coarse
Delay be initially set to minimum value, and allow activate PFD output signal DN, it is assumed that the delay of VCDL with control voltage
Decline and increase.Therefore, the delay between the outputting and inputting of VCDL will be increased up a clock for reaching input signal
Period.So no matter VCDL provide delay time have how long, DLL will not lock mistake, and delay time is fixed as one
A clock cycle.This SC_PFD resets dynamic DFF group by what a reducible dynamic DFF and two were made of NAND
At schematic block circuit diagram is as shown in Figure 7.Advantage using this kind of PFD is that circuit diagram is simple, operable input reference frequency compared with
Height, reset path is shorter, and power consumption is lower, and the duty ratio of followed by Clk_ref and Clk_out do not need accurately to reach 50%, because
It is edging trigger for the triggering type of DFF.Inventor by the more even level phase inverters of output cascade in Fig. 7, thus
Additional delay is introduced in PFD to extend the charging time of capacitor.Because if the pulse width of UP and DN is inadequate, capacitor charging
The voltage value of arrival does not reach the threshold value for making switch conduction, can not thus make the switch conduction in charge pump.
The mismatch that the most important problem of the PFD/CP linearity is current source is influenced in fact, and electric current can be with process corner
Variation and change, and electric current can also be influenced by charge pump output voltage, when charge pump is there are when charging and discharging currents mismatch, general
Additional charge injection and outflow loop filter are had, periodic voltage fluctuation can be generated on capacitor.And charge pump
Unstable being mainly derived from of output voltage switchs metal-oxide-semiconductor channel-length modulation, and the metal-oxide-semiconductor of long channel can effectively weaken
Channel modulation effect makes the output voltage of charge pump tend to a stationary value.As shown in figure 8, it can using cascode structure
To improve the output impedance of current source, to make the voltage change of charge pump outputs to the shadow of metal-oxide-semiconductor saturation region curent change
Sound greatly reduces.Transmission gate can reduce the mismatch of charge and discharge branch switch turn-on time as switch.Next charge pump
Non-ideal effects are exactly clock feedthrough and the charge injection of switching tube, and countermeasure is one dummy pipe of access, with control switch
The opposite clock of pipe clock come control a drain-source connection metal-oxide-semiconductor.
In order to replicate the VCDU of VCDU (DCC in Fig. 6) and the coarse_stage of DLL_coarse completely, VCDU
Load also should be consistent, so joined dummy buffer (DB in Fig. 6) at the node of VCDL.For the purposes of
Identical delay is obtained between Clk_ref and Clk_out, joined dummy delay unit (DCC_D) after Clk_ref, really
The load for protecting them is consistent.Buf is the buffer cell of correction waveform.
After DLL_coarse stablizes, the time delay interval between CLK_start and CLK_stop is exactly thin switching stage
One delay dynamic range, the step value of thin switching stage indicate with Td_f, then
Fine_stage_1-fine_stage_2=16Td_f
The delays time to control unit of DLL_fine and fine_stage must be also consistent, the stepping of such fine_stage
Value and dynamic range can just follow the variation of DLL_fine.To which the variation of negative-feedback compensation PVT turns to thick conversion unit and carefully
Change the influence of control unit.
Particular embodiments described above has carried out further in detail the purpose of the present invention, technical scheme and beneficial effects
Describe in detail bright, it should be understood that the above is only a specific embodiment of the present invention, is not intended to restrict the invention, it is all
Within the spirit and principles in the present invention, any modification, equivalent substitution, improvement and etc. done should be included in protection of the invention
Within the scope of.
Claims (10)
1. a kind of two-stage digital time converter, characterized by comprising:
First delay circuit inputs gate-control signal and light pulse signal, including the delay using voltage controllable time delay unit composition
Chain generates corresponding delay time for the corresponding delay output of high-order control multiple selector selection of delays time to control word；
Second delay circuit, is connected to the rear end of the first delay circuit, including first order phase inverter, and the first inverter output connects
Multiple parallel unit capacitors are connect, the first inverter output is also connected with the second phase inverter.
2. two-stage digital time converter according to claim 1, which is characterized in that further include:
First coded conversion device, input control signal are used to form the first delay circuit middle rank time delay chain gating switch
Control code；
Second coded conversion device, input control signal, for controlling the size of specific capacitance in the second delay circuit.
3. two-stage digital time converter according to claim 2, which is characterized in that first coded conversion device is two
System is converted into the converter of class thermometer-code coding mode.
4. two-stage digital time converter according to claim 2, which is characterized in that second coded conversion device is two
System turns the converter of standard thermometer code.
5. two-stage digital time converter according to claim 1, which is characterized in that further include:
First bias voltage circuit, including delay locked loop, for providing the bias voltage of the first delay circuit；
Second bias voltage circuit, including delay locked loop, for providing the bias voltage of the first delay circuit.
6. two-stage digital time converter according to claim 5, which is characterized in that first bias voltage circuit and
Second bias voltage circuit respectively include: phase frequency detector, charge pump, loop filter and voltage control delay line.
7. two-stage digital time converter according to claim 1, which is characterized in that include multiple thick on the time delay chain
Delay unit, the thick delay unit are based on the improved extension apparatus of electric current starvation principle.
8. two-stage digital time converter according to claim 1, which is characterized in that first delay circuit includes more
Grade transmission gate switch, it is in parallel on time delay chain to constitute output stage.
9. two-stage digital time converter according to claim 7, which is characterized in that the quantity of the thick delay unit is
32, and the load of each thick delay unit is identical.
10. two-stage digital time converter according to claim 6, which is characterized in that the charge pump is total using common source
Grid structure.
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| CN110673113A (en) * | 2019-08-16 | 2020-01-10 | 西安电子科技大学 | High-precision low-kickback-noise clock regeneration delay chain |
| CN110673113B (en) * | 2019-08-16 | 2021-08-10 | 西安电子科技大学 | High-precision low-kickback-noise clock regeneration delay chain |
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| CN110764492A (en) * | 2019-11-15 | 2020-02-07 | 北京广利核系统工程有限公司 | Multichannel switching value signal generating device and SOE event simulator |
| CN112054800A (en) * | 2020-08-03 | 2020-12-08 | 博流智能科技（南京）有限公司 | Digital time conversion method, digital time converter and digital phase-locked loop |
| CN112054800B (en) * | 2020-08-03 | 2023-08-08 | 博流智能科技（南京）有限公司 | Digital time conversion method, digital time converter and digital phase-locked loop |
| CN114509929A (en) * | 2022-01-20 | 2022-05-17 | 芯思原微电子有限公司 | Time-to-digital conversion system |
| CN114509929B (en) * | 2022-01-20 | 2023-09-12 | 芯思原微电子有限公司 | Time-to-digital conversion system |
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