CN110673113B - High-precision low-kickback-noise clock regeneration delay chain - Google Patents
High-precision low-kickback-noise clock regeneration delay chain Download PDFInfo
- Publication number
- CN110673113B CN110673113B CN201910759880.3A CN201910759880A CN110673113B CN 110673113 B CN110673113 B CN 110673113B CN 201910759880 A CN201910759880 A CN 201910759880A CN 110673113 B CN110673113 B CN 110673113B
- Authority
- CN
- China
- Prior art keywords
- transistor
- clock
- delay
- transistors
- terminal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 230000008929 regeneration Effects 0.000 title claims abstract description 45
- 238000011069 regeneration method Methods 0.000 title claims abstract description 45
- 238000006243 chemical reaction Methods 0.000 claims abstract description 34
- 230000001172 regenerating effect Effects 0.000 claims description 9
- 238000001914 filtration Methods 0.000 claims description 6
- 238000010586 diagram Methods 0.000 description 14
- 230000000630 rising effect Effects 0.000 description 7
- 101000885321 Homo sapiens Serine/threonine-protein kinase DCLK1 Proteins 0.000 description 5
- 102100039758 Serine/threonine-protein kinase DCLK1 Human genes 0.000 description 5
- 108010001267 Protein Subunits Proteins 0.000 description 4
- 238000007599 discharging Methods 0.000 description 4
- 230000003111 delayed effect Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 2
- 230000008602 contraction Effects 0.000 description 2
- 238000001514 detection method Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 230000001934 delay Effects 0.000 description 1
- 230000007613 environmental effect Effects 0.000 description 1
- 230000014509 gene expression Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- G01S7/00—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00
- G01S7/48—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S17/00
- G01S7/483—Details of pulse systems
- G01S7/486—Receivers
- G01S7/4865—Time delay measurement, e.g. time-of-flight measurement, time of arrival measurement or determining the exact position of a peak
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- G01S7/00—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00
- G01S7/48—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S17/00
- G01S7/491—Details of non-pulse systems
- G01S7/4912—Receivers
- G01S7/4915—Time delay measurement, e.g. operational details for pixel components; Phase measurement
-
- G—PHYSICS
- G04—HOROLOGY
- G04F—TIME-INTERVAL MEASURING
- G04F10/00—Apparatus for measuring unknown time intervals by electric means
- G04F10/005—Time-to-digital converters [TDC]
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Computer Networks & Wireless Communication (AREA)
- Radar, Positioning & Navigation (AREA)
- Remote Sensing (AREA)
- Pulse Circuits (AREA)
Abstract
The invention discloses a high-precision low-kickback noise clock regeneration delay chain, which comprises: the voltage conversion module is connected with the voltage input end and used for converting the input signal into a first voltage signal and a second voltage signal; the delay chain module is connected with the voltage conversion module and the clock input end and used for controlling clock delay time according to the first voltage signal and the second voltage signal to obtain a first clock signal cluster and a second clock signal cluster; and the clock driving module is connected with the delay chain module and is used for receiving and processing the first clock signal cluster and the second clock signal cluster and outputting a multi-phase clock signal cluster. The clock regeneration delay chain provided by the invention has the capability of interference and clock regeneration, and can be suitable for high-precision system-level application.
Description
Technical Field
The invention belongs to the technical field of laser radar signal receiver systems, and particularly relates to a high-precision low-kickback-noise clock regeneration delay chain.
Background
The laser radar utilizes a laser transmitter to emit laser to irradiate on a detected object, laser echo reflected by a target object is received by an avalanche photodiode working in a linear mode and converted into a current signal, a front-end analog receiver linearly converts pulse current generated by the avalanche photodiode into a voltage signal, a time-to-digital conversion circuit is utilized to obtain flight time information of the pulse, or an analog-to-digital converter acquires amplitude of echo pulse, and finally the amplitude is provided for a subsequent digital signal processor to be further processed. In the time-to-digital conversion circuit, the delay chain phase-locked loop has wide application prospect.
The wide application of the delay chain phase-locked loop requires that the precision and the stability of the delay chain outputting the multi-phase clock are higher, and the interference of external environment noise or internal noise of the delay chain on the phase splitting precision is avoided. For some multi-delay chain systems, the consistency of delay time of different delay chains is required to be high under the same voltage, and the weak change of control voltage cannot generate huge interference on the delay chains; under different voltages, the delay chain is required to accurately generate stable delays with different delay times.
However, the conventional voltage-controlled delay unit does not have anti-interference capability and clock regeneration capability, the phase intervals of the output multiphase clocks are inconsistent, the duty ratio consistency is poor, the phase noise is high, the phase splitting precision is low, the voltage division ratio of similar delay time is low, the voltage division ratio is easily influenced by environmental noise, and the voltage-controlled delay unit cannot be applied to high-precision system-level applications such as a multi-line integrated chip and a high-resolution precision chip.
Disclosure of Invention
In order to solve the above problems in the prior art, the present invention provides a high-precision and low-kickback noise clock regeneration delay chain. The technical problem to be solved by the invention is realized by the following technical scheme:
a high precision low kickback noise clock regeneration delay chain comprising: the voltage conversion module is connected with the voltage input end and used for converting the input signal into a first voltage signal and a second voltage signal;
the delay chain module is connected with the voltage conversion module and the clock input end and used for controlling clock delay time according to the first voltage signal and the second voltage signal to obtain a first clock signal cluster and a second clock signal cluster;
and the clock driving module is connected with the delay chain module and is used for receiving and processing the first clock signal cluster and the second clock signal cluster and outputting a multi-phase clock signal cluster.
In one embodiment of the present invention, the delay chain module includes N cascaded delay chain basic units, and the delay chain basic units are connected to the voltage conversion module; wherein N is a positive integer.
In one embodiment of the present invention, the delay chain basic unit includes a low-pass filtering unit, a first delay sub-unit, a first clock regeneration sub-unit, a second delay sub-unit, and a second clock regeneration sub-unit, which are connected in series in sequence.
In one embodiment of the present invention, the low pass filtering subunit includes a first resistor R1 and a second resistor R2; wherein,
one end of the first resistor R1 is connected with the voltage conversion module, and the other end is connected with the first delay subunit and the second delay subunit;
one end of the second resistor R2 is connected to the voltage conversion module, and the other end is connected to the first delay subunit and the second delay subunit.
In one embodiment of the present invention, the first delay sub-unit includes transistors M1, M5, M6, M3 connected in series in this order to a power supply terminal VDD and a GND terminal; wherein,
the source of the transistor M1 is connected with a power supply VDD terminal, and the source of the transistor M3 is connected with a GND terminal;
the gate of the transistor M1 is connected with the voltage conversion module through the first resistor R1;
the gate of the transistor M3 is connected with the voltage conversion module through the second resistor R2;
the gates of the transistors M5 and M6 are connected with each other and are connected with a clock input end;
in one embodiment of the present invention, the first clock regeneration subunit includes transistors M7, M8, M9, M10; wherein,
the gate of the transistor M7 is connected with the common drain terminal of the transistors M5 and M6, and the source of the transistor M7 is connected with the VDD terminal;
the gate of the transistor M8 is connected with the gate of the transistor M7 and the common drain terminal of the transistors M5 and M6, the source of the transistor M8 is connected with the GND terminal, and the drain of the transistor M8 is connected with the drain of the transistor M7;
the gate of the transistor M9 is connected with the common drain terminal of the transistors M7 and M8, and the source of the transistor M9 is connected with the VDD terminal;
the gate of the transistor M10 is connected to the gate of the transistor M9 and to the common drain terminal of the transistors M7 and M8, the source of the transistor M10 is connected to the GND terminal, and the drain of the transistor M10 is connected to the drain of the transistor M9 and outputs the first clock signal as the output terminal of the first clock regeneration subunit.
In one embodiment of the present invention, the second delay sub-unit includes transistors M2, M11, M12, M4 connected in series to the power supply terminal VDD and the GND terminal in this order; wherein,
the source of the transistor M2 is connected with a power supply VDD terminal, and the source of the transistor M4 is connected with a GND terminal;
the gate of the transistor M2 is connected with the voltage conversion module through the first resistor R1;
the gate of the transistor M4 is connected with the voltage conversion module through the second resistor R2;
the gates of the transistors M11 and M12 are connected to each other and to the output terminal of the first clock regeneration subunit.
In one embodiment of the present invention, the second clock regeneration subunit includes transistors M13, M14, M15, M16; wherein,
the gate of the transistor M13 is connected with the common drain terminal of the transistors M11 and M12, and the source of the transistor M13 is connected with the VDD terminal;
the gate of the transistor M14 is connected with the gate of the transistor M13 and the common drain terminal of the transistors M11 and M12, the source of the transistor M14 is connected with the GND terminal, and the drain of the transistor M14 is connected with the drain of the transistor M13;
the gate of the transistor M15 is connected with the common drain terminal of the transistors M13 and M14, and the source of the transistor M15 is connected with the VDD terminal;
the gate of the transistor M16 is connected to the gate of the transistor M15 and to the common drain terminal of the transistors M13 and M14, the source of the transistor M16 is connected to the GND terminal, and the drain of the transistor M16 is connected to the drain of the transistor M15 and outputs the second clock signal as the output terminal of the second clock regeneration subunit.
In one embodiment of the invention, the transistors M1, M2, M5, M7, M9, M11, M13 and M15 are all PMOS transistors, and the transistors M3, M4, M6, M8, M10, M12, M14 and M16 are all NMOS transistors.
In an embodiment of the present invention, the clock driving module includes N clock driving units, and the N clock driving units are sequentially connected to the N delay chain basic units.
The invention has the beneficial effects that:
1. the clock regeneration delay chain provided by the invention adopts a method of embedding a low-pass filter, thereby reducing the kickback noise of a high-speed clock to a voltage control line, improving the voltage control capability of the voltage control line and ensuring the phase interval consistency of the generated multiphase clock;
2. according to the clock regeneration delay chain, the clock regeneration unit is adopted to adjust the voltage-controlled delay time and recover the clock duty ratio, so that the output clock of each voltage-controlled delay unit has certain clock delay and has steep rising edges and falling edges, and the duty ratio consistency of the multi-phase clock is ensured;
3. the clock regeneration delay chain provided by the invention is additionally provided with the clock regeneration unit, and the inherent delay of the delay chain unit is increased due to the inherent delay of the clock regeneration unit, so that the adjustment range of the voltage-controlled line can be correspondingly reduced to reach the same delay time, the precision of the voltage-controlled delay is effectively improved, the anti-noise performance of the voltage-controlled delay chain is improved, the voltage-controlled voltage change required by the same delay time difference is increased, and the clock regeneration delay chain is more suitable for a high-precision multi-chain delay chain phase-locked loop and a time digital detection system formed by the same.
The present invention will be described in further detail with reference to the accompanying drawings and examples.
Drawings
Fig. 1 is a schematic diagram of a high-precision low-kickback-noise clock regenerative delay chain structure according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of another high-precision low-kickback noise clock regeneration delay chain structure according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a basic unit structure of a delay chain according to an embodiment of the present invention;
FIG. 4 is an equivalent circuit diagram of a low pass filter provided by an embodiment of the invention;
fig. 5 is a schematic diagram of the delay module building basic delay unit outputting multi-phase clock pulse contraction provided by the embodiment of the invention;
FIG. 6 is a schematic diagram illustrating waveforms of the CLK signal delayed by the basic delay unit according to an embodiment of the present invention;
fig. 7 is a diagram comparing the delay effect of the conventional delay chain and the present invention.
Detailed Description
The present invention will be described in further detail with reference to specific examples, but the embodiments of the present invention are not limited thereto.
Example one
Referring to fig. 1, fig. 1 is a schematic diagram of a high-precision low-kickback noise clock regeneration delay chain structure according to an embodiment of the present invention, including:
the voltage conversion module is connected with the voltage input end and used for converting the input signal into a first voltage signal and a second voltage signal;
the delay chain module is connected with the voltage conversion module and the clock input end and used for controlling clock delay time according to the first voltage signal and the second voltage signal to obtain a first clock signal cluster and a second clock signal cluster;
and the clock driving module is connected with the delay chain module and is used for receiving and processing the first clock signal cluster and the second clock signal cluster and outputting a multi-phase clock signal cluster.
In this embodiment, the voltage input signal VCTR is connected to the input terminal of the voltage conversion module as a control signal of the whole delay chain delay time, and the voltage conversion module converts the VCTR signal into the control signal VBP and the control signal VBN, that is, the first voltage signal and the second voltage signal, and outputs the control signal VBP and the control signal VBN to the delay chain module to control the specific delay time of the delay chain module.
Referring to fig. 2, fig. 2 is a schematic diagram of another high-precision low-kickback noise clock regeneration delay chain structure according to an embodiment of the present invention.
In this embodiment, the delay chain module includes N cascaded delay chain basic units, and each of the delay chain basic units is connected to the voltage conversion module; wherein N is a positive integer. The control signals VBP and VBN are input signals, connected to each delay chain basic unit, as delay time control signals specific to the delay chain basic unit, which outputs N DCLK signals and N OCLK signals, that is, a first clock signal cluster and a second clock signal cluster. The CLK signal is coupled as an input signal to the first delay chain basic unit. The output signals of the delay chain basic units are connected to a clock driving module, correspondingly, the clock driving module comprises N clock driving units, and the N clock driving units are sequentially connected with the N delay chain basic units.
In this embodiment, the OCLK signal of the first delay chain basic unit is used as an output signal and is connected to the second delay unit and the first clock driving module; the DCLK signal of the first delay chain basic unit is also used as an output signal and is connected to the first clock driving module.
In the same way, the OCLK signal of the N-1 th delay chain basic unit is used as an output signal and is connected to the N-1 th delay unit and the N-1 th clock driving module; the DCLK signal of the N-1 th delay chain base unit is also coupled as an output signal to the N-1 th clock driving block.
The OCLK signal of the Nth delay chain basic unit is used as an output signal and is connected to the Nth clock driving module; the DCLK signal of the nth delay chain basic unit is also connected as an output signal to the nth clock driving module.
And finally, the output signals of the first to Nth clock driving modules are N-phase clock signal clusters.
Referring to fig. 3, fig. 3 is a schematic diagram of a basic unit structure of a delay chain according to an embodiment of the present invention, where the basic unit of the delay chain includes a low-pass filtering subunit 211, a first delay subunit 212, a first clock regeneration subunit 213, a second delay subunit 214, and a second clock regeneration subunit 215, which are sequentially connected in series.
In this embodiment, the low pass filtering subunit 211 includes a first resistor R1 and a second resistor R2; one end of the first resistor R1 is connected to the voltage conversion module, and the other end is connected to the first delay subunit 212 and the second delay subunit 214;
one end of the second resistor R2 is connected to the voltage conversion module, and the other end is connected to the first delay subunit 212 and the second delay subunit 214.
In the present embodiment, the first delay subunit 212 includes transistors M1, M5, M6, M3 connected in series to the power supply terminals VDD and GND in this order; the transistors M1 and M5 are PMOS tubes, and the transistors M6 and M3 are NMOS tubes;
the source of the transistor M1 is connected with a power supply VDD terminal, and the source of the transistor M3 is connected with a GND terminal;
the gate of the transistor M1 is connected with the voltage conversion module through the first resistor R1;
the gate of the transistor M3 is connected with the voltage conversion module through the second resistor R2;
the gates of the transistors M5 and M6 are connected to each other and to the clock input.
In the present embodiment, the first delay subunit mainly plays a role of delay, and the principle is that M3 and M1 are used as current sources to control the maximum current for charging and discharging the node a in fig. 3, so as to delay the rising (falling) speed of the rising edge (falling edge) of the a node signal, thereby playing a role of delay.
In a conventional voltage-controlled delay chain, a voltage-controlled line controls the charging and discharging current of a MOS transistor. The gate source, the gate drain and the gate liner capacitor of the MOS transistor have a path for high-frequency signals, and for large-swing signals such as clock signals, kickback noise is easily generated by capacitive coupling to influence voltage-controlled voltage, and the phenomenon is particularly obvious under the conditions of cascade connection of a plurality of delay units and a plurality of delay chains. In addition, because the length of the delay line is long, a plurality of other circuit modules are likely to pass through, cross over and bypass in actual production, and therefore the delay line is extremely susceptible to noise generated by other modules.
In the embodiment, the low-pass filter is introduced between the noise source and the voltage control line, so that the influence of the high-frequency clock signal on the voltage control line is reduced, and the phase interval consistency of the generated multiphase clock is ensured.
Referring to fig. 4, fig. 4 is an equivalent circuit diagram of a low pass filter according to an embodiment of the invention; in the figure, RoutRepresenting the output impedance of a voltage-controlled MOS transistor, CgsRepresenting the gate capacitance of the voltage-controlled MOS transistor, C representing the output capacitance of the voltage conversion module, RloadRepresenting the output resistance, R representing the introduced filter resistance, and when this resistance is not introduced, the noise current I generated by the noise current sourcenoiseThe voltage response generated on the voltage control line can be expressed as:
when a low-pass filter capacitor is introduced, the voltage response of the noise current generated by the noise current source on the voltage control line can be expressed as:
considering the actual parameters of the two voltage response expressions and comparing them, it can be seen that the introduced low-pass filter reduces the high-frequency noise response by a factor of about (sggsr + 1).
In the present embodiment, the first clock regeneration subunit 213 includes transistors M7, M8, M9, M10; the transistors M7 and M9 are PMOS tubes, and the transistors M8 and M10 are NMOS tubes;
the gate of the transistor M7 is connected with the common drain terminal of the transistors M5 and M6, and the source of the transistor M7 is connected with the VDD terminal;
the gate of the transistor M8 is connected with the gate of the transistor M7 and the common drain terminal of the transistors M5 and M6, the source of the transistor M8 is connected with the GND terminal, and the drain of the transistor M8 is connected with the drain of the transistor M7;
the gate of the transistor M9 is connected with the common drain terminal of the transistors M7 and M8, and the source of the transistor M9 is connected with the VDD terminal;
the gate of the transistor M10 is connected to the gate of the transistor M9 and to the common drain of the transistors M7 and M8, the source of the transistor M10 is connected to the GND terminal, and the drain of the transistor M10 is connected to the drain of the transistor M9 and outputs the first clock signal, i.e., the DCLK signal, as the output terminal of the first clock regeneration subunit.
In this embodiment, the N first clock signals output by the N cascaded delay chain basic units are the first clock signal cluster.
In a traditional delay chain, a basic delay unit is mainly built by a delay module, and after a signal passes through the unit, the output rising edge and the output falling edge are both slowed down; if the cascade count increases, the final output signal may start to fall when it rises to VDD, causing duty cycle degradation; if the cascade count continues to increase, the duty cycle continues to deteriorate, eventually resulting in the signal failing to effectively flip, i.e., the duty cycle is 0. Referring to fig. 5, fig. 5 is a schematic diagram of the delay module building a basic delay unit to output multi-phase clock pulse contraction according to an embodiment of the present invention.
In the embodiment, the clock regeneration unit is added, so that the clock duty ratio is recovered while the voltage-controlled delay time is adjusted, the output clock of each voltage-controlled delay unit has certain clock delay and has steep rising edges and falling edges, and the duty ratio consistency of the multi-phase clock is ensured.
The clock regeneration unit records only the delay time by charging and discharging an unlimited inverter group, and recovers the rising and falling speeds of the clock. Taking the rising edge of the CLK signal as an example, please refer to fig. 6, where fig. 6 is a schematic diagram of a signal waveform of the CLK signal delayed by the basic delay unit according to the embodiment of the present invention; after the CLK signal is delayed and inverted by the first delay subunit, point a in fig. 3 becomes a falling edge, and the discharge current of the point a signal is limited, so that the falling edge of the point a signal is slowed down; thereby achieving the purpose of delay. After passing through the first clock regeneration subunit, the charging and discharging current is not controlled by a current source, so that the signal waveforms of the node B and the node C can be established most quickly, and the clock duty ratio is recovered.
In the present embodiment, the second delay subunit 214 includes transistors M2, M11, M12, M4 connected in series to the power supply terminals VDD and GND in this order; the transistors M2 and M11 are PMOS tubes, and the transistors M12 and M4 are NMOS tubes;
the source of the transistor M2 is connected with a power supply VDD terminal, and the source of the transistor M4 is connected with a GND terminal;
the gate of the transistor M2 is connected with the voltage conversion module through the first resistor R1;
the gate of the transistor M4 is connected with the voltage conversion module through the second resistor R2;
the gates of the transistors M11 and M12 are connected to each other and to the output terminal of the first clock regeneration subunit.
The second clock regeneration subunit 215 includes transistors M13, M14, M15, M16; the transistors M13 and M15 are PMOS tubes, and the transistors M14 and M16 are NMOS tubes;
the gate of the transistor M13 is connected with the common drain terminal of the transistors M11 and M12, and the source of the transistor M13 is connected with the VDD terminal;
the gate of the transistor M14 is connected with the gate of the transistor M13 and the common drain terminal of the transistors M11 and M12, the source of the transistor M14 is connected with the GND terminal, and the drain of the transistor M14 is connected with the drain of the transistor M13;
the gate of the transistor M15 is connected with the common drain terminal of the transistors M13 and M14, and the source of the transistor M15 is connected with the VDD terminal;
the gate of the transistor M16 is connected to the gate of the transistor M15 and to the common drain of the transistors M13 and M14, the source of the transistor M16 is connected to GND, and the drain of the transistor M16 is connected to the drain of the transistor M15 and outputs the second clock signal, i.e., the OCLK signal, as the output terminal of the second clock regeneration subunit.
In this embodiment, the N second clock signals output by the N cascaded delay chain basic units are the second clock signal cluster.
The working principle of the second delay subunit and the second clock regeneration subunit is the same as that of the first delay subunit and the first clock regeneration subunit, and details are not repeated here.
Referring to fig. 7, fig. 7 is a diagram comparing the delay effect of the conventional delay chain and the delay effect of the present invention according to the embodiment of the present invention. In this embodiment, due to the inherent delay of the introduced clock regeneration unit, the inherent delay of the delay chain unit is increased, so that the adjustment range of the voltage-controlled line can be correspondingly reduced to reach the same delay time, which effectively improves the precision of the voltage-controlled delay, improves the anti-noise performance of the voltage-controlled delay chain, and ensures that the voltage-controlled voltage change required by the same delay time difference is increased, thereby being more suitable for a high-precision multi-chain delay chain phase-locked loop and a time digital detection system formed by the same.
The foregoing is a more detailed description of the invention in connection with specific preferred embodiments and it is not intended that the invention be limited to these specific details. For those skilled in the art to which the invention pertains, several simple deductions or substitutions can be made without departing from the spirit of the invention, and all shall be considered as belonging to the protection scope of the invention.
Claims (7)
1. A high accuracy low kickback noise clock regenerative delay chain, comprising:
the voltage conversion module is connected with the voltage input end and used for converting the input signal into a first voltage signal and a second voltage signal;
the delay chain module is connected with the voltage conversion module and the clock input end and used for controlling clock delay time according to the first voltage signal and the second voltage signal to obtain a first clock signal cluster and a second clock signal cluster; the delay chain module comprises N cascaded delay chain basic units, and the delay chain basic units are connected with the voltage conversion module; wherein N is a positive integer; the delay chain basic unit comprises a low-pass filtering subunit, a first delay subunit, a first clock regeneration subunit, a second delay subunit and a second clock regeneration subunit which are sequentially connected in series;
the low-pass filtering subunit comprises a first resistor R1 and a second resistor R2; wherein,
one end of the first resistor R1 is connected with the voltage conversion module, and the other end is connected with the first delay subunit and the second delay subunit;
one end of the second resistor R2 is connected with the voltage conversion module, and the other end is connected with the first delay subunit and the second delay subunit;
and the clock driving module is connected with the delay chain module and is used for receiving and processing the first clock signal cluster and the second clock signal cluster and outputting a multi-phase clock signal cluster.
2. The clock regenerative delay chain of claim 1, wherein the first delay sub-unit comprises transistors M1, M5, M6, M3 connected in series in sequence to a power supply terminal VDD and a GND terminal; wherein,
the source of the transistor M1 is connected with a power supply VDD terminal, and the source of the transistor M3 is connected with a GND terminal;
the gate of the transistor M1 is connected with the voltage conversion module through the first resistor R1;
the gate of the transistor M3 is connected with the voltage conversion module through the second resistor R2;
the gates of the transistors M5 and M6 are connected to each other and to the clock input.
3. The clock regenerative delay chain of claim 2, wherein the first clock regenerative subunit comprises transistors M7, M8, M9, M10; wherein,
the gate of the transistor M7 is connected with the common drain terminal of the transistors M5 and M6, and the source of the transistor M7 is connected with the VDD terminal;
the gate of the transistor M8 is connected with the gate of the transistor M7 and the common drain terminal of the transistors M5 and M6, the source of the transistor M8 is connected with the GND terminal, and the drain is connected with the drain of the transistor M7;
the gate of the transistor M9 is connected with the common drain terminal of the transistors M7 and M8, and the source of the transistor M9 is connected with the VDD terminal;
the gate of the transistor M10 is connected to the gate of the transistor M9 and to the common drain terminal of the transistors M7 and M8, the source of the transistor M10 is connected to the GND terminal, and the drain of the transistor M10 is connected to the drain of the transistor M9 and outputs the first clock signal as the output terminal of the first clock regeneration subunit.
4. The clock regenerative delay chain of claim 3, wherein the second delay sub-unit comprises transistors M2, M11, M12, M4 connected in series in sequence to a power supply terminal VDD and a GND terminal; wherein,
the source of the transistor M2 is connected with a power supply VDD terminal, and the source of the transistor M4 is connected with a GND terminal;
the gate of the transistor M2 is connected with the voltage conversion module through the first resistor R1;
the gate of the transistor M4 is connected with the voltage conversion module through the second resistor R2;
the gates of the transistors M11 and M12 are connected to each other and to the output terminal of the first clock regeneration subunit.
5. The clock regenerative delay chain of claim 4, wherein the second clock regenerative subunit comprises transistors M13, M14, M15, M16; wherein,
the gate of the transistor M13 is connected with the common drain terminal of the transistors M11 and M12, and the source of the transistor M13 is connected with the VDD terminal;
the gate of the transistor M14 is connected with the gate of the transistor M13 and the common drain terminal of the transistors M11 and M12, the source of the transistor M14 is connected with the GND terminal, and the drain of the transistor M14 is connected with the drain of the transistor M13;
the gate of the transistor M15 is connected with the common drain terminal of the transistors M13 and M14, and the source of the transistor M15 is connected with the VDD terminal;
the gate of the transistor M16 is connected to the gate of the transistor M15 and to the common drain terminal of the transistors M13 and M14, the source of the transistor M16 is connected to the GND terminal, and the drain of the transistor M16 is connected to the drain of the transistor M15 and outputs the second clock signal as the output terminal of the second clock regeneration subunit.
6. The clock regeneration delay chain of claim 5, wherein the transistors M1, M2, M5, M7, M9, M11, M13 and M15 are all PMOS transistors, and the transistors M3, M4, M6, M8, M10, M12, M14 and M16 are all NMOS transistors.
7. The clock regenerative delay chain of claim 1, wherein the clock driver module comprises N clock driver units, the N clock driver units being sequentially connected to N delay chain base units.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910759880.3A CN110673113B (en) | 2019-08-16 | 2019-08-16 | High-precision low-kickback-noise clock regeneration delay chain |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910759880.3A CN110673113B (en) | 2019-08-16 | 2019-08-16 | High-precision low-kickback-noise clock regeneration delay chain |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN110673113A CN110673113A (en) | 2020-01-10 |
| CN110673113B true CN110673113B (en) | 2021-08-10 |
Family
ID=69075366
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910759880.3A Active CN110673113B (en) | 2019-08-16 | 2019-08-16 | High-precision low-kickback-noise clock regeneration delay chain |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN110673113B (en) |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1507156A (en) * | 2002-12-06 | 2004-06-23 | ���µ�����ҵ��ʽ���� | Duty ratio correction circuit |
| CN104467819A (en) * | 2014-07-08 | 2015-03-25 | 北京芯诣世纪科技有限公司 | Delay-locked loop, voltage-controlled delay line and delay unit |
| CN104702269A (en) * | 2013-12-10 | 2015-06-10 | 精工爱普生株式会社 | Detection device, sensor, electronic apparatus and moving object |
| CN106849942A (en) * | 2016-12-29 | 2017-06-13 | 北京时代民芯科技有限公司 | A kind of ultrahigh speed low jitter multiphase clock circuit |
| CN107565934A (en) * | 2016-06-30 | 2018-01-09 | 无锡华润上华科技有限公司 | Annular voltage controlled oscillator and phaselocked loop |
| CN107797442A (en) * | 2017-11-08 | 2018-03-13 | 安凯(广州)微电子技术有限公司 | Time-to-digital conversion apparatus and digital phase-locked loop |
| CN107888171A (en) * | 2017-11-16 | 2018-04-06 | 上海北京大学微电子研究院 | A kind of high speed is low to recalcitrate noise dynamic comparer and circuit |
| CN109696821A (en) * | 2018-12-14 | 2019-04-30 | 中国科学技术大学 | Two-stage digital time converter |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101818505B1 (en) * | 2011-07-11 | 2018-01-15 | 삼성전자 주식회사 | Duty ratio recover circuit |
-
2019
- 2019-08-16 CN CN201910759880.3A patent/CN110673113B/en active Active
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1507156A (en) * | 2002-12-06 | 2004-06-23 | ���µ�����ҵ��ʽ���� | Duty ratio correction circuit |
| CN104702269A (en) * | 2013-12-10 | 2015-06-10 | 精工爱普生株式会社 | Detection device, sensor, electronic apparatus and moving object |
| CN104467819A (en) * | 2014-07-08 | 2015-03-25 | 北京芯诣世纪科技有限公司 | Delay-locked loop, voltage-controlled delay line and delay unit |
| CN107565934A (en) * | 2016-06-30 | 2018-01-09 | 无锡华润上华科技有限公司 | Annular voltage controlled oscillator and phaselocked loop |
| CN106849942A (en) * | 2016-12-29 | 2017-06-13 | 北京时代民芯科技有限公司 | A kind of ultrahigh speed low jitter multiphase clock circuit |
| CN107797442A (en) * | 2017-11-08 | 2018-03-13 | 安凯(广州)微电子技术有限公司 | Time-to-digital conversion apparatus and digital phase-locked loop |
| CN107888171A (en) * | 2017-11-16 | 2018-04-06 | 上海北京大学微电子研究院 | A kind of high speed is low to recalcitrate noise dynamic comparer and circuit |
| CN109696821A (en) * | 2018-12-14 | 2019-04-30 | 中国科学技术大学 | Two-stage digital time converter |
Non-Patent Citations (3)
| Title |
|---|
| A 10-KS/s 625-Hz-Bandwidth 60-dB SNDR Noise-Shaping ADC for Bio-potential Signals Detection Application;Jin Hu 等;《2018 IEEE Asia Pacific Conference on Circuits and Systems》;20190210;第46-49页 * |
| FPGA中基于DLL的时钟网络的设计;李亮;《中国优秀硕士学位论文全文数据库 信息科技辑》;20090115(第01期);正文全文 * |
| 一种具有延迟校准功能的可编程多相位时钟电路;刘术彬 等;《西安电子科技大学学报（自然科学版）》;20141231;第41卷(第6期);第57-63页 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN110673113A (en) | 2020-01-10 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9048820B2 (en) | High-speed fully-differential clock duty cycle calibration circuit | |
| US9054681B2 (en) | High speed duty cycle correction and double to single ended conversion circuit for PLL | |
| US7522084B2 (en) | Cycle time to digital converter | |
| US9973178B1 (en) | Method and apparatus for clock frequency multiplier | |
| US8884676B2 (en) | Clock generator with duty cycle control and method | |
| CN110957998A (en) | Circuit for accurately correcting duty ratio of clock signal | |
| CN100533984C (en) | Duty-ratio calibrating circuit for flow-line modulus converter | |
| CN108199699B (en) | Clock circuit with stable duty ratio and low jitter | |
| KR20120005013A (en) | Techniques for non-overlapping clock generation | |
| US7548104B2 (en) | Delay line with delay cells having improved gain and in built duty cycle control and method thereof | |
| CN104753499B (en) | Duty ratio calibrating circuit | |
| CN202103633U (en) | Analog-digital mixed clock duty cycle calibration circuit | |
| CN102347767A (en) | Digital-analog hybrid mode clock duty ratio calibration circuit | |
| CN106160462B (en) | A kind of charge pump system that driving capability is stablized | |
| US20090251186A1 (en) | Semiconductor integrated circuit | |
| JP3761858B2 (en) | Clock signal generation circuit | |
| CN1577611A (en) | Delay locked loop (dll) circuit and method for locking clock delay by using the same | |
| CN103595413B (en) | A kind of time domain comparer for gradually-appoximant analog-digital converter | |
| CN110673113B (en) | High-precision low-kickback-noise clock regeneration delay chain | |
| US5367204A (en) | Multiple digital clock edge generator circuit and method | |
| CN116707497B (en) | Tunable low-speed clock duty cycle skew trimming circuit, method and timing circuit | |
| CN110808737B (en) | Digital correction method for delay chain circuit of asynchronous SAR-ADC | |
| CN108011619A (en) | A kind of pulse pattern generator | |
| CN102035527A (en) | Offset voltage elimination technology for differential time domain comparator | |
| US6025747A (en) | Logic signal selection circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |