CN110673113B - High-precision low-kickback-noise clock regeneration delay chain - Google Patents

Abstract

The invention discloses a clock regeneration delay chain with high precision and low kickback noise, comprising: a voltage conversion module connected to a voltage input terminal for converting an input signal into a first voltage signal and a second voltage signal; connecting the voltage conversion module and the clock input terminal, and controlling the clock delay time according to the first voltage signal and the second voltage signal to obtain the first clock signal cluster and the second clock signal cluster; the clock driving module is connected to the The delay chain module is configured to receive and process the first clock signal cluster and the second clock signal cluster, and output a multi-phase clock signal cluster. The clock regeneration delay chain provided by the present invention has the ability of interference and clock regeneration, and can be adapted to the application of high precision system level.

Description

A Clock Regeneration Delay Chain with High Precision and Low Kickback Noise

technical field

The invention belongs to the technical field of laser radar signal receiver systems, in particular to a clock regeneration delay chain with high precision and low kickback noise.

Background technique

The laser radar uses the laser transmitter to emit laser light on the object to be detected, and the laser echo reflected by the target object is received by the avalanche photodiode operating in linear mode and converted into a current signal, and then the front-end analog receiver converts the avalanche photoelectric The pulse current generated by the diode is linearly converted into a voltage signal, and then the time-of-flight information of the pulse is obtained by the time-to-digital conversion circuit, or the amplitude of the echo pulse is collected by the analog-to-digital converter, and finally provided to the subsequent digital signal processor for processing. further processing. In the time-to-digital conversion circuit, the delay chain phase-locked loop has a wide application prospect.

The wide application of the delay chain phase-locked loop requires higher precision and stability of the output multi-phase clock of the delay chain, avoiding the interference of external environmental noise or internal noise of the delay chain on its phase separation accuracy. For some multi-delay chain systems, under the same voltage, the delay time consistency of different delay chains is required to be high, and the slight change of the control voltage will not cause great interference to the delay chain; under different voltages, the delay chain is required to accurately generate different delays Stable delay in time.

However, the traditional voltage-controlled delay unit does not have the anti-interference ability and clock regeneration ability, and the phase interval of the output multi-phase clock is inconsistent, the duty cycle consistency is poor, the phase noise is high, the phase separation accuracy is low, and the voltage discrimination degree of the similar delay time is low. , it is easily affected by environmental noise, and cannot adapt to high-precision system-level applications such as multi-line integrated chips and high-resolution precision chips.

SUMMARY OF THE INVENTION

In order to solve the above problems in the prior art, the present invention provides a clock regeneration delay chain with high precision and low kickback noise. The technical problem to be solved by the present invention is realized by the following technical solutions:

A clock regeneration delay chain with high precision and low kickback noise, comprising: a voltage conversion module connected to a voltage input terminal for converting an input signal into a first voltage signal and a second voltage signal;

a delay chain module, connected to the voltage conversion module and the clock input terminal, and configured to control the clock delay time according to the first voltage signal and the second voltage signal to obtain a first clock signal cluster and a second clock signal cluster;

A clock driving module, connected to the delay chain module, is configured to receive and process the first clock signal cluster and the second clock signal cluster, and output a multi-phase clock signal cluster.

In an embodiment of the present invention, the delay chain module includes N cascaded delay chain basic units, and the delay chain basic units are all connected to the voltage conversion module; wherein, N is a positive integer.

In an embodiment of the present invention, the basic unit of the delay chain includes a low-pass filtering unit, a first delay subunit, a first clock regeneration subunit, a second delay subunit, and a second clock regeneration subunit, which are connected in series in sequence.

In an embodiment of the present invention, the low-pass filter subunit includes a first resistor R1 and a second resistor R2; wherein,

One end of the first resistor R1 is connected to the voltage conversion module, and the other end is connected to the first delay subunit and the second delay subunit;

One end of the second resistor R2 is connected to the voltage conversion module, and the other end is connected to the first delay subunit and the second delay subunit.

In an embodiment of the present invention, the first delay subunit includes transistors M1, M5, M6, and M3 serially connected to the power supply terminal VDD and the GND terminal in sequence; wherein,

The source of the transistor M1 is connected to the power supply VDD terminal, and the source of the transistor M3 is connected to the GND terminal;

The gate of the transistor M1 is connected to the voltage conversion module through the first resistor R1;

The gate of the transistor M3 is connected to the voltage conversion module through the second resistor R2;

The gates of the transistors M5 and M6 are connected to each other and connected to the clock input;

In an embodiment of the present invention, the first clock regeneration subunit includes transistors M7, M8, M9, and M10; wherein,

The gate of the transistor M7 is connected to the drain common terminal of the transistors M5 and M6, and the source of the transistor M7 is connected to the power supply VDD terminal;

The gate of the transistor M8 is connected to the gate of the transistor M7 and is connected to the common drain of the transistors M5 and M6, the source of the transistor M8 is connected to the GND terminal, and the drain of the transistor M8 is connected to the the drain of transistor M7;

The gate of the transistor M9 is connected to the drain common terminal of the transistors M7 and M8, and the source of the transistor M9 is connected to the power supply VDD terminal;

The gate of the transistor M10 is connected to the gate of the transistor M9 and is connected to the common drain of the transistors M7 and M8, the source of the transistor M10 is connected to the GND terminal, and the drain of the transistor M10 is connected to the The drain of the transistor M9 is used as the output terminal of the first clock regeneration subunit to output the first clock signal.

In an embodiment of the present invention, the second delay subunit includes transistors M2, M11, M12, and M4 serially connected to the power supply terminal VDD and the GND terminal in sequence; wherein,

The source of the transistor M2 is connected to the power supply VDD terminal, and the source of the transistor M4 is connected to the GND terminal;

The gate of the transistor M2 is connected to the voltage conversion module through the first resistor R1;

The gate of the transistor M4 is connected to the voltage conversion module through the second resistor R2;

The gates of the transistors M11 and M12 are connected to each other and to the output terminal of the first clock regeneration subunit.

In an embodiment of the present invention, the second clock regeneration subunit includes transistors M13, M14, M15, and M16; wherein,

The gate of the transistor M13 is connected to the drain common terminal of the transistors M11 and M12, and the source of the transistor M13 is connected to the power supply VDD terminal;

The gate of the transistor M14 is connected to the gate of the transistor M13 and is connected to the common drain of the transistors M11 and M12, the source of the transistor M14 is connected to the GND terminal, and the drain of the transistor M14 is connected to the the drain of transistor M13;

The gate of the transistor M15 is connected to the common drain of the transistors M13 and M14, and the source of the transistor M15 is connected to the power supply VDD;

The gate of the transistor M16 is connected to the gate of the transistor M15 and is connected to the common drain of the transistors M13 and M14, the source of the transistor M16 is connected to the GND terminal, and the drain of the transistor M16 is connected to the The drain of the transistor M15 is used as the output terminal of the second clock regeneration subunit to output the second clock signal.

In an embodiment of the present invention, the transistors M1, M2, M5, M7, M9, M11, M13, and M15 are all PMOS transistors, and the transistors M3, M4, M6, M8, M10, M12, M14, M16 Both are NMOS transistors.

In an embodiment of the present invention, the clock driving module includes N clock driving units, and the N clock driving units shown are sequentially connected to the N delay chain basic units.

Beneficial effects of the present invention:

1. The clock regeneration delay chain provided by the present invention adopts the method of embedding a low-pass filter, which reduces the kickback noise of the high-speed clock to the voltage control line, improves the voltage control ability of the voltage control line, and ensures the multi-phase generated. Clock phase interval consistency;

2. The clock regeneration delay chain provided by the present invention adopts the clock regeneration unit to restore the clock duty ratio while adjusting the voltage-controlled delay time, so that the output clock of each voltage-controlled delay unit has a certain clock delay and a steep rise at the same time. edge and falling edge, thus ensuring the consistency of the duty cycle of the multi-phase clock;

3. The clock regeneration delay chain provided by the present invention adds a clock regeneration unit. Due to the inherent delay of the clock regeneration unit, the inherent delay of the delay chain unit increases, so that the adjustment range of the voltage control line can be correspondingly reduced to reach the same delay. time, which effectively improves the accuracy of the voltage-controlled delay, improves the anti-noise performance of the voltage-controlled delay chain, and ensures that the voltage-controlled voltage change required for the same delay time difference increases, which is more suitable for high-precision, multi-chain delay chains. Phase-locked loop and its time digital detection system.

The present invention will be further described in detail below with reference to the accompanying drawings and embodiments.

Description of drawings

1 is a schematic structural diagram of a clock regeneration delay chain with high precision and low kickback noise provided by an embodiment of the present invention;

2 is a schematic structural diagram of another clock regeneration delay chain with high precision and low kickback noise provided by an embodiment of the present invention;

3 is a schematic structural diagram of a basic unit of a delay chain provided by an embodiment of the present invention;

4 is an equivalent circuit diagram of a low-pass filter provided by an embodiment of the present invention;

FIG. 5 is a schematic diagram of outputting multi-phase clock pulse contraction of a basic delay unit constructed by a delay module according to an embodiment of the present invention;

6 is a schematic diagram of a signal waveform of a CLK signal after being delayed by a basic delay unit provided by an embodiment of the present invention;

FIG. 7 is a comparison diagram of the delay effect of a conventional delay chain provided by an embodiment of the present invention and the present invention.

Detailed ways

The present invention will be described in further detail below with reference to specific embodiments, but the embodiments of the present invention are not limited thereto.

Example 1

Please refer to FIG. 1. FIG. 1 is a schematic structural diagram of a clock regeneration delay chain with high precision and low kickback noise provided by an embodiment of the present invention, including:

a voltage conversion module, connected to the voltage input terminal, for converting the input signal into a first voltage signal and a second voltage signal;

a delay chain module, connected to the voltage conversion module and the clock input terminal, and configured to control the clock delay time according to the first voltage signal and the second voltage signal to obtain a first clock signal cluster and a second clock signal cluster;

A clock driving module, connected to the delay chain module, is configured to receive and process the first clock signal cluster and the second clock signal cluster, and output a multi-phase clock signal cluster.

In this embodiment, the voltage input signal VCTR is connected to the input terminal of the voltage conversion module. As a control signal for the delay time of the entire delay chain, the voltage conversion module converts the VCTR signal into the control signal VBP and the control signal VBN, that is, the first voltage The signal and the second voltage signal are output to the delay chain module to control the specific delay time of the delay chain module.

Referring to FIG. 2, FIG. 2 is a schematic structural diagram of another clock regeneration delay chain with high precision and low kickback noise provided by an embodiment of the present invention.

In this embodiment, the delay chain module includes N cascaded delay chain basic units, and the delay chain basic units are all connected to the voltage conversion module; wherein, N is a positive integer. The control signals VBP and VBN are used as input signals and are connected to each delay chain basic unit. As the specific delay time control signal of the delay chain basic unit, the delay chain basic unit outputs N DCLK signals and N OCLK signals, that is, the first clock A signal cluster and a second clock signal cluster. The CLK signal is used as an input signal to connect to the first delay chain base unit. The output signal of the delay chain basic unit is connected to the clock driving module. Correspondingly, the clock driving module includes N clock driving units, and the N clock driving units shown are connected to the N delay chain basic units in sequence.

In this embodiment, the OCLK signal of the first delay chain basic unit is used as an output signal and is connected to the second delay unit and the first clock driving module; the DCLK signal of the first delay chain basic unit is also used as an output signal and is connected to the first clock driving module. a clock drive module.

By analogy, the OCLK signal of the N-1th delay chain basic unit is used as an output signal, which is connected to the Nth delay unit and the N-1th clock driving module; the DCLK signal of the N-1th delay chain basic unit is also used as an output signal. , connected to the N-1th clock driver module.

The OCLK signal of the Nth delay chain basic unit is used as an output signal and connected to the Nth clock driving module; the DCLK signal of the Nth delay chain basic unit is also used as an output signal and connected to the Nth clock driving module.

Finally, the output signals of the first to Nth clock driving modules are N-phase clock signal clusters.

Please refer to FIG. 3. FIG. 3 is a schematic structural diagram of a basic unit of a delay chain provided by an embodiment of the present invention. The basic unit of the delay chain includes a low-pass filter subunit 211, a first delay subunit 212, and a first clock regeneration subunit that are connected in series in sequence. unit 213 , second delay subunit 214 and second clock regeneration subunit 215 .

In this embodiment, the low-pass filter subunit 211 includes a first resistor R1 and a second resistor R2; wherein, one end of the first resistor R1 is connected to the voltage conversion module, and the other end is connected to the first delay subunit 212 and the second delay subunit 214;

One end of the second resistor R2 is connected to the voltage conversion module, and the other end is connected to the first delay subunit 212 and the second delay subunit 214 .

In this embodiment, the first delay subunit 212 includes transistors M1, M5, M6, and M3 serially connected to the power supply terminal VDD and the GND terminal in sequence; wherein, the transistors M1 and M5 are PMOS transistors, and the transistor M6 , M3 is NMOS tube;

The source of the transistor M1 is connected to the power supply VDD terminal, and the source of the transistor M3 is connected to the GND terminal;

The gate of the transistor M1 is connected to the voltage conversion module through the first resistor R1;

The gate of the transistor M3 is connected to the voltage conversion module through the second resistor R2;

The gates of the transistors M5 and M6 are connected to each other and to the clock input.

In this embodiment, the first delay subunit mainly plays a delay role. The principle is that M3 and M1 act as current sources to control the maximum current for charging and discharging node A in FIG. 3 , thereby delaying the rising edge of the node A signal. (falling edge) rising (falling) speed, thus acting as a delay.

The traditional voltage-controlled delay chain controls the charge and discharge current of the MOS tube by the voltage-controlled line. The gate-source, gate-drain, and gate-liner capacitance of the MOS transistor have paths for high-frequency signals, and for large-swing signals such as clock signals, it is easy to cause capacitive coupling to produce kickback noise, which affects the voltage control. voltage, this phenomenon is especially obvious when multiple delay cells are cascaded and multiple delay chains are used. In addition, due to the long length of the delay line, it is likely to pass, cross, and bypass multiple other circuit modules in actual production, so it is highly susceptible to noise generated by other modules.

In this embodiment, by introducing a low-pass filter between the noise source and the voltage control line, the influence of the high frequency clock signal on the voltage control line is reduced, and the phase interval consistency of the generated multiphase clock is ensured.

Please refer to FIG. 4, which is an equivalent circuit diagram of a low-pass filter provided by an embodiment of the present invention; in the figure, R _out represents the output impedance of the voltage-controlled MOS transistor, C _gs represents the gate capacitance of the voltage-controlled MOS transistor, and C represents the voltage The output capacitance of the conversion module, R _load represents the output resistance, and R represents the introduced filter resistance. When the resistance is not introduced, the voltage response generated by the noise current I _noise generated by the noise current source on the voltage control line can be expressed as:

When the low-pass filter capacitor is introduced, the voltage response generated by the noise current generated by the noise current source on the voltage control line can be expressed as:

Considering the actual parameters of the two voltage response expressions and comparing them, it can be found that the low-pass filter introduced reduces the high-frequency noise response by about (sCgsR+1) times.

In this embodiment, the first clock regeneration subunit 213 includes transistors M7, M8, M9, and M10; wherein, the transistors M7 and M9 are PMOS transistors, and the transistors M8 and M10 are NMOS transistors;

The gate of the transistor M7 is connected to the drain common terminal of the transistors M5 and M6, and the source of the transistor M7 is connected to the power supply VDD terminal;

The gate of the transistor M8 is connected to the gate of the transistor M7 and is connected to the common drain of the transistors M5 and M6, the source of the transistor M8 is connected to the GND terminal, and the drain of the transistor M8 is connected to the the drain of transistor M7;

The gate of the transistor M9 is connected to the drain common terminal of the transistors M7 and M8, and the source of the transistor M9 is connected to the power supply VDD terminal;

The gate of the transistor M10 is connected to the gate of the transistor M9 and is connected to the common drain of the transistors M7 and M8, the source of the transistor M10 is connected to the GND terminal, and the drain of the transistor M10 is connected to the The drain of the transistor M9 is used as the output terminal of the first clock regeneration subunit to output the first clock signal, that is, the DCLK signal.

In this embodiment, the N first clock signals output by the N cascaded delay chain basic units are the first clock signal clusters.

In the traditional delay chain, the basic delay unit is mainly constructed by a delay module. After the signal passes through the unit, the output rising and falling edges will slow down; if the cascade count increases, the final output signal may rise before reaching VDD. , it begins to drop, resulting in the deterioration of the duty cycle; if the cascade count continues to increase, the duty cycle continues to deteriorate, and eventually the signal cannot be effectively inverted, that is, the duty cycle is 0. Referring to FIG. 5, FIG. 5 is a schematic diagram of outputting multi-phase clock pulse contraction of a basic delay unit constructed by a delay module according to an embodiment of the present invention.

In this embodiment, by adding a clock regeneration unit, while adjusting the voltage-controlled delay time, the clock duty cycle is restored, so that the output clock of each voltage-controlled delay unit has a certain clock delay and has a steep rising edge and a falling edge at the same time. Thus, the duty cycle consistency of the multi-phase clock is guaranteed.

The clock regeneration unit only records the delay time and recovers the clock rising and falling speed by charging and discharging unlimited inverter groups. Taking the rising edge of the input signal CLK as an example, please refer to FIG. 6. FIG. 6 is a schematic diagram of the signal waveform of the CLK signal after being delayed by the basic delay unit provided by the embodiment of the present invention; 3. Point A becomes the falling edge, and the discharge current of the signal at point A is limited, so the falling edge of the signal at point A is slowed down; thus achieving the purpose of delay. After passing through the first clock regeneration subunit, since the charging and discharging current is not controlled by the current source, the signal waveforms of node B and node C can be established most quickly, and the duty cycle of the clock can be recovered.

In this embodiment, the second delay subunit 214 includes transistors M2, M11, M12, and M4 serially connected to the power supply terminals VDD and GND in sequence; wherein, the transistors M2 and M11 are PMOS transistors, and the transistors M12 and M4 are PMOS transistors. It is an NMOS tube;

The source of the transistor M2 is connected to the power supply VDD terminal, and the source of the transistor M4 is connected to the GND terminal;

The gate of the transistor M2 is connected to the voltage conversion module through the first resistor R1;

The gate of the transistor M4 is connected to the voltage conversion module through the second resistor R2;

The gates of the transistors M11 and M12 are connected to each other and to the output terminal of the first clock regeneration subunit.

The second clock regeneration subunit 215 includes transistors M13, M14, M15, and M16; wherein, the transistors M13 and M15 are PMOS tubes, and the transistors M14 and M16 are NMOS tubes;

The gate of the transistor M13 is connected to the drain common terminal of the transistors M11 and M12, and the source of the transistor M13 is connected to the power supply VDD terminal;

The gate of the transistor M14 is connected to the gate of the transistor M13 and is connected to the common drain of the transistors M11 and M12, the source of the transistor M14 is connected to the GND terminal, and the drain of the transistor M14 is connected to the the drain of transistor M13;

The gate of the transistor M15 is connected to the common drain of the transistors M13 and M14, and the source of the transistor M15 is connected to the power supply VDD;

The gate of the transistor M16 is connected to the gate of the transistor M15 and is connected to the common drain of the transistors M13 and M14, the source of the transistor M16 is connected to the GND terminal, and the drain of the transistor M16 is connected to the The drain of the transistor M15 is used as the output terminal of the second clock regeneration subunit to output the second clock signal, that is, the OCLK signal.

In this embodiment, the N second clock signals output by the N cascaded delay chain basic units are the second clock signal clusters.

The working principles of the second delay subunit and the second clock regeneration subunit are the same as those of the first delay subunit and the first clock regeneration subunit, and will not be repeated here.

Referring to FIG. 7 , FIG. 7 is a comparison diagram of the delay effect of a conventional delay chain provided by an embodiment of the present invention and the present invention. In this embodiment, due to the inherent delay of the introduced clock regeneration unit, the inherent delay of the delay chain unit increases, so that the adjustment range of the voltage control line can be correspondingly reduced to reach the same delay time, which makes the voltage control delay The accuracy is effectively improved, and the anti-noise performance of the voltage-controlled delay chain is improved, which ensures that the voltage-controlled voltage change required for the same delay time difference increases, so it is more suitable for high-precision, multi-chain delay chain phase-locked loops and its constituted. Time digital detection system.

The above content is a further detailed description of the present invention in combination with specific preferred embodiments, and it cannot be considered that the specific implementation of the present invention is limited to these descriptions. For those of ordinary skill in the technical field of the present invention, without departing from the concept of the present invention, some simple deductions or substitutions can be made, which should be regarded as belonging to the protection scope of the present invention.

Claims (7)

1. A high accuracy low kickback noise clock regenerative delay chain, comprising:

the voltage conversion module is connected with the voltage input end and used for converting the input signal into a first voltage signal and a second voltage signal;

the delay chain module is connected with the voltage conversion module and the clock input end and used for controlling clock delay time according to the first voltage signal and the second voltage signal to obtain a first clock signal cluster and a second clock signal cluster; the delay chain module comprises N cascaded delay chain basic units, and the delay chain basic units are connected with the voltage conversion module; wherein N is a positive integer; the delay chain basic unit comprises a low-pass filtering subunit, a first delay subunit, a first clock regeneration subunit, a second delay subunit and a second clock regeneration subunit which are sequentially connected in series;

the low-pass filtering subunit comprises a first resistor R1 and a second resistor R2; wherein,

one end of the first resistor R1 is connected with the voltage conversion module, and the other end is connected with the first delay subunit and the second delay subunit;

one end of the second resistor R2 is connected with the voltage conversion module, and the other end is connected with the first delay subunit and the second delay subunit;

and the clock driving module is connected with the delay chain module and is used for receiving and processing the first clock signal cluster and the second clock signal cluster and outputting a multi-phase clock signal cluster.

2. The clock regenerative delay chain of claim 1, wherein the first delay sub-unit comprises transistors M1, M5, M6, M3 connected in series in sequence to a power supply terminal VDD and a GND terminal; wherein,

the source of the transistor M1 is connected with a power supply VDD terminal, and the source of the transistor M3 is connected with a GND terminal;

the gate of the transistor M1 is connected with the voltage conversion module through the first resistor R1;

the gate of the transistor M3 is connected with the voltage conversion module through the second resistor R2;

the gates of the transistors M5 and M6 are connected to each other and to the clock input.

3. The clock regenerative delay chain of claim 2, wherein the first clock regenerative subunit comprises transistors M7, M8, M9, M10; wherein,

the gate of the transistor M7 is connected with the common drain terminal of the transistors M5 and M6, and the source of the transistor M7 is connected with the VDD terminal;

the gate of the transistor M8 is connected with the gate of the transistor M7 and the common drain terminal of the transistors M5 and M6, the source of the transistor M8 is connected with the GND terminal, and the drain is connected with the drain of the transistor M7;

the gate of the transistor M9 is connected with the common drain terminal of the transistors M7 and M8, and the source of the transistor M9 is connected with the VDD terminal;

the gate of the transistor M10 is connected to the gate of the transistor M9 and to the common drain terminal of the transistors M7 and M8, the source of the transistor M10 is connected to the GND terminal, and the drain of the transistor M10 is connected to the drain of the transistor M9 and outputs the first clock signal as the output terminal of the first clock regeneration subunit.

4. The clock regenerative delay chain of claim 3, wherein the second delay sub-unit comprises transistors M2, M11, M12, M4 connected in series in sequence to a power supply terminal VDD and a GND terminal; wherein,

the source of the transistor M2 is connected with a power supply VDD terminal, and the source of the transistor M4 is connected with a GND terminal;

the gate of the transistor M2 is connected with the voltage conversion module through the first resistor R1;

the gate of the transistor M4 is connected with the voltage conversion module through the second resistor R2;

the gates of the transistors M11 and M12 are connected to each other and to the output terminal of the first clock regeneration subunit.

5. The clock regenerative delay chain of claim 4, wherein the second clock regenerative subunit comprises transistors M13, M14, M15, M16; wherein,

the gate of the transistor M13 is connected with the common drain terminal of the transistors M11 and M12, and the source of the transistor M13 is connected with the VDD terminal;

the gate of the transistor M14 is connected with the gate of the transistor M13 and the common drain terminal of the transistors M11 and M12, the source of the transistor M14 is connected with the GND terminal, and the drain of the transistor M14 is connected with the drain of the transistor M13;

the gate of the transistor M15 is connected with the common drain terminal of the transistors M13 and M14, and the source of the transistor M15 is connected with the VDD terminal;

the gate of the transistor M16 is connected to the gate of the transistor M15 and to the common drain terminal of the transistors M13 and M14, the source of the transistor M16 is connected to the GND terminal, and the drain of the transistor M16 is connected to the drain of the transistor M15 and outputs the second clock signal as the output terminal of the second clock regeneration subunit.

6. The clock regeneration delay chain of claim 5, wherein the transistors M1, M2, M5, M7, M9, M11, M13 and M15 are all PMOS transistors, and the transistors M3, M4, M6, M8, M10, M12, M14 and M16 are all NMOS transistors.

7. The clock regenerative delay chain of claim 1, wherein the clock driver module comprises N clock driver units, the N clock driver units being sequentially connected to N delay chain base units.

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