CN103532555A - Voltage comparator based on voltage-controlled oscillators - Google Patents
Voltage comparator based on voltage-controlled oscillators Download PDFInfo
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Abstract
The invention relates to a voltage comparator based on a voltage-controlled oscillator, which comprises a voltage-controlled oscillator receiving input voltage and a voltage-controlled oscillator receiving reference voltage, wherein the voltage-controlled oscillators are connected with different input ports of a frequency detector respectively; two output ports, corresponding to the input ports, of the frequency detector are connected with a corresponding high level control end and a low level control end in a charge pump circuit respectively; a capacitor is arranged in the charge pump circuit; and the charge pump circuit outputs a compared level signal. The voltage comparator based on the voltage-controlled oscillators overcomes the disadvantages of difficult design, poor noise immunity and long transmission time of the traditional comparator at low supply voltage, has reliable output performances, and is applicable to a high-precision and high-speed low-voltage analog-to-digital converter.
Description
Technical field
The present invention relates to analog integrated circuit technical field, is the voltage comparator based on voltage controlled oscillator concretely.
Background technology
Current, along with the fast development of wireless communication technology, analog-to-digital conversion device towards low pressure, low-power consumption, at a high speed, high-precision future development.The type of existing analog to digital converter can be divided into Nyquist analog to digital converter and oversampling analog-to-digital converter according to sample frequency and system bandwidth.Wherein, Nyquist analog to digital converter can be divided into SAR again, FLASH, and Pipeline etc., their sample frequency is all the twice of system bandwidth; Oversampling analog-to-digital converter also divide discrete time analog to digital converter and continuous time analog to digital converter.Above-mentioned analog-to-digital conversion device, all needs analog signal to be compared, quantized by comparator, just can obtain last quantification Output rusults.
Main CMOS comparator configuration has now: open loop comparator, switching capacity comparator, regeneration latched comparator and pre-amplification regeneration latched comparator.These traditional comparators are all to utilize the voltage of input signal and reference voltage to compare by amplifier, and precision relatively and limited speed are in gain, bandwidth and the Slew Rate of amplifier.In the situation that requiring resolution higher, toward contact, need to add multistage pre-amplification circuit, the transmission time of circuit is also long, and Output rusults noise resisting ability is relatively poor.Along with CMOS size is dwindled further, it is more and more difficult that the design of these comparators in low supply voltage also becomes.
Summary of the invention
The invention provides a kind of voltage comparator based on voltage controlled oscillator, to overcome traditional comparator, under low supply voltage, be not easy to the shortcoming designing, noise resisting ability is poor, the transmission time is long, be suitable for low-voltage, high accuracy, analog to digital converter at a high speed.
The present invention is based on the voltage comparator of voltage controlled oscillator, comprise that the voltage controlled oscillator that receives the voltage controlled oscillator of input voltage and receive reference voltage is connected to respectively the different input port of frequency discriminator, two output ports corresponding with described input port of frequency discriminator are connected to respectively high level control end corresponding in charge pump circuit and low level control end, in charge pump circuit, be provided with electric capacity, the level signal after exporting relatively by charge pump circuit.Voltage comparator of the present invention is not directly to compare two input voltage signals to obtain the result of comparison, but voltage signal is converted into frequency signal by voltage controlled oscillator, then compares.Because the output of the frequency signal of voltage controlled oscillator can utilize digital circuit to process, therefore have good noise resisting ability.And comparative result constantly charges to output capacitance through charge pump or the process inverter output again of constantly discharging obtains.Therefore the comparative result of output just only has high level and low level two states, is not easy to make mistakes.
Concrete, described voltage controlled oscillator comprises that at least 3 groups are by a NMOS pipe and a transistor pair that PMOS pipe forms, the drain electrode of every group transistor centering NMOS pipe and the drain electrode of PMOS pipe are all connected the right NMOS pipe of another group transistor and the grid of PMOS pipe, voltage is relatively inputted by the grid of tail current source NMOS pipe, output frequency signal through each transistor to after again through two reversers outputs.The effect of voltage controlled oscillator is mainly that the voltage signal of input is converted into frequency signal.The signal of input is larger, and the concussion frequency of voltage controlled oscillator output is higher.Output frequency is only required the signal voltage monotone increasing with input, and not requiring increases along with signal voltage is linear.The effect of frequency discriminator is the size of two frequencies of comparison, and the control signal of outputting charge pump.The structure of frequency discriminator can consist of RS latch, NAND gate, inverter and transmission gate.
Concrete, at the high level control end described in charge pump circuit, be connected with the grid of a NMOS pipe, described low level control end is connected with the grid of a PMOS pipe, constant current source is connected with the source electrode of PMOS pipe with described NMOS pipe by auxiliary circuit, the drain electrode of NMOS pipe and PMOS pipe is exported by two reversers, is also connected with the electric capacity of ground connection at the input of two reversers.The effect of charge pump is, according to the typical pulse width of the output high level port of frequency discriminator above and low level port, electric capacity is carried out to charge or discharge.When frequency discriminator, to be that high level port is output as low, and low level port is output as when low, the PMOS pipe conducting in charge pump circuit, and NMOS manages cut-off, to capacitor charging; When the low level port of frequency discriminator is output as height, high level port is output as when high, the NMOS pipe conducting in lotus pump circuit, and PMOS manages cut-off, capacitor discharge; When the high level port of frequency discriminator is output as lowly, low level port is output as when high, and PMOS pipe and NMOS pipe in charge pump circuit all end, the electric current electric capacity of not flowing through, and capacitance voltage maintenance is constant; When the high level port of frequency discriminator is output as height, low level port is output as when low, and PMOS pipe and NMOS in charge pump circuit manage conductings, and it is constant that capacitance voltage also keeps.Finally, the voltage of output capacitance is exported last comparative result through two-stage reverser.
Further, two described ring oscillators that voltage controlled oscillator is all same progression, and the Voltage-output of the voltage that is relatively output as charge pump institute bringing onto load electric capacity of frequency discriminator after two-stage inverter, the comparison Output rusults of frequency discriminator can be directly used in digital units.
The present invention is based on the voltage comparator of voltage controlled oscillator, overcome traditional comparator and under low supply voltage, be not easy to the shortcoming designing, noise resisting ability is poor, the transmission time is long, there is reliable output performance, can be applicable to low-voltage, high accuracy, analog to digital converter at a high speed.
Below in conjunction with the embodiment of embodiment, foregoing of the present invention is described in further detail again.But this should be interpreted as to the scope of the above-mentioned theme of the present invention only limits to following example.Without departing from the idea case in the present invention described above, various replacements or the change according to ordinary skill knowledge and customary means, made, all should comprise within the scope of the invention.
Accompanying drawing explanation
Fig. 1 is the circuit diagram that the present invention is based on the voltage comparator of voltage controlled oscillator.
Fig. 2 is the circuit diagram of voltage controlled oscillator in Fig. 1.
Fig. 3 is the structure chart of kam-frequency circuit in Fig. 1.
Fig. 4 is the structure chart of charge pump circuit in Fig. 1.
Fig. 5 is the simulation figure that the input signal of circuit diagram shown in Fig. 1 is less than reference signal.
Fig. 6 is the simulation figure that the input signal of circuit diagram shown in Fig. 1 is greater than reference signal.
Embodiment
Voltage comparator based on voltage controlled oscillator of the present invention as shown in Figure 1, by two, receive input voltage V1, the voltage controlled oscillator VCO 1 of V2, VCO2 is connected to respectively the corresponding input port of frequency discriminator PFD by the first output frequency Fre1 and the second output frequency Fre2, two voltage controlled oscillator VCO 1, VCO2 is the ring oscillator of same progression.Two high level output port UP corresponding with described input port and the low level output port DN of frequency discriminator PFD are connected to respectively high level control end corresponding in charge pump circuit and low level control end, in charge pump circuit, be provided with capacitor C ap, the level signal after exporting relatively by charge pump circuit.
Described voltage controlled oscillator as shown in Figure 2, comprised that 3 groups by a NMOS pipe and a transistor pair that PMOS pipe forms, the drain electrode of every group transistor centering NMOS pipe and the drain electrode of PMOS pipe are all connected the right NMOS pipe of another group transistor and the grid of PMOS pipe, voltage is relatively inputted by the grid of tail current source NMOS pipe, output frequency of oscillation through each transistor to after again through two reversers outputs.
As shown in Figure 4, at the high level control end UP described in charge pump circuit, be connected with the grid of a NMOS pipe, described low level control end DN is connected with the grid of a PMOS pipe, constant current source I is connected with the source electrode of PMOS pipe with described NMOS pipe by auxiliary circuit, the drain electrode of NMOS pipe and PMOS pipe is exported by two reversers, is connected with the capacitor C ap of ground connection at the input of two reversers.
The comparator based on voltage controlled oscillator of the present embodiment is not directly to compare the result that two input voltage signals obtain comparison, but voltage signal is passed through to voltage controlled oscillator VCO 1, and VCO2 is converted into frequency signal, then compares.Because voltage controlled oscillator VCO 1, the frequency signal output of VCO2 can utilize digital circuit to process, therefore have good noise resisting ability.And comparative result constantly charges to output capacitance Cap through charge pump circuit or the process inverter output again of constantly discharging obtains.Therefore the comparative result of output just only has high level and low level two states, is not easy to make mistakes.
The effect of voltage controlled oscillator is mainly that the voltage signal of input is converted into frequency signal.The signal of input is larger, and the concussion frequency of voltage controlled oscillator output is higher.Output frequency is only required the signal voltage monotone increasing with input, and not requiring increases along with signal voltage is linear.Voltage controlled oscillator adopts structure as shown in Figure 2, in the present embodiment, voltage controlled oscillator adopts tertiary circulation shape oscillator, mainly to consider that comparator do not do requirement to the linearity of the output frequency of ring oscillator, just monotonicity is done to requirement, therefore in order to make the less ring oscillator of selecting three grades of area of circuit.
In Fig. 1, the effect of frequency discriminator PFD is the size of two frequencies of comparison, and the control signal of output charge pump circuit.As shown in Figure 3, when the first output frequency Fre1 is greater than the second output frequency Fre2, the high level output end UP of frequency discriminator PFD is output as high average effective switch level width and is greater than low level output end DN and is output as low average effective switch level width.When the first output frequency Fre1 is less than the second output frequency Fre2, the high level output end UP of frequency discriminator PFD is output as high average effective switch level width and is less than low level output end DN and is output as low average effective switch level width.The structure of frequency discriminator PFD can consist of RS latch, NAND gate, inverter and transmission gate.The d type flip flop of two band resets up and down of frequency discriminator PFD consists of two cross-linked RS latchs.When the rising edge of the first output frequency Fre1 first arrives than the rising edge of the second output frequency Fre2, the output Q output high level of d type flip flop above, high level output end UP is output as high level.Until the rising edge of the second output frequency Fre2 arrives, d type flip flop output Q is below output as height, cause reset signal to be output as high level, make all output low levels of d type flip flop, high level output end UP is low by hypermutation, low level output end DN only exports narrow low level pulse, and effective switch level pulse duration of high level output end UP is greater than effective switch level pulse duration of low level output end DN.While arriving after the rising edge of the first output frequency Fre1 is than the rising edge of the second output frequency Fre2, its principle is the same, and effective switch level pulse duration of low level output end DN is greater than effective switch level pulse duration of high level output end UP.
The effect of charge pump circuit is according to the high level output end UP of frequency discriminator PFD and the typical pulse width of low level output end DN output are carried out charge or discharge to capacitor C ap above.Because system compares Output rusults within 50ns, suppose that output capacitance is 50fF, supply voltage is 1V, when charging current is 10uA, from 0, being charged to the supply voltage charging interval used is 5ns.Because charge pump circuit is not always to capacitor C ap charging or electric discharge, but carry out work according to the control impuls of frequency discriminator PFD, therefore the actual time that is charged to supply voltage may need 6～8 times of charging interval.Therefore the charging current of charge pump circuit can be made as to 10uA, capacitor C ap is made as 50fF.In fact output voltage does not need to be charged to supply voltage, and the turnover voltage that only need to reach inverter can be identified as high level.When low level output end DN is output as lowly, high level output end UP is output as when low, corresponding PMOS pipe conducting in charge pump circuit, and NMOS manages cut-off, and capacitor C ap is charged; When high level output end, UP is output as height, and low level output end DN is output as when high, and NMOS manages conducting, and PMOS manages cut-off, and capacitor C ap is discharged; When low level output end DN is output as lowly, high level output end UP is output as when high, and PMOS pipe and NMOS manage conductings, the electric current electric capacity of not flowing through, and the output voltage maintenance of capacitor C ap is constant; When low level output end, DN is output as height, and high level output end UP is output as when low, and PMOS pipe and NMOS manage and end, and it is constant that the output voltage of capacitor C ap also keeps.Finally, the voltage of output capacitance Cap is exported last comparative result through two-stage reverser.
Below in conjunction with the description to system configuration and modules function above, the principle that weight analysis the present invention is based on the comparator of voltage controlled oscillator, and theoretical foundation of the present invention.
The present invention is mainly the comparison that relatively changes into frequency of voltage, and process relatively is mainly divided into two steps: 1, voltage signal is changed into the frequency signal corresponding with it, and the larger frequency of voltage signal is higher; 2, by the frequency height of two kinds of frequency signals more out.
First, voltage signal is changed into and its frequency signal one to one, this can realize by ring oscillator.If the output frequency of oscillator is Fre, control voltage is Vc, and free oscillation frequency is f0, and the frequency of oscillator output Fre can be expressed as
Fre=f
0+K
vco·V
c+K
2·V
c 2+K
3·V
c 3+......(1)
From formula (1), can see that will make voltage signal and frequency signal is relation one to one, it is dull only needing the function of formula (1), and will make output frequency, be that monotonically increasing only need to regulate the breadth length ratio of voltage controlled oscillator pipe that the coefficient of controlling voltage Vc is just, even if this under low pressure also can realize at an easy rate.And, due to the gain of voltage controlled oscillator can accomplish very high, even if the voltage signal being compared is more or less the same, through also converting the frequency signal of easily distinguishing after voltage controlled oscillator to.
Secondly, by frequency signal, more out, this can realize with frequency discriminator PFD and charge pump circuit.When the frequency of the Fre1 of the input of frequency discriminator PFD is greater than the frequency of Fre2, high level output end UP output has wider effective switch level width, and low level output end DN output to only have the time of narrow reset delay be low level.Therefore charge pump circuit will discharge with constant current I to capacitor C ap, until capacitor C ap both end voltage is just to stop electric discharge at 0 o'clock.In like manner, when the first output frequency Fre1 is less than the second output frequency Fre2, high level output end UP output only has the reseting pulse width of narrow high level, and low level output end DN output has wider Low level effective switch level width, charge pump circuit will charge with constant current I to capacitor C ap, until the voltage of capacitor C ap just stops charging while being supply voltage VDD.The voltage that unit interval electric capacity changes is determined by formula (2) below:
Wherein Δ V is the voltage of capacitance variations, and unit is volt; Δ t is the time of capacitor charge and discharge, and unit is second; I is charging and discharging currents, and unit is ampere; C is charge pump load capacitance, and unit is farad.When load capacitance C is 50fF, supply voltage VDD is 1V, and when charging current is 10uA, from 0, being charged to the supply voltage charging interval used is 5ns.
In sum, when input voltage signal V1 is greater than reference voltage signal V2, the first output frequency Fre1 of voltage controlled oscillator is greater than the second output frequency Fre2, the load capacitance Cap electric discharge of charge pump circuit, and comparative result is output as low level; Otherwise when input voltage signal V1 is less than reference voltage signal V2, the first output frequency Fre1 of voltage controlled oscillator is less than the second output frequency Fre2, the capacitor C ap charging of charge pump circuit to load, comparative result is output as high level.From the output signal of voltage controlled oscillator, the signal of processing of circuit is to be just similar to the long arc signal of thinking digital signal substantially, therefore the noise resisting ability of circuit is stronger.Because the gain of voltage controlled oscillator can be very high, so comparator can reach higher resolution.
As shown in Figure 5, the comparator based on voltage controlled oscillator of the present embodiment is carried out to circuit simulation.When input voltage V1 is 0.20V, the first output frequency Fre1 of the first voltage controlled oscillator VCO 1 is 300.5M; When reference voltage V2 is 0.21V, the second output frequency Fre2 of the second voltage controlled oscillator VCO 2 is 310.5M.Frequency discriminator PFD compares and makes the average Low level effective switch level width of low level output end DN output be greater than the effective switch level width of mean height level that high level output end UP exports two frequency signals, to output capacitance, Cap charges, and relatively Output rusults is high level.Simulation result as shown in Figure 5.As can be seen from Figure 5, when 32.5nss, the voltage Vch of capacitor C ap is charged to supply voltage, and the Output rusults Vout of comparator has exported high level when 22.8ns, judges input voltage V1 and is less than reference voltage V2.The comparator that passes through comparison signal voltage swing of traditional structure will need hundreds of nanosecond just can obtain comparative result.Therefore speed is faster comparatively speaking for the comparator based on voltage controlled oscillator that, the present invention proposes.
As shown in Figure 6, when input voltage V1 is 0.1V, the first output frequency Fre1 of the first voltage controlled oscillator VCO 1 is 200.1M; When reference voltage V2 is 0.05V, the second output frequency Fre2 of the second voltage controlled oscillator VCO 2 is 150.0M, frequency discriminator PFD compares and makes the average low level pulse width of low level output end DN output be less than the mean height level pulse widths that high level output end UP exports two frequency signals, output capacitance Cap electric discharge, relatively Output rusults is low level.Simulation result as shown in Figure 6.As can be seen from Figure 6, output capacitance voltage remains on low level state always.
In sum, the comparator based on voltage controlled oscillator that the present invention proposes is applicable to low pressure, there is stronger noise resisting ability, higher resolution and time decision relatively faster, can be applied in low pressure, at a high speed, in the conversion of high-precision analog to digital.
Claims (4)
1. the voltage comparator based on voltage controlled oscillator, its feature comprises: receive the different input port that the voltage controlled oscillator of input voltage and the voltage controlled oscillator of reception reference voltage are connected to respectively frequency discriminator, two output ports corresponding with described input port of frequency discriminator are connected to respectively high level control end corresponding in charge pump circuit and low level control end, in charge pump circuit, be provided with electric capacity, the level signal after exporting relatively by charge pump circuit.
2. the voltage comparator based on voltage controlled oscillator as claimed in claim 1, it is characterized by: described voltage controlled oscillator comprises that at least 3 groups are by a NMOS pipe and a transistor pair that PMOS pipe forms, the drain electrode of every group transistor centering NMOS pipe and the drain electrode of PMOS pipe are all connected the right NMOS pipe of another group transistor and the grid of PMOS pipe, voltage is relatively inputted by the grid of tail current source NMOS pipe, output frequency signal through each transistor to after again through two reversers outputs.
3. the voltage comparator based on voltage controlled oscillator as claimed in claim 1, it is characterized by: at the high level control end described in charge pump circuit, be connected with the grid of a NMOS pipe, described low level control end is connected with the grid of a PMOS pipe, constant current source is connected with the source electrode of PMOS pipe with described NMOS pipe by auxiliary circuit, the drain electrode of NMOS pipe and PMOS pipe is exported by two reversers, is also connected with the electric capacity of ground connection at the input of two reversers.
4. the voltage comparator based on voltage controlled oscillator as described in one of claims 1 to 3, is characterized by: two described ring oscillators that voltage controlled oscillator is all same progression.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN106664018A (en) * | 2014-10-17 | 2017-05-10 | 密克罗奇普技术公司 | Measuring output current in a buck smps |
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| CN113162614A (en) * | 2020-01-22 | 2021-07-23 | 瑞昱半导体股份有限公司 | High speed clock filter and method thereof |
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Application publication date: 20140122 |