CN110798212B - Time domain interleaved waveform synthesis timing mismatch calibration device and method - Google Patents
Time domain interleaved waveform synthesis timing mismatch calibration device and method Download PDFInfo
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Abstract
The utility model provides a time domain interweaving waveform synthesis timing mismatch calibration device and method, a sinusoidal waveform generation module generates two paths of sinusoidal signals with the same frequency and half sampling period phase delay difference, one path is a reference signal, the other path is an adjustment signal, the phase delay difference of the two paths of sinusoidal signals is Ts/2, the sinusoidal signals are respectively converted into sinusoidal analog signals after passing through a DAC module, a phase discrimination module extracts the phase difference of the two paths of sinusoidal signals and converts the phase difference into a direct current signal, a loop filtering module filters the noise of the direct current signal and converts the noise into a direct current voltage signal, an analog delay module generates corresponding delay according to the direct current voltage and delays the DAC sampling clock of the adjustment signal, so that the phase difference of the two paths of sinusoidal signals tends to be infinite zero; the phase difference is directly converted into the control quantity of DAC sampling clock delay without phase difference measurement, so that the phases of two paths of DAC output signals are automatically adjusted in a negative feedback manner, and the method has the advantages of high precision, good stability, simple structure and high speed.
Description
Technical Field
The present disclosure relates to the field of high-speed arbitrary waveform generation technologies, and in particular, to a time-domain interleaved waveform synthesis timing mismatch calibration apparatus and method.
Background
The statements in this section merely provide background information related to the present disclosure and may not necessarily constitute prior art.
The high-speed arbitrary waveform generation technology is a signal generation technology based on digital, analog and computer technologies, and is widely applied to the fields of radar, satellite communication, electronic countermeasure, radio frequency test, integrated circuit test and the like, and becomes a research hotspot in the field of modern electronic technologies. The high-speed arbitrary waveform generator using the technology as the core has the advantages of high output frequency stability and resolution, high frequency switching speed, continuous output waveform phase during switching and the like, and the abundant signal excitation capability of the generator comprises a high-speed waveform generator, a function generator, a broadband white noise signal generator, an amplitude modulation source and the like. With the development of electronic technology, high-speed arbitrary waveform generators may play an important role in a variety of applications such as broadband communication, radar systems, high-speed pulse simulation, high-speed digital design, field environment simulation, and playback.
The sampling rate and bandwidth at which high-speed arbitrary waveforms occur is limited by the sampling rate and bandwidth of the DAC. Due to the design level of the DAC chip and the restriction of the processing technology, the sampling rate and the bandwidth of the single-path DAC cannot meet the requirements of high-speed arbitrary waveform generation. At present, the DAC parallel mode is the main approach to solve the problem, and a time-domain interleaved waveform synthesis method is mainly adopted. For example, two paths of DAC signals are synthesized, a first channel outputs even points of waveform data to DAC-1, a second channel outputs odd points of the waveform data to DAC-2, phase delay difference of output of the two channels is Ts/2, and Ts is the sampling clock period of the DAC. The output of the two channels realizes the superposition of analog signals through an adder. The superposed output signals can break through the limitation of the sampling rate and the bandwidth of a single-path DAC, the sampling rate of output waveforms is twice of the sampling rate of the DAC, the bandwidth can reach 40% of the sampling rate of the waveforms, and the sampling rate and the bandwidth of the output waveforms are effectively improved. The output phase time sequences of the two channels have to strictly differ by half a sampling period, and the quality of the interleaved waveform is reduced and the spurious signals are increased due to the time sequence mismatch. The delay differences of the DACs easily cause timing mismatch, which usually requires calibration. At present, two common calibration devices are provided, one is realized by a dual-channel ADC and a processor, the ADC acquires signals output by two channels of DACs, the processor calculates a phase difference between the two channels, and then adjusts a phase of waveform data. The other method is realized by a logic gate and a processor, the two paths of DAC output signals are subjected to logic AND operation, the phase difference is converted into a pulse signal, the pulse width of the pulse signal is measured by the processor to obtain the phase difference, and then the phase of waveform data is adjusted.
The inventor of the present disclosure finds that the conventional timing calibration apparatus first uses a processor to perform phase difference measurement, and then performs phase adjustment according to the measurement result. When the phase difference is measured, new errors are introduced into the time delay of the ADC circuit or the logic gate circuit, the calibration precision is reduced, the measurement result is calculated through the processor, the time consumption is large, and the circuit structure is complex.
Disclosure of Invention
In order to solve the defects of the prior art, the invention provides a time domain interleaved waveform synthesis timing mismatch calibration device and method, which directly convert phase difference into control quantity of DAC sampling clock delay without phase difference measurement, so that the phases of two paths of DAC output signals realize negative feedback automatic adjustment, and have the advantages of high precision, good stability, simple structure and high speed.
In order to achieve the purpose, the following technical scheme is adopted in the disclosure:
the disclosure provides a time-domain interleaved waveform synthesis timing mismatch calibration apparatus in a first aspect.
A time domain interweaving waveform synthesis time sequence mismatch calibration device comprises a sine waveform generation module, two output selection modules, two DAC modules, a phase discrimination module, a loop filtering module, a signal conditioning module and an analog delay module;
the sinusoidal waveform generating module generates two paths of sinusoidal signals with the same frequency and phase delay difference of half a sampling period, one path is a reference signal, the other path is an adjusting signal, the phase delay difference Ts/2 of the two paths of sinusoidal signals is converted into sinusoidal analog signals after passing through the output selection module and the DAC module respectively, and then the sinusoidal analog signals enter the phase discrimination module through the microwave switch respectively;
the phase discrimination module extracts the phase difference of the two sinusoidal signals and converts the phase difference into a direct current signal, the loop filter module filters the noise of the direct current signal and converts the noise into a direct current voltage signal, the signal conditioning module adds gain for the direct current voltage signal so as to match the input voltage range of the analog delay module, the analog delay module generates corresponding delay amount according to the direct current voltage and delays the DAC sampling clock of the adjusting signal, and the phase difference of the two sinusoidal signals is infinitely close to zero.
As some possible implementation manners, the phase detection module includes a phase detection circuit and a charge pump circuit, the phase detection circuit includes two DFF flip-flops and an and gate, when the phase detection module works, D terminals of the two DFF flip-flops are set to a high level, a reference signal and an adjustment signal are respectively used as clock input signals of the two DFF flip-flops, and outputs of the two DFF flip-flops are connected to RST terminals of the DFF flip-flops after passing through the and gate;
the charge pump circuit comprises two constant current sources and two MOS tube control switches, and the two MOS tube control switches are respectively controlled by output signals of two DFF triggers of the phase discrimination circuit so as to realize the charge or discharge of the charge pump.
As some possible implementation manners, the calibration apparatus further includes a lock detection module, where the lock detection module is a dc ADC module, the dc ADC module is connected to the output end of the loop filter module, the dc ADC module detects the state of the dc voltage output by the loop filter module, and when the level value is not changed, it determines that the circuit is locked;
as some possible implementation manners, the two output selection modules respectively output waveform data of even-numbered sampling points and odd-numbered sampling points to the two DAC modules, the two signals enter the power synthesis module through the microwave switch to be synthesized into one signal, and the one signal is output after passing through the low-pass filtering module.
A second aspect of the present disclosure provides a time-domain interleaved waveform synthesis timing mismatch calibration method.
A time-domain interleaved waveform synthesis timing mismatch calibration method utilizes the time-domain interleaved waveform synthesis timing mismatch calibration device of the first aspect of the present disclosure, and comprises the following steps:
the sine waveform generating module generates sine waveform reference data and adjusting data with the initial phase delay difference of half a sampling period, the two paths of waveform data are converted into two paths of sine analog signals with the phase difference through the DAC module respectively, and the two paths of waveform analog signals reach the phase discrimination module through the microwave switch;
the phase discrimination module extracts the phase difference of the two paths of sinusoidal signals and converts the phase difference into a direct current signal, and the loop filtering module filters the noise of the direct current signal and converts the noise into a direct current voltage signal;
the signal conditioning module adds gain to the direct-current voltage to match the input voltage range of the analog delay module, and the analog delay module delays the DAC sampling clock of the adjusted signal according to the delay amount generated by the direct-current voltage, so that the phase difference of the two paths of sinusoidal signals is infinitely close to zero.
As some possible implementation manners, when the phase difference obtained by subtracting the adjustment signal from the reference signal is greater than zero, the phase demodulation module outputs a dc voltage increase, the analog delay module outputs a DAC sampling clock with an increased delay amount, and the initial phase of the adjustment signal output is increased, so that the phase difference is increased and tends to zero without limitation.
As some possible implementation manners, when the phase difference obtained by subtracting the adjustment signal from the reference signal is less than zero, the phase demodulation module outputs a reduced direct-current voltage, the analog delay module outputs a DAC sampling clock with a reduced delay amount, and the adjustment signal outputs an initial phase with a reduced phase difference, which is not limited to zero.
As some possible implementations, the analog delay module is implemented by an analog phase shifter, and the characteristics of the analog phase shifter are represented as:
wherein, the first and the second end of the pipe are connected with each other,
kc is the transfer characteristic parameter of the analog phase shifter, and Vt is the output voltage of the signal conditioning module.
As a further limitation, the output voltage Vt of the signal conditioning module is calculated by:
wherein Vtmax is the maximum value of the input voltage of the analog delay module, vomax is the maximum value of the output voltage of the signal conditioning module, and Vo is the control voltage output by the loop filter module;
further, the calculation method of the control voltage Vo output by the loop filter module is as follows:
wherein Z(s) is an impedance function of the loop filter module,
the output current of the phase discrimination module;
further, the output current of the phase discrimination module
The calculation method specifically comprises the following steps:
wherein Icp is the charge and discharge current of the charge pump circuit,
the phase difference of the adjustment signal is subtracted from the reference signal,
the method comprises the steps of waveform data initial phase difference, FPGA and DAC internal delay error.
As some possible implementation manners, after the direct current ADC module detects that the circuit is locked, the values of the phase demodulation module and the analog delay module are not changed, the delay difference between the two channels is half of the sampling clock period, the output selection module outputs the waveform data of the even number sample point and the odd number sample point to the two DAC modules, the two signals enter the power synthesis module through the microwave switch to be synthesized into one signal, and the one signal is filtered and output.
The third aspect of the present disclosure provides an arbitrary waveform synthesis apparatus, which includes the time-domain interleaved waveform synthesis timing mismatch calibration apparatus according to the first aspect of the present disclosure, and performs calibration by using the time-domain interleaved waveform synthesis timing mismatch calibration method according to the second aspect of the present disclosure.
Compared with the prior art, the beneficial effect of this disclosure is:
1. according to the method, the phase-to-phase delay measurement is not needed, the control quantity of the phase-difference conversion DAC sampling clock delay is directly delayed, the phases of two paths of DAC output signals are subjected to negative feedback automatic adjustment, and the method has the advantages of high precision, good stability, simple structure and high speed.
2. The calibration device disclosed by the disclosure adopts a negative feedback mode, when the phase difference of subtracting a reference signal from an adjusting signal is less than zero, the output direct current level of a phase discrimination module is increased, the delay amount of a DAC (digital-to-analog converter) sampling clock output by an analog delay module is increased, and the output initial phase of the adjusting signal is increased, so that the phase difference is increased and tends to zero; when the phase difference of the reference signal subtracted by the adjusting signal is larger than zero, the output direct current level of the phase discrimination module is reduced, the delay amount of the sampling clock of the DAC output by the analog delay module is reduced, the output initial phase of the adjusting signal is reduced, so that the phase difference is reduced and tends to zero, after the calibration is completed, the phase delay of the waveform data is half of the sampling period, the DAC delay is zero, and the channel delay is half of the sampling period.
3. The phase discrimination module comprises a phase discrimination circuit and a charge pump circuit, the phase difference of two paths of calibration signals is converted into charge-discharge current, so that the phase difference information of the two paths of signals can be extracted with high precision, and meanwhile, a simulation phase shifter chip is adopted, so that the phase discrimination is high.
Drawings
Fig. 1 is a schematic structural diagram of a time-domain interleaved waveform synthesis timing mismatch calibration apparatus according to embodiment 1 of the present disclosure.
Fig. 2 is a schematic flow chart of a time-domain interleaved waveform synthesis timing mismatch calibration method according to embodiment 1 of the present disclosure.
Fig. 3 is a block diagram of an implementation of the phase detection module and the filtering module according to embodiment 1 of the present disclosure.
Fig. 4 is a characteristic diagram of a simulated phase shifter according to embodiment 1 of the present disclosure.
Fig. 5 is a schematic diagram of DAC interleaving of the return-to-zero hold function according to embodiment 1 of the present disclosure.
Detailed Description
It should be noted that the following detailed description is exemplary and is intended to provide further explanation of the disclosure. Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs.
It is noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments according to the present disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, and it should be understood that when the terms "comprises" and/or "comprising" are used in this specification, they specify the presence of stated features, steps, operations, devices, components, and/or combinations thereof, unless the context clearly indicates otherwise.
The embodiments and features of the embodiments in the present application may be combined with each other without conflict.
Example 1:
as shown in fig. 1, an embodiment 1 of the present disclosure provides a time-domain interleaved waveform synthesis timing mismatch calibration apparatus, which includes a sine wave generation module, a phase discrimination module, a loop filtering module, a signal conditioning module, an analog delay module, a lock detection module, a microwave switch, and an output selection module.
The sine wave generation module is used for generating calibration signals, and the calibration signals comprise a reference sine signal Sig1 and an adjustment sine signal Sig2;
the phase discrimination module converts the phase difference of the two calibration signals into charge and discharge current; the loop filter module converts the current into a direct current level and filters the noise of direct current voltage; the signal conditioning module is used for amplifying or attenuating direct-current voltage and matching the voltage range output by the loop filtering module and input by the analog delay module;
the analog delay module controls the delay amount of the DAC sampling clock of the path of the adjusting signal Sig2 through the direct-current voltage to realize the initial phase adjustment of the output signal of the path. The locking detection module obtains the locking state of the circuit through the measurement of the direct-current voltage. The microwave switch has a single-pole double-throw function and can realize the switching of a calibration channel and an interweaving channel. The output selection module realizes the switching of sine wave and interweaving wave.
The overall workflow diagram is shown in fig. 2. After each power-up, the calibration mode is entered first. The microwave switch switches to the calibration channel. The sine waveform generation module generates waveforms based on a DDS principle and is mainly realized by an FPGA program. The module generates two paths of sine waveform reference data and adjusting data with the same frequency and initial phase delay of 0 and Ts/2 respectively, wherein Ts is a sampling period. Two paths of waveform data are converted into two paths of sine analog signals with phase difference through a DAC, and the two paths of waveform data reach the phase discrimination module through a microwave switch.
The phase detection module is mainly realized by a digital circuit, mainly comprises a phase detection circuit and a charge pump circuit, and the realization block diagram is shown in figure 3.
The phase discrimination circuit mainly comprises two DFF triggers and an AND gate, the charge pump circuit mainly comprises two constant current sources and two control switches, and the switching circuit is generally realized by an MOS (metal oxide semiconductor) tube and is controlled by an output signal of the phase discrimination circuit.
When the phase discrimination module works, the D ends of the two DFF triggers are set to be high level, and the input signals Sig1 and Sig2 are used as clocks of the DFF triggers. Sig1 is the reference signal, sig2 is the adjustment signal, and the RST signal is generated by the outputs of the two DFF flip-flops through the and gate.
When the rising edge of Sig1 comes, the output signal Q1 first becomes high, and then when the rising edge of Sig2 comes, the output signal Q2 also becomes high. At this point, with both Q1 and Q2 asserted, the RST signal is asserted, causing the DFF flip-flop to reset, turning both the Q1 and Q2 signals low. That is, when the rising edges of Sig1 and Sig2 are aligned, Q1 and Q2 are both low. The Q1 and Q2 signals reflect the phase difference between the Sig1 and Sig2 signals. If the phase of the signal Sig1 is ahead of the signal Sig2, Q1 is a pulse signal with a certain width, so that the charge pump continuously outputs the charging current, whereas if the phase of the signal Sig1 is behind the signal Sig2, the charge pump continuously discharges.
Provided with a charge pumpThe charging and discharging current of the circuit is Icp, and the phase difference of the reference signal minus the adjusting signal is
Wherein the content of the first and second substances,
the method mainly comprises a waveform data initial phase difference, an FPGA, a DAC internal delay error and the like.
The phase demodulation module outputs a current of
The loop filter module is a second-order passive low-pass filter and is composed of a resistor and a capacitor, so that the output current of the phase discrimination module is converted into a control voltage Vo similar to direct current, ripples and burrs of the control voltage are suppressed, and the implementation block diagram is shown in fig. 3.
When the charging current is increased, the Vo value is gradually increased in a step shape, otherwise, the Vo value is decreased in a step shape.
The impedance function of the loop filter module is Z(s) of
The value of the control voltage Vo is
The signal conditioning module is used for adjusting the gain of the control voltage and mainly comprises an operational amplifier.
Adjusting the expression as
Wherein, vtmax is the maximum value of the input voltage of the analog delay module, and Vomax is the maximum value of the output voltage of the signal conditioning module.
The analog delay module is mainly realized by an analog phase shifter and controls the delay amount of the signal through external voltage. The characteristic diagram of the phase shifter is simulated as shown in fig. 4.
The analog phase shifter characteristics can be expressed as
Wherein the content of the first and second substances,
kc is determined by the switching characteristics of the analog phase shifter, and Vt is the input voltage. />
As can be seen from the transmission characteristics of the DAC, the delay of the sampling clock is positively correlated with the delay of the output signal, when the phase delay of the reference signal is greater than the adjustment signal, i.e. when the phase delay of the reference signal is greater than the adjustment signal
Positive, the result of the calibration means is ≥ as can be seen from the equation given above>
Also positive, the delay of the adjustment signal is increased, whereby->
The value of (c) is decreased.
In the same way, when
When it is negative, it is selected>
Also negative, the adjustment signal delay is reduced so that->
The value of (a) increases.
Finally, the process is carried out in a batch,
the value of (a) will tend to zero and the phases of the two signals are aligned.
The locking detection module mainly comprises a direct current ADC (analog to digital converter), when the output phases are aligned, the loop filtering module outputs a stable direct current level, the state of the level is detected through the ADC, and when the level value is unchanged, circuit locking can be judged.
After the circuit is locked, the calibration device realizes the circuit state that the phase delay difference of two paths of waveform data is Ts/2, the phase delay of the DAC output waveform tends to 0, the values of the phase discrimination module and the analog phase shifter are not changed any more, and the phase delay difference of the two paths of channels is half of the period of a sampling clock. The calibration means will switch to the interleaving mode. The output selection module outputs the waveform data of the even number sampling points and the odd number sampling points to the two paths of DACs, the time delay between the two paths of DACs is unchanged, and the time delay meets the interweaving time sequence requirement.
Taking DAC interleaving of the return-to-zero hold function as an example, a schematic diagram is shown in fig. 5, two signals enter a power synthesis module through a microwave switch to be synthesized into one signal, and the one signal is output after filtering.
Example 2:
an embodiment 2 of the present disclosure provides an arbitrary waveform synthesis apparatus, including the time-domain interleaved waveform synthesis timing mismatch calibration apparatus described in embodiment 1 of the present disclosure.
The above description is only a preferred embodiment of the present disclosure and is not intended to limit the present disclosure, and various modifications and changes may be made to the present disclosure by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present disclosure should be included in the protection scope of the present disclosure.
Claims (10)
1. A time domain interweaving waveform synthesis time sequence mismatch calibration device is characterized by comprising a sine waveform generation module, two output selection modules, two DAC modules, a phase discrimination module, a loop filtering module, a signal conditioning module and an analog delay module;
the sinusoidal waveform generating module generates two paths of sinusoidal signals with the same frequency and phase delay difference of half a sampling period, one path is a reference signal, the other path is an adjusting signal, the phase delay difference Ts/2 of the two paths of sinusoidal signals is converted into sinusoidal analog signals after passing through the output selection module and the DAC module respectively, and then the sinusoidal analog signals enter the phase discrimination module through the microwave switch respectively;
the phase discrimination module extracts the phase difference of the two sinusoidal signals and converts the phase difference into a direct current signal, the loop filter module filters the noise of the direct current signal and converts the noise into a direct current voltage signal, the signal conditioning module adds gain for the direct current voltage signal so as to match the input voltage range of the analog delay module, the analog delay module generates corresponding delay amount according to the direct current voltage and delays the DAC sampling clock of the adjusting signal, and the phase difference of the two sinusoidal signals is infinitely close to zero.
2. The time-domain interleaved waveform synthesis timing mismatch calibration device according to claim 1, wherein the phase detection module comprises a phase detection circuit and a charge pump circuit, the phase detection circuit comprises two DFF flip-flops and an and gate, when the phase detection module is in operation, D terminals of the two DFF flip-flops are both set to a high level, the reference signal and the adjustment signal are respectively used as clock input signals of the two DFF flip-flops, and outputs of the two DFF flip-flops are connected to RST terminals of the DFF flip-flops after passing through the and gate;
the charge pump circuit comprises two constant current sources and two MOS tube control switches, and the two MOS tube control switches are respectively controlled by output signals of two DFF triggers of the phase discrimination circuit so as to realize the charge or discharge of the charge pump.
3. The apparatus of claim 1, further comprising a lock detection module, wherein the lock detection module is a dc ADC module, the dc ADC module is connected to an output of the loop filter module, the dc ADC module detects a state of a dc voltage output from the loop filter module, and determines that the circuit is locked when a level value is not changed;
or the two output selection modules respectively output the waveform data of the even number sampling points and the odd number sampling points to the two DAC modules, the two signals enter the power synthesis module through the microwave switch to be synthesized into one signal, and the one signal is output after passing through the low-pass filtering module.
4. A time-domain interleaved waveform synthesis timing mismatch calibration method, characterized by using the time-domain interleaved waveform synthesis timing mismatch calibration apparatus of any one of claims 1-3, the steps are as follows:
the sine waveform generating module generates sine waveform reference data and adjusting data with the initial phase delay difference of half a sampling period, the two paths of waveform data are converted into two paths of sine analog signals with the phase difference through the DAC module respectively, and the two paths of waveform analog signals reach the phase discrimination module through the microwave switch;
the phase discrimination module extracts the phase difference of the two paths of sinusoidal signals and converts the phase difference into a direct current signal, and the loop filtering module filters the noise of the direct current signal and converts the noise into a direct current voltage signal;
the signal conditioning module adds gain to the direct-current voltage to match the input voltage range of the analog delay module, and the analog delay module delays the DAC sampling clock of the adjusted signal according to the delay amount generated by the direct-current voltage, so that the phase difference of the two paths of sinusoidal signals is infinitely close to zero.
5. The method of time-domain interleaved waveform synthesis timing mismatch calibration according to claim 4, wherein when the phase difference between the reference signal and the adjustment signal is greater than zero, the phase discrimination module increases the output dc voltage, the analog delay module increases the delay of the sampling clock of the DAC, and the initial phase of the adjustment signal is increased, so that the phase difference is increased and approaches zero without limitation.
6. The method of time-domain interleaved waveform synthesis timing mismatch calibration according to claim 4, wherein when the phase difference between the reference signal and the adjustment signal is less than zero, the phase discrimination module outputs a reduced dc voltage, the analog delay module outputs a reduced DAC sampling clock delay amount, and the initial phase of the adjustment signal output is reduced, whereby the phase difference is reduced and approaches zero without limitation.
7. The time-domain interleaved waveform synthesis timing mismatch calibration method according to claim 4, wherein said analog delay block is implemented by an analog phase shifter characterized by:
wherein the content of the first and second substances,
kc is the transfer characteristic parameter of the analog phase shifter, and Vt is the output voltage of the signal conditioning module.
8. The time-domain interleaved waveform synthesis timing mismatch calibration method according to claim 7, wherein the output voltage Vt of the signal conditioning module is calculated by:
wherein Vtmax is the maximum value of the input voltage of the analog delay module, vomax is the maximum value of the output voltage of the signal conditioning module, and Vo is the control voltage output by the loop filter module;
further, the calculation method of the control voltage Vo output by the loop filter module is as follows:
wherein Z(s) is an impedance function of the loop filter module,
the output current of the phase discrimination module;
go toStep by step, phase discrimination module output current
The calculation method specifically comprises the following steps:
wherein Icp is the charge and discharge current of the charge pump circuit,
the phase difference of the adjustment signal is subtracted from the reference signal,
the method comprises the steps of waveform data initial phase difference, FPGA and DAC internal delay error.
9. The time-domain interleaved waveform synthesis timing mismatch calibration method according to claim 4, wherein after the direct current ADC module detects that the circuit is locked, values of the phase discrimination module and the analog delay module do not change any more, delay of two channels differs by half a sampling clock period, the output selection module outputs waveform data of even number samples and odd number samples to the two DAC modules, the two signals enter the power synthesis module through the microwave switch to be synthesized into one signal, and the filtered signal is output.
10. An arbitrary waveform synthesis apparatus comprising the time domain interleaved waveform synthesis timing mismatch calibration apparatus according to any one of claims 1 to 3, and calibrated by the time domain interleaved waveform synthesis timing mismatch calibration method according to any one of claims 4 to 9.
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| CN113805042B (en) * | 2021-09-17 | 2022-10-18 | 普源精电科技股份有限公司 | Time delay measuring device and testing method |
| CN115412089B (en) * | 2022-09-22 | 2024-04-09 | 中国科学院长春光学精密机械与物理研究所 | Automatic phase alignment method for demodulation switch signal |
| CN116991198B (en) * | 2023-09-28 | 2023-12-26 | 深圳市鼎阳科技股份有限公司 | Waveform generator, multi-signal channel delay correction method and medium |
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| CN1894854A (en) * | 2003-12-15 | 2007-01-10 | 皇家飞利浦电子股份有限公司 | Circuit arrangement and method for locking onto and/or processing data, in particular audio, television and/or video data |
| CN106502309A (en) * | 2016-11-15 | 2017-03-15 | 中国电子科技集团公司第四十研究所 | It is zeroed based on DA and keeps time domain intertexture random waveform synthesizer and the method for function |
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