CN112491420B

CN112491420B - High-speed high-resolution DA conversion circuit based on time interleaving

Info

Publication number: CN112491420B
Application number: CN202011351556.7A
Authority: CN
Inventors: 王锂; 陈文黎; 马敏
Original assignee: University of Electronic Science and Technology of China
Current assignee: University of Electronic Science and Technology of China
Priority date: 2020-11-27
Filing date: 2020-11-27
Publication date: 2021-11-02
Anticipated expiration: 2040-11-27
Also published as: CN112491420A

Abstract

The invention discloses a high-speed high-resolution DA conversion circuit based on time interleaving, which comprises: the device comprises a control module, a high-resolution DAC module, a channel amplitude calibration module, a high-speed analog switch switching module, a sampling holder module and a filtering output module; the control module, the high-resolution DAC module, the channel amplitude calibration module, the high-speed analog switch switching module, the sampling holder module and the filtering output module are sequentially connected. The invention utilizes the DAC chip with low sampling rate and high resolution to construct the DA conversion circuit with high sampling rate and high resolution to meet the requirement of ADC test, and solves the problem that the existing DAC chip is difficult to realize high resolution and high sampling rate at the same time.

Description

High-speed high-resolution DA conversion circuit based on time interleaving

Technical Field

The invention relates to the field of integrated circuits, in particular to a high-speed high-resolution DA conversion circuit based on time interleaving.

Background

The integrated circuit industry is comprised of design, manufacturing, packaging, and testing industries. The integrated circuit test is the last barrier to ensure the stability and reliability of the integrated circuit. Because the different levels of testing require different equipment and principles, the testing equipment and principles are also different. The principles and functions of testing are increasingly systematic and complex from device level to board level to system level. At this stage, chip testing has become the largest contributor to the cost of integrated circuit products.

Chip testing is divided into Digital chip testing, Analog chip testing and Digital-Analog hybrid chip testing according to chip types, wherein in the Digital-Analog hybrid chip testing, Analog-to-Digital Converter (ADC) chip testing is a type of chip mainly tested. According to the IEEE 1241 standard, a waveform with a resolution 3-4 bits higher than that of the ADC to be tested is used in the test of the ADC.

With the improvement of chip technology, the conversion rate and resolution of the ADC chip are higher and higher. At present, the resolution of the ADC in the high-precision acquisition system is mainly 16 bits, and the resolution of the audio ADC is mainly 16 bits to 24 bits, even 32-bit audio ADC. With the development, the testing mode of the ADC is also changing, but whether the evaluation board or the ATE test is adopted, a signal with higher resolution is required to be acquired by the ADC. While higher-precision analog signals are generally generated by a DA conversion circuit or an evaluation board in automatic test equipment, the existing DAC chip is difficult to simultaneously achieve high resolution and high sampling rate. For example: in the case of 24-bit high resolution, the sampling rate is generally very low, only a few hundred kilohertz; the resolution is low again at a high sampling rate of several hundred megabits, the highest of which is only 16 bits. For an audio ADC, the resolution is generally 24 bits, and for ADCs for other purposes, the resolution can reach 20 bits; during testing, signals with 24-bit high resolution and a frequency of tens of kilohertz waveforms are needed to be tested. And no high-resolution high-speed DAC chip capable of directly meeting the requirements exists in the market at present.

Disclosure of Invention

The invention provides a high-speed high-resolution DA conversion circuit based on time interleaving, which is realized by the following technical scheme:

a high-speed high-resolution DA conversion circuit based on time interleaving, comprising: the device comprises a control module, a high-resolution DAC module, a channel amplitude calibration module, a high-speed analog switch switching module, a sampling holder module and a filtering output module; the control module, the high-resolution DAC module, the channel amplitude calibration module, the high-speed analog switch switching module, the sampling holder module and the filtering output module are sequentially connected;

the control module is used for providing a digital signal and a clock signal for the high-resolution DAC module;

the multi-channel high-resolution DAC module is used for converting the digital signals given by the control module into analog signals and outputting analog waveforms;

the multichannel amplitude calibration module is used for calibrating the amplitude of the analog waveform output by the high-resolution DAC module;

the high-speed analog switch switching module is used for selecting the output analog waveform of each channel;

the sampling holder module is used for sampling and holding the output switched by the analog switch;

and the filtering output module is used for filtering the output waveform.

The DA conversion circuit with the high sampling rate and the high resolution is constructed by utilizing the existing DAC chip with the low sampling rate and the high resolution to meet the requirement of ADC test, and the function of the DA conversion circuit with the sampling rate f multiplied by N compared with the original DAC sampling rate f is realized under the condition of meeting the switching frequency of the multiplexer, namely the function of the high-speed and high-resolution DA conversion circuit is realized compared with the original high-resolution DAC.

Furthermore, the control module comprises an FPGA chip and a control circuit thereof, wherein the hardware circuit mainly comprises the FPGA chip, the FPGA configuration flash chip and the FPGA power supply module so as to ensure that the FPGA can normally work.

Furthermore, the output of the control module is a digital signal and a clock signal, and the digital signal is provided for the high-resolution DAC module.

The beneficial effect of the above further scheme is that the control module provides digital signals and clocks for the subsequent DAC units, and the digital signals obtained by each DAC unit are different and are related to each other.

Furthermore, the high-resolution DAC module includes a plurality of high-resolution DAC units with the same model parameter, each high-resolution DAC unit receives the digital signal output by the control module and converts the digital signal into an analog signal, and each high-resolution DAC unit operates at the same sampling frequency.

The further scheme has the advantages that the digital quantity given by the control module is converted into the analog quantity, the analog waveform is output, a plurality of sampling point data of the input signal are output through DA (digital-to-analog) to form, and the grouping is carried out on the sampling point data and is respectively given to each DAC to be output.

Furthermore, the digital signals generated by the control module are sequentially distributed to the high-resolution DACs according to the time sequence of the sampling points.

The further scheme has the beneficial effects that the input signals are sequentially distributed according to the sequence of the sampling time points, and the sampling rate of the original DA conversion circuit is increased.

Furthermore, the channel amplitude calibration module comprises channel amplitude calibration units with the same number as the high-resolution DAC units, and each high-resolution DAC unit is correspondingly connected with one channel amplitude calibration unit.

The effective result of the above further scheme is that the output of each channel has a difference, and if the output is directly switched to the switch switching module, the final output will have the condition of amplitude mismatch, and a burr will appear. The amplitude calibration module is required to perform amplitude calibration between multiple channels.

Further, the switching frequency of the high-speed analog switch switching module is expressed as:

F＝n*f；

f is the switching frequency of the high-speed analog switch switching module; n is the number of high-speed DAC units, and f is the sampling frequency of each high-speed DAC unit.

The beneficial effect of the above further scheme is that a higher sampling rate is achieved while the output is switched.

Further, the switching frequency of the high-speed analog switching module is the same as the sampling frequency of the sample and hold module.

The beneficial effect of the above further scheme is that the output of the high-speed analog switch switching module can be ensured to be consistent with the input of the sample holder module in period, and the output value of each high-speed analog switch switching module can be ensured to be completely input into the sample holder module.

Further, the switching conditions of the high-speed analog switch switching module are as follows:

and when the sampling updating of the output of any channel amplitude calibration unit is completed, the high-speed analog switch switching module switches the input channel to the current corresponding channel and inputs the output signal of the corresponding any channel amplitude calibration unit.

The beneficial effect of the above-mentioned further scheme is that the output of guaranteeing after every passageway calibration can both be gathered by the switch switching module the very first time to guarantee that the data that get into the switch switching module is the data of correct order.

Drawings

The accompanying drawings, which are included to provide a further understanding of the embodiments of the invention and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the invention and together with the description serve to explain the principles of the invention. In the drawings:

fig. 1 is a diagram showing a structure of a DA conversion circuit of the present invention.

FIG. 2 is a schematic diagram of sampling points according to an embodiment of the present invention.

Detailed Description

Hereinafter, the term "comprising" or "may include" used in various embodiments of the present invention indicates the presence of the invented function, operation or element, and does not limit the addition of one or more functions, operations or elements. Furthermore, as used in various embodiments of the present invention, the terms "comprises," "comprising," "includes," "including," "has," "having" and their derivatives are intended to mean that the specified features, numbers, steps, operations, elements, components, or combinations of the foregoing, are only meant to indicate that a particular feature, number, step, operation, element, component, or combination of the foregoing, and should not be construed as first excluding the existence of, or adding to the possibility of, one or more other features, numbers, steps, operations, elements, components, or combinations of the foregoing.

In various embodiments of the invention, the expression "or" at least one of a or/and B "includes any or all combinations of the words listed simultaneously. For example, the expression "a or B" or "at least one of a or/and B" may include a, may include B, or may include both a and B.

Expressions (such as "first", "second", and the like) used in various embodiments of the present invention may modify various constituent elements in various embodiments, but may not limit the respective constituent elements. For example, the above description does not limit the order and/or importance of the elements described. The foregoing description is for the purpose of distinguishing one element from another. For example, the first user device and the second user device indicate different user devices, although both are user devices. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of various embodiments of the present invention.

It should be noted that: if it is described that one constituent element is "connected" to another constituent element, the first constituent element may be directly connected to the second constituent element, and a third constituent element may be "connected" between the first constituent element and the second constituent element. In contrast, when one constituent element is "directly connected" to another constituent element, it is understood that there is no third constituent element between the first constituent element and the second constituent element.

The terminology used in the various embodiments of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the various embodiments of the invention. As used herein, the singular forms are intended to include the plural forms as well, unless the context clearly indicates otherwise. Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which various embodiments of the present invention belong. The terms (such as those defined in commonly used dictionaries) should be interpreted as having a meaning that is consistent with their contextual meaning in the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein in various embodiments of the present invention.

In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is further described in detail below with reference to examples and accompanying drawings, and the exemplary embodiments and descriptions thereof are only used for explaining the present invention and are not meant to limit the present invention.

Example 1

A high-speed high-resolution DA conversion circuit based on time interleaving, as shown in fig. 1, comprising: the device comprises a control module, a high-resolution DAC module, a channel amplitude calibration module, a high-speed analog switch switching module, a sampling holder module and a filtering output module; the control module, the high-resolution DAC module, the channel amplitude calibration module, the high-speed analog switch switching module, the sampling holder module and the filtering output module are sequentially connected;

the control module comprises an FPGA (field programmable gate array) and peripheral circuits thereof, wherein the control module mainly comprises a Series 7 series FPGA chip 325T, a flash chip with the model number of s25fl256 is configured for the FPGA, and an FPGA power supply module so as to ensure that the FPGA can normally work, and the output of the FPGA is a digital signal, a clock and a control signal. The main function of the digital-to-analog converter is to provide digital quantity for a plurality of high-resolution DAC modules, and the digital quantity of each DAC module is different and has correlation. Taking the case of two DAC modules as an example, assume that the digital signals generated by the FPGA are: s1, S2, S3, … …, S (2 n); the digital signal to DAC1 is the one corresponding to the original signal: s1, S3, S5, … … S (2 n-1); the digital signal to DAC2 is the one corresponding to the original signal: s2, S4, S6, … … S (2 n). In addition to providing digital values to the DAC, the control module also has control functions including: providing digital quantity for the multi-channel calibration module and controlling the gain of the channel; providing a control signal for the high-speed analog channel switching module to control channel switching; providing a control signal for the sample-and-hold module to control the switching of the sample-and-hold state;

the multi-channel high-resolution DAC module mainly comprises a high-resolution DAC and peripheral circuits thereof, specifically, the DAC is AKA4490EQ of AKM company, pins 2, 3, 4, 5 and 46 of the DAC are used as input pins to be connected to IO pins of a front-end FPGA, the multi-channel high-resolution DAC module has the main functions of converting digital quantity given by a control module into analog quantity, outputting analog waveforms, outputting the analog waveforms through pins 25, 26, 35 and 36, entering input pins of an operational amplifier and then outputting the analog waveforms to a rear end.

The multichannel amplitude calibration module mainly comprises a voltage-controlled gain attenuation amplifier and peripheral circuits thereof, specifically, the model of the voltage-controlled gain attenuation amplifier is AD8336, an input pin 4 of the voltage-controlled gain attenuation amplifier is connected to a front-end output signal, an input pin 11 is connected to an IO port of the control module through a conversion chip, a control signal is output by an FPGA of the control module, control voltage is generated through the conversion chip to control the amplification factor, amplitude attenuation amplification control of signals input by the pin 4 is realized, and further analog waveform amplitude output by the high-resolution DAC module is calibrated, because the output of each channel has difference, if the output is directly switched and output for the switch switching module, the condition that the amplitude is unmatched can occur in the final output, and burrs occur. The amplitude calibration module is required to perform amplitude calibration between multiple channels.

The high-speed analog switch switching module mainly comprises a multiplexer and peripheral circuits thereof, specifically, the type of the multiplexer is AD8184, pins 1, 3, 5 and 7 of the multiplexer are connected to the output of a front-end amplitude calibration module, each pin corresponds to one channel, pins 11, 12 and 13 of the multiplexer are connected to IO pins of an FPGA chip of a control module and used for receiving control signals of the control module, so that the function of selecting one of the pins 1, 3, 5 and 7 for output is realized, an output pin 10 of the multiplexer is connected to the rear end, the function of selecting and outputting analog waveforms output by each channel of the front end is realized, and a higher sampling rate is realized. The switching frequency of the high-speed analog switch has a certain relation with the number and frequency of the high-resolution DAC modules, and if the number of the high-resolution DAC modules is n and the sampling rate of each DAC is f, the switching frequency of the high-speed analog switch is n x f; the switching condition of the high-speed analog switch switching module is to satisfy the corresponding relation between the output and the channel, and the specific description is as follows:

when the output of any channel amplitude calibration unit is sampled and updated, the high-speed analog switch switching module switches an input channel to a current corresponding channel and inputs a corresponding output signal of any channel amplitude calibration unit; that is, when the frequency and the switching sequence of the high-speed switch switching module are established, the sampling update completion time points between the output channels of the front end, i.e., the channel amplitude calibration module, have a certain sequence, that is, according to the channel switching sequence, the time interval between every two adjacent output channel sampling update completion time points is the time length corresponding to the switching frequency of the switch switching module.

The sampling and holding module mainly comprises a sampling and holding device, specifically, the type of the sampling and holding device is AD783, an input pin 2 of the sampling and holding device is connected to a front-end output, a control pin 7 of the sampling and holding device is connected to an IO pin of a control module FPGA and used for receiving a control signal and realizing the function of sampling or holding a signal input by the pin 2, and an output pin 8 of the sampling and holding device is connected to a rear-end filtering module. The main function is to sample and hold the output after the analog switch is switched, and solve the problem of output amplitude attenuation caused in the switching process of the front-end switch. The state switching frequency of the sampling holder is consistent with the switching frequency of the high-speed analog switch switching module;

the filtering module mainly comprises a low-pass filter and mainly has the function of filtering an output waveform and improving the waveform quality.

Example 2

The DA conversion circuit in this embodiment is explained by data conversion of a waveform, and in this embodiment, a waveform is formed by a plurality of sampling point data through DA outputs, which are grouped and respectively given to each DAC output. Assuming that N DACs are provided, the total number of sampling points is S × N, S is an integer, and the digital quantity is in time sequence: d1, D2, D3, … …, D (S × N); we divide the total sample points into N groups of S data per group. As in fig. 2, assume that the first amount of data to DAC1 is D1, the first amount of data to DAC2 is D2, and so on, and the first amount of data to DACN is D (n). Then the D (N +1) data is sent to DAC1 again, the D (N +2) data is sent to DAC2, the cycle is repeated, the mth data quantity of the nth DAC is D (mN + N) data, and the induction and the collation are carried out, then:

the data amount corresponding to the first DAC is: d1, D (N +1), D (2N +1) … … D ((S-2) × N +1), D ((S-1) × N + 1);

the amount of data for the second DAC is: d2, D (N +2), D (2N +2) … … D ((S-2) × N +2), D ((S-1) × N + 2); the data amount corresponding to the third DAC is: d3, D (N +3), D (2N +3) … … D ((S-2) × N +3), D ((S-1) × N + 3);

by the analogy, the method can obtain the effect that,

the data amount corresponding to the Nth DAC is as follows: d (N), D (2N), D (3N) … … D ((S-1) × N), D (S × N);

thus, after the channel output is switched through the multiplexer, the channel output can be sequentially restored into digital quantity according to the sequence of the DAC output: d1, D2, D3, … … D (N +1), D (N +2), … … D (S × N).

Through the DA conversion circuit, the function of the DA conversion circuit with the sampling rate f multiplied by N compared with the original DAC sampling rate f can be realized under the condition of meeting the switching frequency of the multiplexer, namely the function of the high-speed high-resolution DA conversion circuit is realized compared with the original high-resolution DAC.

As will be appreciated by one skilled in the art, embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.

The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

The above-mentioned embodiments are intended to illustrate the objects, technical solutions and advantages of the present invention in further detail, and it should be understood that the above-mentioned embodiments are merely exemplary embodiments of the present invention, and are not intended to limit the scope of the present invention, and any modifications, equivalent substitutions, improvements and the like made within the spirit and principle of the present invention should be included in the scope of the present invention.

Claims

1. A high-speed high-resolution DA conversion circuit based on time interleaving, comprising: the device comprises a control module, a multi-channel high-resolution DAC module, a multi-channel amplitude calibration module, a high-speed analog switch switching module, a sampling holder module and a filtering output module; the control module, the multi-channel high-resolution DAC module, the multi-channel amplitude calibration module, the high-speed analog switch switching module, the sampling holder module and the filtering output module are sequentially connected;

and the filtering output module is used for filtering the output waveform.

2. The time-interleaving-based high-speed high-resolution DA conversion circuit according to claim 1, wherein the control module comprises an FPGA chip and a control circuit thereof, and the FPGA chip is configured with a flash chip and an FPGA power supply module to ensure that the FPGA can work normally.

3. The high-speed high-resolution DA conversion circuit based on time interleaving according to claim 2, wherein the multi-channel high-resolution DAC module comprises a plurality of high-resolution DAC units with the same model parameter, each high-resolution DAC unit respectively receives the digital signal output by the control module and converts the digital signal into an analog signal, and each high-resolution DAC unit works under the same sampling frequency.

4. The high-speed high-resolution DA conversion circuit based on time interleaving according to claim 3, wherein the digital signals generated by the control module are sequentially distributed to the plurality of high-resolution DAC units according to the time sequence of sampling points.

5. The high-speed high-resolution DA conversion circuit based on time interleaving according to claim 4, wherein the multi-channel amplitude calibration module comprises a same number of channel amplitude calibration units as the high-resolution DAC units, and each high-resolution DAC unit is correspondingly connected with one channel amplitude calibration unit.

6. The high-speed high-resolution DA conversion circuit based on time interleaving according to claim 5, wherein the switching frequency of the high-speed analog switching module is expressed as:

F＝n*f；

7. The high-speed high-resolution DA conversion circuit based on time interleaving according to claim 6, wherein the switching frequency of the high-speed analog switching module is the same as the sampling frequency of the sample holder module.

8. The high-speed high-resolution DA conversion circuit based on time interleaving according to claim 7, wherein the switching condition of the high-speed analog switch switching module is as follows: and when the output of any channel amplitude calibration unit is sampled and updated, the high-speed analog switch switching module switches the input channel to the current channel and inputs the output signal of the corresponding any channel amplitude calibration unit.