CN114157301A - Double-slope double-edge count-down analog-to-digital conversion device and conversion method thereof - Google Patents
Double-slope double-edge count-down analog-to-digital conversion device and conversion method thereof Download PDFInfo
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- CN114157301A CN114157301A CN202111512930.1A CN202111512930A CN114157301A CN 114157301 A CN114157301 A CN 114157301A CN 202111512930 A CN202111512930 A CN 202111512930A CN 114157301 A CN114157301 A CN 114157301A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/50—Analogue/digital converters with intermediate conversion to time interval
- H03M1/56—Input signal compared with linear ramp
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- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
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- H04N25/71—Charge-coupled device [CCD] sensors; Charge-transfer registers specially adapted for CCD sensors
- H04N25/75—Circuitry for providing, modifying or processing image signals from the pixel array
Abstract
The invention provides a double-slope double-edge count-down analog-to-digital conversion device and a conversion method thereof, wherein the device comprises a slope generator, a comparator, a high-speed clock, a low-speed clock, a digital logic circuit and a data processor; the slope generator is used for generating two slope signals with the same slope and opposite directions; inputting a pixel signal and two slope signals to two input ends of a comparator, calculating low-speed and high-speed clock counting pulses by a digital logic circuit according to an output signal of the comparator, a high-speed clock and a low-speed clock, calculating extra bit counting pulses according to a high-speed clock and a high-speed clock pulse control signal, and respectively inputting the extra bit counting pulses to a high-bit counter, a low-bit counter and an extra bit counter for counting downwards; the data processor calculates the quantized value of the pixel signal voltage according to the count values of the high counter, the low counter and the extra bit counter. The invention can reduce the power consumption of the ramp generator during resetting and the design complexity of the counter.
Description
Technical Field
The invention relates to the technical field of analog-to-digital conversion, in particular to a double-slope double-edge downward counting analog-to-digital conversion device and a conversion method thereof.
Background
Column-level Analog-to-Digital Converter (ADC) structures have been widely used in modern CMOS image sensor designs, and ramp ADCs are circuit structures commonly used in column-level ADCs. For a conventional dual-ramp ADC, ramp signals of the dual-ramp ADC are as shown in fig. 1, when a single pixel is converted, two ramp signals are serially output, a swing of the first ramp signal is small, a swing of the second ramp signal is large, directions of the two ramp signals are consistent, and slopes are the same. The first ramp signal is used to convert the reset voltage and the second ramp signal is used to reset the signal voltage.
An ideal dual-ramp signal and an actual dual-ramp signal of a conventional dual-ramp ADC are shown in fig. 2, a stabilization time required for resetting a first ramp signal from V1 to V0 is T1, and a stabilization time required for resetting a second ramp signal from V2 to V0 is T2, so that a stabilization time required for resetting the dual-ramp ADC is T1+ T2, and therefore, it is known that the stabilization time required for resetting the ramp signal is longer, the conversion time of the dual-ramp ADC is increased to a certain extent, and power consumption consumed for resetting the ramp signal is large.
The dual edge counting principle of the conventional dual ramp ADC is shown in fig. 3 and 4, and a dual edge dual clock is used to count the corresponding counting interval. The frequency of the two paths of clock signals is one high and one low, and the two paths of clock signals and the total counting interval generate low-speed counting pulses and high-speed counting pulses through the counting control logic unit.
The counting interval is counted by the low-speed clock in most time, and the high-speed clock is used for counting only when the overturning moment of the comparator and the falling edge of the low-speed clock are less than one low-speed clock period. This counting is similar to the length measurement reading with a ruler, first in centimeters and then in millimeters. There is no difference in accuracy from reading in millimeters at all, but the reading speed can be many times faster. The high-low two-path clocks with different frequencies are adopted for counting, so that the speed of analog-digital conversion cannot be increased, but the total counting times of the counter can be greatly reduced, and the reduction of power consumption is brought.
The counting interval required to count is counting interval 1 and counting interval 2, and the counter for counting the low-speed clock pulse counts up all the time. As can be seen from fig. 3, in the counting interval 1, the left-side pulse enabled by the low-speed clock pulse counts one less pulse. Similarly, in the counting interval 2, the low-speed clock pulse enables one more segment on the right side, that is, the high-speed clock pulse enables the corresponding waveform, so that the high-speed clock pulse needs to count up and then count down, thereby causing the high-order counter to have the counting function of both up and down.
The high-speed clock enable 1 and the high-speed clock enable 2 are delay signals in which the high-speed clock control signal is sampled by the falling edge and the rising edge of the high-speed clock, respectively. As can be seen from FIG. 4, one less clock edge is counted from the left end of the high-speed clock pulse enable 1 to the first flip edge of the comparator; while high speed clock enable 2 may capture the one clock edge counted less by high speed clock enable 1. Similarly, the rightmost edge of the high speed clock pulse enable 1 counts one more clock edge to the second flip edge of the comparator, while the high speed clock pulse enable 2 counts accurately.
Therefore, an extra bit counter is required to count up the least counted clock edge of the high speed clock pulse enable 1 and count down the most counted clock edge of the high speed clock pulse enable 1. Based on the count value of the extra bit counter, the high-speed clock pulse enable 1 and the high-speed clock pulse enable 2 are subjected to simple logic processing, and the clock edge counted least on the left side and the clock edge counted most on the right side of the high-speed clock pulse enable 1 are obtained. This requires an extra bit counter that also has the function of counting up and down.
Because the extra-position counter and the high-position counter need to have the counting functions of upward counting and downward counting at the same time, the design complexity of the counter is increased, and meanwhile, the layout area occupied by the counter is increased.
Disclosure of Invention
The invention aims to overcome the defects in the prior art and provides a double-slope double-edge count-down analog-digital conversion device and a conversion method thereof.
The invention provides a double-slope double-edge count-down analog-to-digital conversion device, which comprises a slope generator, a comparator, a high-speed clock, a low-speed clock, a digital logic circuit, a high-order counter, a low-order counter, an extra-order counter and a data processor, wherein the slope generator is connected with the comparator; the slope generator is used for generating a first slope signal and a second slope signal which have the same slope absolute value and opposite directions; the pixel signal output by the image sensor and the first ramp signal and the second ramp signal generated by the comparator are respectively used as two paths of input signals of the comparator, and the output signal of the comparator, the high-speed clock and the low-speed clock are respectively sent to the digital logic circuit; the digital logic circuit respectively samples local time periods of a first ramp signal and a second ramp signal by using a falling edge of a low-speed clock and a rising edge of a high-speed clock to obtain a high-order counting enable and a low-order counting enable, performs logic AND operation on the high-order counting enable and the low-speed clock to obtain a low-speed clock counting pulse, and performs logic AND operation on the low-order counting enable and the high-speed clock to obtain a high-speed clock counting pulse; the digital logic circuit also samples a high-speed clock pulse control signal synchronous with the low-bit counting enable by utilizing the rising edge and the falling edge of the high-speed clock to obtain two extra-bit counting enables, and performs logic AND operation on the two extra-bit counting enables to obtain extra-bit counting pulses; the high-order counter is used for counting down the counting pulse of the high-speed clock and transmitting the counting value to the data processor; the low-order counter is used for counting down the counting pulse of the low-speed clock and transmitting the counting value to the data processor; the extra bit counter is used for counting down the extra bit counting pulse and transmitting the counting value to the data processor; the data processor is used for calculating a quantized value of the pixel signal voltage according to a formula 2 x (a + Nb) + c; wherein a is the count value output by the high-order counter, b is the count value output by the low-order counter, c is the count value output by the extra-order counter, and N is the ratio of the frequency of the high-speed clock to the frequency of the low-speed clock.
Preferably, the first ramp signal gradually rises, and the second ramp signal gradually falls; or the first ramp signal gradually falls and the second ramp signal gradually rises.
Preferably, the comparator comprises a first current source, a second current source, a first voltage source, a second voltage source, a first switch, a second switch and a capacitor; one end of the first current source is connected to the power supply, the other end of the first current source is coupled to one end of the second current source, the other end of the second current source is grounded, one end of the first voltage source is grounded, the other end of the first voltage source is coupled to one end of the first switch, the other end of the first switch is coupled between the first current source and the second current source, one end of the second voltage source is grounded, the other end of the second voltage source is coupled to one end of the second switch, the other end of the second switch is coupled between the first switch and the second current source, the capacitor is coupled between the first switch and the second switch, and the other end of the capacitor is grounded.
Preferably, at time t0, closing the second switch resets the voltage between the first current source and the second current source to the voltage of the second voltage source; at time t1, the second switch and the first current source are opened, the second current source is closed at the same time, the second current source discharges the capacitor, the voltage of the capacitor linearly decreases along with time, and a first ramp signal is formed; at time t2, closing the first switch, resetting the voltage between the first current source and the second current source to the voltage of the first voltage source; at time t3, the first switch and the second current source are opened while the first current source is closed, the first current source charges the capacitor, and the voltage of the capacitor increases linearly with time to form a second ramp signal.
Preferably, at time t0, the first switch is closed, resetting the voltage between the first current source and the second current source to the voltage of the first voltage source; at time t1, the first switch and the second current source are opened, the first current source is closed, the first current source charges the capacitor, the voltage of the capacitor increases linearly with time, and a first ramp signal is formed; at time t2, closing the second switch, resetting the voltage between the first current source and the second current source to the voltage of the second voltage source; at time t3, the second switch and the first current source are opened while the second current source is closed, the second current source discharges the capacitor, and the voltage of the capacitor linearly decreases with time to form a second ramp signal.
Preferably, the digital logic circuit samples the time period between the starting time of the first ramp signal and the starting time of the second ramp signal to the turning time of the comparator by using the falling edge of the low-speed clock to obtain a high-order count enable; the digital logic circuit also respectively samples the time period from the starting time of the first ramp signal and the second ramp signal to the overturning time of the comparator by using the rising edge of the high-speed clock to obtain low-order counting enable.
The invention provides a double-slope double-edge down-counting analog-to-digital conversion method, which comprises the following steps:
s1, inputting a first ramp signal and a second ramp signal which have the same absolute value of slope and opposite directions and are generated by a ramp generator into one input end of a comparator, and inputting a pixel signal output by an image sensor into the other input end of the comparator;
s2, respectively sending the output signal of the comparator, the high-speed clock and the low-speed clock to the digital logic circuit, wherein the digital logic circuit respectively samples the local time periods of the first ramp signal and the second ramp signal by utilizing the falling edge of the low-speed clock and the rising edge of the high-speed clock to obtain a high-order counting enable and a low-order counting enable; the digital logic circuit also samples a high-speed clock pulse control signal synchronous with the low-bit counting enable by utilizing the rising edge and the falling edge of the high-speed clock to obtain two extra-bit counting enables;
s3, carrying out logic AND operation on the high-order counting enable and the low-speed clock through a digital logic circuit to obtain low-speed clock counting pulses, carrying out logic AND operation on the low-order counting enable and the high-speed clock to obtain high-speed clock counting pulses, and carrying out logic AND operation on two extra-order counting enables to obtain extra-order counting pulses;
s4, counting down the high-speed clock counting pulse by adopting a high-order counter, and transmitting the counting value to a data processor; counting down the counting pulse of the low-speed clock by adopting a low-order counter, and transmitting the counting value to a data processor; an extra bit counter is adopted to count down extra bit counting pulses and transmit the count value to a data processor;
s5, the data processor calculates the quantized value of the pixel signal voltage according to the formula 2 (a + Nb) + c; wherein a is the count value output by the high-order counter, b is the count value output by the low-order counter, c is the count value output by the extra-order counter, and N is the ratio of the frequency of the high-speed clock to the frequency of the low-speed clock.
Preferably, the first ramp signal gradually rises, and the second ramp signal gradually falls; or the first ramp signal gradually falls and the second ramp signal gradually rises.
Preferably, the comparator comprises a first current source, a second current source, a first voltage source, a second voltage source, a first switch, a second switch and a capacitor; one end of the first current source is connected to a power supply, the other end of the first current source is coupled with one end of the second current source, the other end of the second current source is grounded, one end of the first voltage source is grounded, the other end of the first voltage source is coupled with one end of the first switch, the other end of the first switch is coupled between the first current source and the second current source, one end of the second voltage source is grounded, the other end of the second voltage source is coupled with one end of the second switch, the other end of the second switch is coupled between the first switch and the second current source, the capacitor is coupled between the first switch and the second switch, and the other end of the capacitor is grounded; at time t0, closing the second switch, resetting the voltage between the first current source and the second current source to the voltage of the second voltage source; at time t1, the second switch and the first current source are opened, the second current source is closed at the same time, the second current source discharges the capacitor, the voltage of the capacitor linearly decreases along with time, and a first ramp signal is formed; at time t2, closing the first switch, resetting the voltage between the first current source and the second current source to the voltage of the first voltage source; at time t3, the first switch and the second current source are opened while the first current source is closed, the first current source charges the capacitor, and the voltage of the capacitor increases linearly with time to form a second ramp signal.
Preferably, the comparator comprises a first current source, a second current source, a first voltage source, a second voltage source, a first switch, a second switch and a capacitor; one end of the first current source is connected to a power supply, the other end of the first current source is coupled with one end of the second current source, the other end of the second current source is grounded, one end of the first voltage source is grounded, the other end of the first voltage source is coupled with one end of the first switch, the other end of the first switch is coupled between the first current source and the second current source, one end of the second voltage source is grounded, the other end of the second voltage source is coupled with one end of the second switch, the other end of the second switch is coupled between the first switch and the second current source, the capacitor is coupled between the first switch and the second switch, and the other end of the capacitor is grounded; at time t0, closing the first switch, resetting the voltage between the first current source and the second current source to the voltage of the first voltage source; at time t1, the first switch and the second current source are opened, the first current source is closed, the first current source charges the capacitor, the voltage of the capacitor increases linearly with time, and a first ramp signal is formed; at time t2, closing the second switch, resetting the voltage between the first current source and the second current source to the voltage of the second voltage source; at time t3, the second switch and the first current source are opened while the second current source is closed, the second current source discharges the capacitor, and the voltage of the capacitor linearly decreases with time to form a second ramp signal.
Preferably, in step S2, the digital logic circuit samples the time periods between the start times of the first and second ramp signals and the inversion time of the comparator with the falling edge of the low-speed clock to obtain the high count enable; the digital logic circuit also respectively samples the time period from the starting time of the first ramp signal and the second ramp signal to the overturning time of the comparator by using the rising edge of the high-speed clock to obtain low-order counting enable.
Compared with the prior art, the invention can achieve the following technical effects:
1. compared with the double-slope signals with the same slope and the same direction, the double-slope signals with the same absolute value of slope and the opposite direction can accelerate the stabilization time of the slope signals, thereby reducing the time required by the conversion of the double-slope ADC to a certain extent and simultaneously reducing the power consumption required by the reset of the slope generator.
2. The invention adopts a counting mode of double-edge double-clock and only counting downwards at the same time, so that the high-order counter and the extra-order counter only have the function of counting downwards, and compared with the double-edge double-clock counter which needs to count upwards and downwards at the same time, the design complexity of the counter is reduced, and the layout area of the counter can be greatly saved.
Drawings
FIG. 1 is a schematic diagram of a ramp signal of a conventional dual ramp ADC;
FIG. 2 is a schematic diagram of an ideal dual ramp signal versus an actual dual ramp signal for a conventional dual ramp ADC;
FIGS. 3 and 4 are schematic diagrams of the dual edge counting of a conventional dual ramp ADC;
FIG. 5 is a block diagram of a dual-slope dual-edge count-down analog-to-digital conversion apparatus according to an embodiment of the present invention;
FIG. 6 is a schematic diagram of a ramp generator according to one embodiment of the invention;
FIG. 7 is a waveform diagram of a dual ramp signal generated by a ramp generator according to an embodiment of the present invention;
FIG. 8 is a waveform diagram of a bottom-in-back dual ramp signal generated by a ramp generator according to one embodiment of the present invention;
FIG. 9 is a graph illustrating the comparison of the waveforms of a bottom-last-up dual ramp signal with a conventional dual ramp signal, in accordance with one embodiment of the present invention;
FIG. 10 is a schematic diagram of a dual ramp signal count time period according to one embodiment of the present invention;
FIG. 11 is a timing diagram illustrating the manner in which the up-ramp signal is counted followed by the down-ramp signal according to an embodiment of the present invention;
FIG. 12 is a timing diagram illustrating an up-down double edge counting scheme according to one embodiment of the present invention;
fig. 13 is a timing diagram illustrating a manner in which a bottom-last dual ramp signal is counted, according to an embodiment of the invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention will be described in further detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not to be construed as limiting the invention.
Fig. 5 shows an overall architecture of a dual-ramp dual-edge count-down analog-to-digital conversion apparatus according to an embodiment of the present invention.
As shown in fig. 5, the dual-slope dual-edge count-down analog-to-digital conversion apparatus provided by the embodiment of the present invention includes: the circuit comprises a ramp generator, a comparator, a high-speed clock, a low-speed clock, a digital logic circuit, a high-order counter, a low-order counter, an extra-order counter and a data processor; the slope generator is used for generating two slope signals with the same slope absolute value and opposite directions; two ramp signals generated by a ramp generator are used as one path of input signals of a comparator and input into one input end of the comparator, and a pixel signal output by an image sensor is used as the other path of input signals of the comparator and input into the other input end of the comparator; the output signal of the comparator, the high-speed clock and the low-speed clock are respectively sent to the digital logic circuit.
The digital logic circuit respectively samples the time period from the starting time of the two ramp signals to the turning time of the comparator by using the falling edge of the low-speed clock to obtain high-order counting enable, and performs logic AND operation on the high-order counting enable and the low-speed clock to obtain low-speed clock counting pulses.
The digital logic circuit also uses the rising edge of the high-speed clock to respectively sample the time period from the starting time of the two ramp signals to the turning time of the comparator to obtain the low-order counting enable, and carries out logic AND operation on the low-order counting enable and the high-speed clock to obtain the high-speed clock counting pulse.
The digital logic circuit also samples the high-speed clock pulse control signal synchronous with the low-bit counting enable by utilizing the rising edge and the falling edge of the high-speed clock to obtain two extra-bit counting enables, and performs logic AND operation on the two extra-bit counting enables to obtain extra-bit counting pulses.
The high counter is used for counting down the high-speed clock counting pulse and transmitting the counting value to the data processor.
The low counter is used for counting down the counting pulse of the low-speed clock and transmitting the counting value to the data processor.
The extra bit counter is used to count down the extra bit count pulses.
The data processor is used for calculating a quantized value of the pixel signal voltage according to a formula 2 x (a + Nb) + c; wherein a is the count value output by the high-order counter, b is the count value output by the low-order counter, c is the count value output by the extra-order counter, and N is the ratio of the frequency of the high-speed clock to the frequency of the low-speed clock.
The key point of the invention is the structure of the ramp generator, and two ramp signals with the same slope absolute value and opposite directions are generated by the ramp generator.
Fig. 6 shows the structure of a ramp generator according to one embodiment of the invention.
As shown in fig. 6, the ramp generator includes a first current source Q1, a second current source Q2, a first voltage source U1, a second voltage source U2, a first switch S1, a second switch S2, and a capacitor C; wherein, the current magnitudes of the first current source Q1 and the second current source Q2 are equal to each other and are set to I, the voltage of the first voltage source U1 is V0, the voltage of the second voltage source U2 is V2, one end of the first current source Q1 is connected to a power source, the other end of the first current source Q1 is coupled to one end of the second current source Q2, the other end of the second current source Q2 is grounded, one end of the first voltage source U1 is grounded, the other end of the first voltage source U1 is coupled to one end of the first switch S1, the other end of the first switch S1 is coupled between the first current source Q1 and the second current source Q2, one end of the second voltage source U2 is grounded, the other end of the second voltage source U2 is coupled to one end of the second switch S2, the other end of the second switch S2 is coupled between the first switch S1 and the second current source Q2, the node of the first switch S1, the node 1 of the first switch Q638 and the node 2 of the second switch Q2, the other end of the capacitor C is grounded.
By controlling the first current source Q1, the second current source Q2, the first switch S1 and the second switch S2, two kinds of dual ramp signals can be generated, the first kind is a dual ramp signal that rises first and then falls (i.e., the first ramp signal is directed upward and the second ramp signal is directed downward), and the second kind is a dual ramp signal that falls first and then rises (i.e., the first ramp signal is directed downward and the second ramp signal is directed upward).
Fig. 7 shows waveforms of up-and-down dual ramp signals generated by the ramp generator according to an embodiment of the present invention.
As shown in fig. 7, the up-and-down dual-ramp signal means that the direction of the first ramp signal is upward, the direction of the second ramp signal is downward, and the principle of generating the up-and-down dual-ramp signal is as follows:
at time t1, the first switch S1 is closed, and the voltage V between the first current source Q1 and the second current source Q2rampV0 reset to first voltage source U1; at time t2, the first switch S1 and the second current source Q2 are opened while the first current source Q1 is closed, the first current source Q1 charges the capacitor C to time t3, and the voltage of the capacitor C increases linearly with the charging time to form a first ramp signal.
At this time VrampDescribed as follows by the formula: vrampV0+ M · I · (t3-t 2); where V0 represents the initial voltage of the first ramp signal, I represents the charging current of the capacitor C, M represents the integration capacitance of the capacitor C, and (t3-t2) represents the integration time of the capacitor C.
At time t3, the second switch S2 is closed, V is openedrampReset to the voltage V2 of the second voltage source U2; at time t4, the second switch S2 and the first current source Q1 are opened while the second current source Q2 is closed, the second current source Q2 discharges the capacitor C to time t5, and the voltage of the capacitor C linearly decreases with the discharge time, forming a second ramp signal.
At this time VrampDescribed as follows by the formula: vrampV2+ M · I · (t5-t 4); where V2 represents the initial voltage of the second ramp signal, I represents the discharge current of the second current source Q2, M represents the integration capacitance of the capacitor C, and (t5-t4) represents the integration time of the capacitor C.
Fig. 8 shows waveforms of down-first and up-last dual ramp signals generated by a ramp generator according to an embodiment of the present invention.
As shown in fig. 8, the generation principle of the down-first and up-last dual ramp signal is as follows:
at time t1, the second switch S2 is closed, V is openedrampReset to the voltage V2 of the second voltage source U2; at time t2, the second switch S2 and the first current source Q1 are opened while the second current source Q2 is closed, the second current source Q2 discharges the capacitor C to time t3, and the voltage of the capacitor C linearly decreases with the discharge time, forming a first ramp signal.
At this time VrampDescribed as follows by the formula: vrampV2-M · I · (t3-t 2); where V2 represents the initial voltage of the first ramp signal, I represents the discharge current of the second current source Q2, M represents the integration capacitance of the capacitor C, and (t2-t1) represents the integration time of the capacitor C.
At time t3, the first switch S1 is closed, V is openedrampReset to the voltage V0 of the first voltage source U1; at time t4, the first switch S1 and the second current source Q2 are opened while the first current source Q1 is closed, the first current source Q1 charges the capacitor C, and the capacitor C is chargedThe voltage of C increases linearly with the charging time, forming a second ramp signal.
At this time VrampDescribed as follows by the formula: vrampV0+ M · I · (t5-t 4); where V0 represents the initial voltage of the second ramp signal, I represents the charging current of the capacitor C, M represents the integration capacitance of the capacitor C, and (t5-t4) represents the integration time of the capacitor C.
The two double-slope signals are ideal double-slope signals, but actually generated double-slope signals also need a certain stabilization time,
compared with the traditional double-slope signal, the double-slope signal generated by the slope generator provided by the invention has the advantage of shortening the stabilization time during resetting.
Fig. 9 shows a waveform comparison result of a bottom-last-up dual ramp signal according to an embodiment of the present invention with a conventional dual ramp signal.
As shown in fig. 9, the present invention takes the dual-ramp signal of first falling and then rising as an example, and compared with the waveform of the conventional dual-ramp signal, the dual-ramp signal of first rising and then falling is known in the same way.
Fig. 9 (a) shows a conventional ideal dual-ramp signal, fig. 9 (b) shows a conventional actual dual-ramp signal, the stabilization time T1 required by the voltage from V1 to V0, the stabilization time T2 required by the voltage from V2 to V0, and the stabilization time required by the two ramp signals is T1+ T2.
Fig. 9 (c) is an ideal double ramp signal of the present invention, fig. 9 (d) is an actual double ramp signal of the present invention, and the time T required for the voltage to go from V1 to V2 is the settling time.
Comparing (b) and (d), when other conditions (slope rate and swing amplitude, etc.) are the same, it is not difficult to find that T < T1+ T2, that is, the dual-slope signal of the present invention can reduce the settling time of signal reset, thereby reducing the conversion time of the dual-slope ADC and reducing the power consumption required by the reset of the slope generator.
Fig. 10 illustrates the principle of a double ramp signal counting period according to one embodiment of the invention.
As shown in fig. 10, (a) in fig. 10 is a bottom-first and top-second dual ramp signal, and (b) in fig. 10 is a top-first and bottom-second dual ramp signal. The two double-slope signals for realizing related double sampling require difference operation on the reset voltage and the signal voltage of the pixel, namely the value of (VSIG-VRST), and the counting time period corresponding to (VSIG-VRST) is (t6-t5) - (t2-t1), and the arrangement can be obtained:
(t6-t5)-(t2-t1)＝[(t6-t4)-(t5-t4)]-(t2-t1)＝(t6-t4)-[(t5-t4)+(t2-t1)]。
wherein, the time period corresponding to (t6-t4) is a known quantity and can be obtained by digital logic circuit processing. The time period to be counted is- [ (t5-t4) + (t2-t1) ], i.e. from the start of the first ramp signal to the first flip edge of the comparator plus from the start of the second ramp signal to the second flip edge of the comparator.
Fig. 11 shows the timing of the counting mode of the up-and-down dual ramp signal according to an embodiment of the present invention.
As shown in fig. 11, the digital logic circuit respectively samples the time period from the start time of the first ramp signal and the second ramp signal to the inversion time of the comparator by using the falling edge of the low-speed clock to obtain the low-speed clock pulse enable (i.e., the high count enable), and logically and-operates the low-speed clock pulse enable and the low-speed clock to obtain the low-speed clock count pulse. And sending the counting pulse of the low-speed clock to a low-order counter, and counting down the counting pulse of the low-speed clock by the low-order counter.
The digital logic circuit also respectively samples the time period from the starting time of the first ramp signal and the second ramp signal to the overturning time of the comparator by using the rising edge of the high-speed clock to obtain a high-speed clock pulse enable (namely, a low-order counting enable), and performs logic AND operation on the high-speed clock pulse enable and the high-speed clock to obtain a high-speed clock counting pulse. And sending the high-speed clock counting pulse to a high-order counter, and counting down the high-speed clock counting pulse through the high-order counter.
As can be seen from fig. 11, the counting interval in which the first ramp signal needs to be counted is the counting interval 1, and the counting interval in which the second ramp signal needs to be counted is the counting interval 2. For counting interval 1, the first pulse signal enabled by the low-speed clock pulse has more sections to the right, and therefore the section needs to be subtracted, and the section counts down by using the high-speed clock counting pulse. Similarly, for the counting interval 2, the right side of the second pulse signal enabled by the low-speed clock pulse counts a section as much, and the section counts down by adopting the high-speed clock counting pulse, so that the high-order counter only needs to count down.
FIG. 12 illustrates a timing sequence of a top-down double edge count mode according to one embodiment of the invention.
As shown in fig. 12, the digital logic circuit further samples the high-speed clock pulse control signal by using the rising edge and the falling edge of the high-speed clock to obtain an extra bit count enable 1 and an extra bit count enable 2, performs a logical and operation on the extra bit count enable 1 and the extra bit count enable 2 to obtain an extra bit count pulse, sends the extra bit count pulse to the extra bit counter, and counts down the extra bit count pulse by the extra bit counter.
The high speed clock control signal is synchronized with the low count enable, and the high speed clock control signal is actually the difference between the two ramp signals (the first ramp signal and the second ramp signal) and the low speed clock enable, corresponding to the section of the counting interval 1 and 2.
One more clock edge is counted from the rightmost end of the first pulse of the extra bit count enable 1 to the first flip edge of the comparator (i.e. the flip edge of the first ramp signal); while the extra bit count enables 2 counts to be accurate. Similarly, the rightmost end of the second pulse of the extra bit count enable 1 counts one more clock edge from the second flip edge of the comparator (i.e., the flip edge of the second ramp signal), and the extra bit count enable 2 counts accurately.
Therefore, the extra bit count enable 1 and the extra bit count enable 2 are logically AND-ed to obtain extra bit count pulses, the extra bit count pulses are counted down through the extra bit counter, and the clock edge number counted by the first pulse of the extra bit count enable 1 and the rightmost end of the second pulse is subtracted. The extra bit counter only needs to have a count down function.
Compared with the traditional double-edge counting mode of the double-slope ADC shown in FIGS. 3 and 4, the high-order counter and the extra-order counter only need to have a down-counting function and do not need to have an up-counting function, so that the design complexity of the high-order counter and the extra-order counter can be reduced, and the layout area of the high-order counter and the extra-order counter can be greatly saved.
Fig. 13 shows the timing of the manner in which the down-first and up-last dual ramp signals are counted, according to one embodiment of the invention.
As shown in fig. 13, like the upper-lower dual-ramp signal, the two counting intervals of the upper-lower dual-ramp signal are a counting interval 1 (corresponding to the counting interval of the first ramp signal to be counted) and a counting interval 2 (corresponding to the counting interval of the second ramp signal to be counted), and the right side of the first pulse signal enabled by the low-speed clock pulse counts one more segment, so that the segment needs to be subtracted, and the segment uses the high-speed clock counting pulse to count down. Similarly, for the counting interval 2, the right side of the second pulse signal enabled by the low-speed clock pulse counts a section more, and the section also counts down by using the high-speed clock, so that the high-order counter only needs to count down.
The timing sequence of the first-lower-to-upper double edge counting mode is the same as the timing sequence of the first-upper-to-lower double edge counting mode, referring to fig. 12, for the first-lower-to-upper double slope signal, it is also necessary to count down the extra bit counting pulse by the extra bit counter, and compensate the clock edge number counted most on the right side of the first pulse and the second pulse of the extra bit counting enable 1, so that the extra bit counter only needs to have the function of counting down.
The high-order counter and the extra-order counter do not need to have a counting-down function, so that the design complexity of the high-order counter and the extra-order counter is reduced, and the layout area of the high-order counter and the extra-order counter can be greatly saved.
Respectively transmitting the count value output by the high counter, the count value output by the low counter and the count value output by the extra counter to a data processor, wherein the data processor is used for calculating to obtain the quantized value of the pixel signal voltage according to a formula 2 x (a + Nb) + c; where a is the count value output by the high-order counter, b is the count value output by the low-order counter, c is the count value output by the extra-order counter, and N is the ratio of the frequency of the high-speed clock to the frequency of the low-speed clock (i.e., the high-speed clock frequency is N times the low-speed clock frequency).
The above details describe the structure and the working principle of the analog-to-digital conversion apparatus with double slopes and double edges counting down, and the present invention also provides an analog-to-digital conversion method implemented by using the apparatus.
The double-slope double-edge count-down analog-to-digital conversion method provided by the embodiment of the invention comprises the following steps:
s1, inputting the first and second ramp signals generated by the ramp generator with the same absolute value of slope and opposite directions to one input terminal of the comparator, and inputting the pixel signal output by the image sensor to the other input terminal of the comparator.
The structure of the ramp generator and the principle of the generated dual ramp signal refer to the related description in the above conversion device and fig. 6-8.
The comparison result between the dual-slope signal with the same absolute value of slope and the opposite direction and the conventional dual-slope signal is shown in fig. 9, and compared with the conventional dual-slope signal, the dual-slope signal with the same absolute value of slope and the opposite direction can accelerate the stabilization time of the slope signal, thereby reducing the time required for the conversion of the dual-slope ADC to a certain extent.
S2, respectively sending the output signal of the comparator, the high-speed clock and the low-speed clock to the digital logic circuit, wherein the digital logic circuit respectively samples the local time periods of the first ramp signal and the second ramp signal by utilizing the falling edge of the low-speed clock and the rising edge of the high-speed clock to obtain a high-order counting enable and a low-order counting enable; the digital logic circuit also samples the high speed clock pulse control signal synchronized with the low bit count enable with the rising and falling edges of the high speed clock to obtain two additional bit count enables.
The digital logic circuit respectively samples the time period from the starting time of the first ramp signal and the second ramp signal to the overturning time of the comparator by using the falling edge of the low-speed clock to obtain high-order counting enable.
The digital logic circuit respectively samples the time period from the starting time of the first ramp signal and the second ramp signal to the overturning time of the comparator by using the rising edge of the high-speed clock to obtain the low-order counting enable.
The high-speed clock pulse control signal is actually the difference between the two ramp signals (the first ramp signal and the second ramp signal) and the low-speed pulse enable, corresponding to the section of the counting interval 1 and 2 which counts more.
And S3, performing logic AND operation on the high-order counting enable and the low-speed clock through the digital logic circuit to obtain low-speed clock counting pulses, performing logic AND operation on the low-order counting enable and the high-speed clock to obtain high-speed clock counting pulses, and performing logic AND operation on two extra-order counting enables to obtain extra-order counting pulses.
S4, counting down the high-speed clock counting pulse by adopting a high-order counter, and transmitting the counting value to a data processor; counting down the counting pulse of the low-speed clock by adopting a low-order counter, and transmitting the counting value to a data processor; an extra bit counter is used to count down the extra bit count pulses and transmit the count value to the data processor.
The principle of the double-edge counting of the double-slope signals with the same absolute value of the slope and opposite directions is shown in fig. 10-13, and compared with the traditional double-slope counting mode, the high-order counter and the extra-order counter only need to have a down-counting function and do not need to have an up-counting function, so that the design complexity of the high-order counter and the extra-order counter can be reduced, and the layout area of the extra-order counter can be greatly saved.
S5, the data processor calculates the quantized value of the pixel signal voltage according to the formula 2 (a + Nb) + c; wherein a is the count value output by the high-order counter, b is the count value output by the low-order counter, c is the count value output by the extra-order counter, and N is the ratio of the frequency of the high-speed clock to the frequency of the low-speed clock.
In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples and features of different embodiments or examples described in this specification can be combined and combined by one skilled in the art without contradiction.
Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention, and that variations, modifications, substitutions and alterations can be made to the above embodiments by those of ordinary skill in the art within the scope of the present invention.
The above embodiments of the present invention should not be construed as limiting the scope of the present invention. Any other corresponding changes and modifications made according to the technical idea of the present invention should be included in the protection scope of the claims of the present invention.
Claims (11)
1. A kind of double slope double edge counts the analog-to-digital conversion device downward, characterized by, including the ramp generator, comparator, high-speed clock, low-speed clock, digital logic circuit, high order counter, low order counter, extra bit counter and data processor; wherein the content of the first and second substances,
the slope generator is used for generating a first slope signal and a second slope signal which have the same slope absolute value and opposite directions; respectively taking a pixel signal output by an image sensor and a first ramp signal and a second ramp signal generated by the comparator as two paths of input signals of the comparator, and respectively sending an output signal of the comparator, the high-speed clock and the low-speed clock to the digital logic circuit;
the digital logic circuit respectively samples local time periods of the first ramp signal and the second ramp signal by using a falling edge of the low-speed clock and a rising edge of the high-speed clock to obtain a high-order counting enable and a low-order counting enable, performs logic AND operation on the high-order counting enable and the low-speed clock to obtain a low-speed clock counting pulse, and performs logic AND operation on the low-order counting enable and the high-speed clock to obtain a high-speed clock counting pulse;
the digital logic circuit also samples a high-speed clock pulse control signal synchronous with the low-order counting enable by utilizing the rising edge and the falling edge of the high-speed clock to obtain two extra-order counting enables, and performs logic AND operation on the two extra-order counting enables to obtain extra-order counting pulses;
the high-order counter is used for counting down the high-speed clock counting pulse and transmitting a counting value to the data processor;
the low-order counter is used for counting down the counting pulse of the low-speed clock and transmitting a counting value to the data processor;
the extra bit counter is used for counting down the extra bit counting pulse and transmitting a counting value to the data processor;
the data processor is used for calculating a quantized value of the pixel signal voltage according to a formula 2 x (a + Nb) + c; wherein a is a count value output by the high-order counter, b is a count value output by the low-order counter, c is a count value output by the extra-order counter, and N is a ratio of the frequency of the high-speed clock to the frequency of the low-speed clock.
2. The dual-ramp dual-edge down-count analog-to-digital conversion device of claim 1, wherein the first ramp signal gradually rises and the second ramp signal gradually falls; or the first ramp signal gradually falls and the second ramp signal gradually rises.
3. The dual slope dual edge count down analog to digital conversion device of claim 2, wherein said comparator comprises a first current source, a second current source, a first voltage source, a second voltage source, a first switch, a second switch, and a capacitor; the power supply is connected to one end of the first current source, the other end of the first current source is coupled to one end of the second current source, the other end of the second current source is grounded, one end of the first voltage source is grounded, the other end of the first voltage source is coupled to one end of the first switch, the other end of the first switch is coupled between the first current source and the second current source, one end of the second voltage source is grounded, the other end of the second voltage source is coupled to one end of the second switch, the other end of the second switch is coupled between the first switch and the second current source, the capacitor is coupled between the first switch and the second switch, and the other end of the capacitor is grounded.
4. The dual slope dual edge count down analog to digital conversion device of claim 3, wherein at time t0, said second switch is closed, resetting the voltage between said first current source and said second current source to the voltage of said second voltage source; at time t1, opening the second switch and the first current source while closing the second current source, the second current source discharging the capacitor, the voltage of the capacitor decreasing linearly with time, forming the first ramp signal;
at time t2, closing the first switch, resetting the voltage between the first current source and the second current source to the voltage of the first voltage source; at time t3, the first switch and the second current source are opened while the first current source is closed, the first current source charges the capacitor, and the voltage of the capacitor increases linearly with time to form the second ramp signal.
5. The dual slope dual edge count down analog to digital conversion device of claim 3, wherein at time t0, said first switch is closed, resetting the voltage between said first current source and said second current source to the voltage of said first voltage source; at time t1, opening the first switch and the second current source while closing the first current source, the first current source charging a capacitor whose voltage increases linearly with time, forming the first ramp signal;
at time t2, closing the second switch, resetting the voltage between the first current source and the second current source to the voltage of the second voltage source; at time t3, the second switch and the first current source are opened while the second current source is closed, the second current source discharges the capacitor, and the voltage of the capacitor linearly decreases with time to form the second ramp signal.
6. The dual-slope dual-edge down-counting analog-to-digital conversion device of claim 1, wherein the digital logic circuit respectively samples a time period from a start time of the first slope signal and a start time of the second slope signal to a flip time of the comparator by using a falling edge of the low-speed clock to obtain a high-count enable;
the digital logic circuit also respectively samples the time period from the starting time of the first ramp signal and the second ramp signal to the overturning time of the comparator by utilizing the rising edge of the high-speed clock to obtain low-order counting enable.
7. A double-slope double-edge count-down analog-to-digital conversion method is characterized by comprising the following steps:
s1, inputting a first ramp signal and a second ramp signal which have the same absolute value of slope and opposite directions and are generated by a ramp generator into one input end of a comparator, and inputting a pixel signal output by an image sensor into the other input end of the comparator;
s2, respectively sending the output signal of the comparator, a high-speed clock and a low-speed clock to a digital logic circuit, wherein the digital logic circuit respectively samples the local time periods of the first ramp signal and the second ramp signal by using the falling edge of the low-speed clock and the rising edge of the high-speed clock to obtain a high-order counting enable and a low-order counting enable; the digital logic circuit also samples a high-speed clock pulse control signal synchronous with the low-bit counting enable by utilizing the rising edge and the falling edge of the high-speed clock to obtain two extra-bit counting enables;
s3, performing logic AND operation on the high-order counting enable and the low-speed clock through the digital logic circuit to obtain a low-speed clock counting pulse, performing logic AND operation on the low-order counting enable and the high-speed clock to obtain a high-speed clock counting pulse, and performing logic AND operation on two extra-order counting enables to obtain an extra-order counting pulse;
s4, counting down the high-speed clock counting pulse by adopting a high-order counter, and transmitting the counting value to a data processor; counting down the counting pulse of the low-speed clock by adopting a low-order counter, and transmitting a counting value to the data processor; counting down the extra bit counting pulse by adopting an extra bit counter, and transmitting a counting value to a data processor;
s5, the data processor calculates the quantized value of the pixel signal voltage according to the formula 2 x (a + Nb) + c; wherein a is a count value output by the high-order counter, b is a count value output by the low-order counter, c is a count value output by the extra-order counter, and N is a ratio of the frequency of the high-speed clock to the frequency of the low-speed clock.
8. The dual-ramp dual-edge down-count analog-to-digital conversion method of claim 7, wherein the first ramp signal gradually rises and the second ramp signal gradually falls; or the first ramp signal gradually falls and the second ramp signal gradually rises.
9. The dual slope dual edge count down analog to digital conversion method of claim 8, wherein said comparator comprises a first current source, a second current source, a first voltage source, a second voltage source, a first switch, a second switch, and a capacitor; one end of the first current source is connected to a power supply, the other end of the first current source is coupled to one end of the second current source, the other end of the second current source is grounded, one end of the first voltage source is grounded, the other end of the first voltage source is coupled to one end of the first switch, the other end of the first switch is coupled between the first current source and the second current source, one end of the second voltage source is grounded, the other end of the second voltage source is coupled to one end of the second switch, the other end of the second switch is coupled between the first switch and the second current source, the capacitor is coupled between the first switch and the second switch, and the other end of the capacitor is grounded;
at time t0, closing the second switch, resetting the voltage between the first current source and the second current source to the voltage of the second voltage source; at time t1, opening the second switch and the first current source while closing the second current source, the second current source discharging the capacitor, the voltage of the capacitor decreasing linearly with time, forming the first ramp signal;
at time t2, closing the first switch, resetting the voltage between the first current source and the second current source to the voltage of the first voltage source; at time t3, the first switch and the second current source are opened while the first current source is closed, the first current source charges the capacitor, and the voltage of the capacitor increases linearly with time to form the second ramp signal.
10. The dual slope dual edge count down analog to digital conversion method of claim 8, wherein said comparator comprises a first current source, a second current source, a first voltage source, a second voltage source, a first switch, a second switch, and a capacitor; one end of the first current source is connected to the power supply, the other end of the first current source is coupled to one end of the second current source, the other end of the second current source is grounded, one end of the first voltage source is grounded, the other end of the first voltage source is coupled to one end of the first switch, the other end of the first switch is coupled between the first current source and the second current source, one end of the second voltage source is grounded, the other end of the second voltage source is coupled to one end of the second switch, the other end of the second switch is coupled between the first switch and the second current source, the capacitor is coupled between the first switch and the second switch, and the other end of the capacitor is grounded;
at time t0, closing the first switch, resetting the voltage between the first current source and the second current source to the voltage of the first voltage source; at time t1, opening the first switch and the second current source while closing the first current source, the first current source charging a capacitor whose voltage increases linearly with time, forming the first ramp signal;
at time t2, closing the second switch, resetting the voltage between the first current source and the second current source to the voltage of the second voltage source; at time t3, the second switch and the first current source are opened while the second current source is closed, the second current source discharges the capacitor, and the voltage of the capacitor linearly decreases with time to form the second ramp signal.
11. The dual-slope dual-edge down-counting analog-to-digital conversion method of claim 8, wherein in step S2, the digital logic circuit respectively samples a time period between the start time of the first ramp signal and the second ramp signal to the flip time of the comparator with a falling edge of the low-speed clock to obtain a high count enable;
the digital logic circuit also respectively samples the time period from the starting time of the first ramp signal and the second ramp signal to the overturning time of the comparator by utilizing the rising edge of the high-speed clock to obtain low-order counting enable.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN115309222A (en) * | 2022-08-26 | 2022-11-08 | 中国计量大学 | Precise current source device based on digital regulation and control slope compensation |
| CN116744140A (en) * | 2023-08-14 | 2023-09-12 | 思特威(上海)电子科技股份有限公司 | Image sensor and readout circuit thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN115309222A (en) * | 2022-08-26 | 2022-11-08 | 中国计量大学 | Precise current source device based on digital regulation and control slope compensation |
| CN115309222B (en) * | 2022-08-26 | 2024-01-16 | 中国计量大学 | Precision current source device based on digital regulation and control slope compensation |
| CN116744140A (en) * | 2023-08-14 | 2023-09-12 | 思特威(上海)电子科技股份有限公司 | Image sensor and readout circuit thereof |
| CN116744140B (en) * | 2023-08-14 | 2023-12-22 | 思特威(上海)电子科技股份有限公司 | Image sensor and readout circuit thereof |
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