CN116915253A

CN116915253A - Analog-to-digital converter for partial discharge ultrasonic detection

Info

Publication number: CN116915253A
Application number: CN202310949163.3A
Authority: CN
Inventors: 孔令明; 王勇; 吉旺威; 杨柳; 朱璐
Original assignee: Guangzhou Power Supply Bureau of Guangdong Power Grid Co Ltd
Current assignee: Guangzhou Power Supply Bureau of Guangdong Power Grid Co Ltd
Priority date: 2023-07-31
Filing date: 2023-07-31
Publication date: 2023-10-20

Abstract

The invention discloses an analog-to-digital converter for partial discharge ultrasonic detection, which comprises a bootstrap switch, a sampling capacitor array, a comparator and an algorithm logic controller, wherein the bootstrap switch is connected with the sampling capacitor array; the bootstrap switch is connected to the input end of the comparator and used for conducting bootstrap according to the received sampling clock signal, receiving the input signal and buffering the input signal to the sampling capacitor array; the sampling capacitor array is connected to the input end of the comparator and used for buffering input signals; the output end of the comparator is connected with the algorithm logic controller and is used for comparing the input signal with the reference signal bit by bit to generate a unit digital signal and transmitting the unit digital signal to the algorithm logic controller; and the algorithm logic controller is used for responding to the unit digital signals, triggering the associated registers bit by bit, generating target digital signals and outputting the target digital signals. Therefore, the power consumption in the partial discharge signal detection process of the power equipment is reduced, and the use cost is effectively reduced.

Description

Analog-to-digital converter for partial discharge ultrasonic detection

Technical Field

The invention relates to the technical field of analog-to-digital conversion, in particular to an analog-to-digital converter for partial discharge ultrasonic detection.

Background

The normal production and life of people cannot be separated from the stable and healthy operation of the power grid system. However, the power grid system and its complexity and bulkiness, the devices of the power grid are also of a large variety, and the power grid devices cannot be operated intact all the time. Aging problems caused by long-term operation of power grid equipment or extreme weather, various emergency situations and the like can cause power grid faults, and normal production and life of people are affected.

Partial discharge may occur when the insulation of the substation electrical equipment is deteriorated. Monitoring and positioning of partial discharge are important means for equipment insulation fault early warning. The partial discharge signal is an analog signal, which cannot be directly processed by a computer or other electronic devices, and the partial discharge signal needs to be converted into a digital signal, and then the computer or other electronic devices perform signal processing and feature extraction to determine whether the power device has a fault, and an analog-to-digital converter is needed to convert the analog signal into the digital signal.

Conventional analog-to-digital converters can be classified by architecture into flash type ADC (flash ADC), pipelined ADC (pipelin ADC), sigma-delta ADC (sigma-delta ADC) and successive approximation ADC (SAR ADC). The analog-digital converters have large differences in the working principle and the working performance, so that the analog-digital converters can be applied to different occasions according to the respective characteristics. However, the conventional ADC has larger power consumption and higher use cost in the process of detecting the partial discharge signal of the power device.

Disclosure of Invention

The invention provides a low-power-consumption analog-to-digital converter for partial discharge detection, which solves the technical problems of larger power consumption and higher use cost in the process of partial discharge signal detection of power equipment by using a traditional ADC.

The invention provides an analog-to-digital converter for partial discharge ultrasonic detection, which comprises a bootstrap switch, a sampling capacitor array, a comparator and an algorithm logic controller, wherein the bootstrap switch is connected with the sampling capacitor array;

the bootstrap switch is connected to the input end of the comparator and is used for conducting bootstrap according to the received sampling clock signal, receiving the input signal and buffering the input signal to the sampling capacitor array;

the sampling capacitor array is connected to the input end of the comparator and used for buffering the input signal;

the output end of the comparator is connected with the algorithm logic controller and is used for comparing the input signal with the reference signal bit by bit to generate a unit digital signal and transmitting the unit digital signal to the algorithm logic controller;

the arithmetic logic controller is used for responding to the unit digital signals, triggering the associated registers bit by bit, generating target digital signals and outputting the target digital signals.

Optionally, the bootstrap switch includes a third MOS transistor, a fourth MOS transistor, a fifth MOS transistor, a sixth MOS transistor, a seventh MOS transistor, an eighth MOS transistor, a ninth MOS transistor, a tenth MOS transistor, and a digital power supply;

the bootstrap switch is specifically configured to turn on the third MOS transistor and the eighth MOS transistor when the received sampling clock signal is at a low level;

the gates of the fourth MOS tube, the sixth MOS tube, the ninth MOS tube and the tenth MOS tube are grounded through the seventh MOS tube and the eighth MOS tube respectively, so that the fourth MOS tube is conducted, the sixth MOS tube, the ninth MOS tube and the tenth MOS tube are disconnected, and the digital power supply is precharged;

when the received sampling clock signal is at a high level, the fourth MOS tube and the third MOS tube are disconnected, and the fifth MOS tube is conducted, so that the bootstrap switch is conducted, and an input signal is received and buffered to the sampling capacitor array.

Optionally, the comparator is a two-tail current type dynamic latching comparator.

Optionally, the comparator is specifically configured to:

comparing the input signal and a reference signal bit by bit;

if the input signal is smaller than the reference signal, generating a unit digital signal with a value of zero and transmitting the unit digital signal to the algorithm logic controller;

and if the input signal is greater than or equal to the reference signal, generating a unit digital signal with a value of one and transmitting the unit digital signal to the algorithm logic controller.

Optionally, the algorithm logic controller is a successive approximation algorithm logic controller, and is configured to implement a successive approximation algorithm.

Optionally, the successive approximation algorithm logic controller includes a logic controller and a timing generator.

Optionally, the algorithm logic controller is specifically configured to:

triggering the associated register in a single clock cycle in response to the unit digital signal and the external clock signal to generate a trigger output;

triggering the trigger adjacent to the register in the clock period through the trigger output to generate a new trigger output;

and when all the triggers are triggered, generating a target digital signal by adopting all the trigger outputs and outputting the target digital signal.

Optionally, the arithmetic logic controller supports synchronous logic or asynchronous logic.

Optionally, the comparator is a one-bit analog-to-digital converter.

Optionally, the capacitor array includes a plurality of sets of parallel capacitor structures and a single intermediate capacitor electrically connected;

the parallel capacitor structure comprises a single buffer capacitor and a two-way switch which are connected in series;

the intermediate capacitors are connected in series between the plurality of groups of parallel capacitor structures, and the number of adjacent parallel capacitor structures is equal.

From the above technical scheme, the invention has the following advantages:

the invention provides an analog-to-digital converter for partial discharge ultrasonic detection, which comprises a bootstrap switch, a sampling capacitor array, a comparator and an algorithm logic controller, wherein the bootstrap switch is connected with the sampling capacitor array; the bootstrap switch is connected to the input end of the comparator and used for conducting bootstrap according to the received sampling clock signal, receiving the input signal and buffering the input signal to the sampling capacitor array; the sampling capacitor array is connected to the input end of the comparator and used for buffering input signals; the output end of the comparator is connected with the algorithm logic controller and is used for comparing the input signal with the reference signal bit by bit to generate a unit digital signal and transmitting the unit digital signal to the algorithm logic controller; and the algorithm logic controller is used for responding to the unit digital signals, triggering the associated registers bit by bit, generating target digital signals and outputting the target digital signals. Therefore, the power consumption in the partial discharge signal detection process of the power equipment is reduced, and the use cost is effectively reduced.

Drawings

In order to more clearly illustrate the embodiments of the invention or the technical solutions of the prior art, the drawings which are used in the description of the embodiments or the prior art will be briefly described, it being obvious that the drawings in the description below are only some embodiments of the invention, and that other drawings can be obtained from these drawings without inventive faculty for a person skilled in the art.

Fig. 1 is a schematic structural diagram of an analog-to-digital converter for partial discharge ultrasonic detection according to an embodiment of the present invention;

fig. 2 is a circuit diagram of a bootstrap switch according to an embodiment of the present invention;

FIG. 3 is a schematic diagram of a dual tail current type dynamic latch comparator according to an embodiment of the present invention;

FIG. 4 is a schematic circuit diagram of a timing generator according to an embodiment of the present invention;

FIG. 5 is a schematic diagram of an output waveform of a timing generator according to an embodiment of the present invention;

fig. 6 is a schematic diagram of a logic structure of a successive approximation algorithm logic controller according to an embodiment of the present invention;

fig. 7 is a schematic circuit diagram of a capacitor array according to an embodiment of the present invention.

Detailed Description

The embodiment of the invention provides a low-power-consumption analog-to-digital converter for partial discharge detection, which is used for solving the technical problems of larger power consumption and higher use cost in the process of partial discharge signal detection of power equipment by using a traditional ADC.

In order to make the objects, features and advantages of the present invention more comprehensible, the technical solutions in the embodiments of the present invention are described in detail below with reference to the accompanying drawings, and it is apparent that the embodiments described below are only some embodiments of the present invention, but not all embodiments of the present invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

Referring to fig. 1, fig. 1 is a schematic structural diagram of an analog-to-digital converter for detecting partial discharge ultrasonic waves according to an embodiment of the present invention.

In the embodiment of the invention, the partial discharge input signal is amplified by the front-end amplifying circuit to a power voltage not exceeding SARADC, and differential signals generated after the partial discharge input signal is amplified by the front-end amplifying circuit are VIP and VIN and are connected to VIP and VIN ports in FIG. 1. The input VIP and VIN are sampled at a high level of the clock and quantized at a low level of the clock. The quantization process is as follows: firstly, 13 comparison pulses are generated by a time sequence generator in the SARLOGIC, the logic controllers are controlled by the 13 clocks, and each clock logic controller adjusts the input of the feedback capacitor array according to the output of the comparator so as to achieve the effect of successive approximation. After one clock cycle, the resulting digital signals DN <11> to DN <0> can be used to quantify the size of the input signal. The set of digital signals may be processed by a computer or other digital signal processing device.

In the embodiment of the present invention, the bootstrap switch is located in the broken line box of the ADC architecture in fig. 1, and a circuit diagram of the bootstrap switch provided in this embodiment is shown in fig. 2, where SAMPLE is a sampling clock signal, and SAMPLE is an inverting signal of the sampling clock.

The working principle comprises two processes: precharge and bootstrap conduction.

When the sampling clock signal SAMPLE is at a low level, the bootstrap switch is in a precharge process, at this time, M3 and M8 are turned on, the gates of M4, M6, M9 and M10 are grounded through M7 and M8, M4 is turned on, and M6, M9 and M10 are turned off, so that the voltage difference between the upper and lower plates of the capacitor Cp is precharged to VDD and kept constant.

When the sampling clock signal SAMPLE is at a high level, the bootstrap switch is in a bootstrap conduction process, at this time, M3 and M4 are disconnected, and M5 is turned on, at this time, the upper and lower plates of the capacitor Cp are respectively connected to two ends of the gate source of M10, so as to ensure that the on-resistance of M10 will not change along with the change of the input signal VIN.

It should be noted that, since the upper plate voltage of the capacitor Cp may be higher than VDD, the source terminal connected to M5 may be likely to be forward biased, and in order to avoid this, the source and the substrate need to be connected together.

Optionally, the comparator is a one-bit analog-to-digital converter.

Further, the comparator is specifically configured to:

comparing the input signal and a reference signal bit by bit;

In an embodiment of the invention, the comparator is one of the basic blocks of the analog-to-digital converter. The comparator outputs a binary digital signal by comparing the magnitudes of an analog signal and a reference signal.

It is worth mentioning that one comparator is a one-bit analog-to-digital converter. Comparators can be divided into two categories in embodiments of the invention: open loop comparators and dynamic latching comparators. The dynamic latching comparator has the characteristics of low power consumption, high speed and the like, and is widely applied to the low-power consumption analog-to-digital converter.

In this embodiment, a dual tail current type dynamic latching comparator is used, which includes two parts, an input gain stage and an output latch, as shown in fig. 3.

The dynamic latch comparator in this embodiment works as follows: in the reset phase CLK is low, the first stage outputs d+ and D-are precharged to VDD through M4 and M5, the second stage output nodes VOUTP and VOUTN are pulled to ground, at which time both tail current tubes M1 and M6 of the two stages are turned off. When CLK is high, the tail current tube of the input stage is conducted, the output nodes D+ and D-start discharging, and the discharging speed is different due to the difference of the voltages of the differential inputs VIP and VIN. Therefore, the voltage difference of nodes D+ and D-is transferred to VOUTN and VOUTP through M11 and M12. Once the common mode voltage of nodes D + and D-drops low enough until nodes VOUTP and VOUTN cannot be clamped to ground, the latch enters a regeneration phase, one end rapidly rises to VDD and the other end is pulled down to ground under the action of positive feedback, completing the comparison.

Further, the successive approximation algorithm logic controller comprises a logic controller and a timing generator.

Optionally, the algorithm logic controller is specifically configured to:

In one example of the invention, the arithmetic logic controller supports synchronous logic or asynchronous logic.

The successive approximation algorithm logic controller is used for realizing the successive approximation algorithm and is a core module in the analog-to-digital converter. This controller can be divided into synchronous logic and asynchronous logic depending on the implementation.

The synchronization logic operates the circuit through an externally accessed clock, and the circuit operates once in each cycle of the clock. For a 12-bit successive approximation type analog-to-digital converter, at least 12 clock cycles are required to quantize the input signal, and at least one clock cycle is required to sample, so that it can be seen that the analog-to-digital converter requires at least 13 clock cycles to complete a digital output of one point. The advantage of synchronous logic is that the logic is relatively intuitive, each action of the circuit is controlled by an external clock, but thus the dependence on the clock is also relatively high, for higher sampling rate analog to digital converters a clock of at least 13 times the frequency of the input signal is required, which is not easy to implement, and thus the synchronous logic is limited to the sampling frequency of the analog to digital converter.

Asynchronous logic is less dependent on the clock than synchronous logic, and the clock that controls the operation of the circuit is generated internally by the logic circuit. In asynchronous logic, a clock pulse is externally given, and a logic circuit generates a corresponding internal clock according to the clock pulse, so that the circuit performs N times of operations (N-bit ADC) to complete one-point quantization.

The successive approximation algorithm logic controller comprises two parts: logic controller and timing generator. As shown in fig. 4, the timing generator CLKS is a sampling clock pulse, Q12 is the last clock output of the logic controller, CLKC is the clock input of the comparator, QP is the positive output of the comparator, and QN is the negative output. The comparator starts to compare at the rising edge of the CLKC, the VALID becomes high level after the comparison is finished, the VALID signal rises to enable the CLKC to fall, the fall of the CLKC leads to the fall of the VALID, the fall of the VALID again leads to the rise of the CLKC, the next comparison period is entered, the comparison is performed in a reciprocating way, a closed loop is generated, the time sequence generator outputs waveforms as shown in fig. 5, and the VALID signal is used for triggering the internal clocks Q1-Q12.

The logic structure of the successive approximation algorithm logic controller in this embodiment is shown in fig. 6. The RESET signal sets the output of each flip-flop of the shift register to 0 prior to the sampling phase. During sampling, the VALID signal shifts high 1 to the output of the first flip-flop of the shift register, and the outputs of the remaining flip-flops remain low 0. At this time, the control signal DN <11> is high level 1, and the rest of the control signals DN <0> to QN <10> are low level 0. When the transition period occurs, the output of the first row of flip-flops sequentially goes high 1 under control of the VALID signal, which also causes the output of the second row of flip-flops to go high 1. At the same time, their respective output results are used as the clock signal of the flip-flop of the previous stage. Thus, DN <11> to DN <0> are each set and then trigger again to obtain a successive approximation logic control signal when the next clock rising edge arrives according to the output of the comparator.

Referring to fig. 7, the capacitor array includes a plurality of groups of parallel capacitor structures and a single intermediate capacitor electrically connected;

In the embodiment of the invention, the received input signals are buffered through the capacitor array, and meanwhile, the power consumption and the area are optimized.

The embodiment of the invention provides an analog-to-digital converter for partial discharge ultrasonic detection, which comprises a bootstrap switch, a sampling capacitor array, a comparator and an algorithm logic controller, wherein the bootstrap switch is connected with the sampling capacitor array; the bootstrap switch is connected to the input end of the comparator and used for conducting bootstrap according to the received sampling clock signal, receiving the input signal and buffering the input signal to the sampling capacitor array; the sampling capacitor array is connected to the input end of the comparator and used for buffering input signals; the output end of the comparator is connected with the algorithm logic controller and is used for comparing the input signal with the reference signal bit by bit to generate a unit digital signal and transmitting the unit digital signal to the algorithm logic controller; and the algorithm logic controller is used for responding to the unit digital signals, triggering the associated registers bit by bit, generating target digital signals and outputting the target digital signals. Therefore, the power consumption in the partial discharge signal detection process of the power equipment is reduced, and the use cost is effectively reduced.

What is not described in detail in the present specification is a known technology to those skilled in the art.

In several embodiments provided by the present invention, it should be understood that the disclosed analog-to-digital converter may be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative, e.g., the division of the units is merely a logical function division, and there may be additional divisions when actually implemented, e.g., multiple units or components may be combined or integrated into another system, or some features may be omitted or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be an indirect coupling or communication connection via some interfaces, devices or units, which may be in electrical, mechanical or other form.

The above embodiments are only for illustrating the technical solution of the present invention, and not for limiting the same; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. An analog-to-digital converter for partial discharge ultrasonic detection is characterized by comprising a bootstrap switch, a sampling capacitor array, a comparator and an algorithm logic controller;

2. The analog-to-digital converter for partial discharge ultrasonic detection according to claim 1, wherein the bootstrap switch comprises a third MOS transistor, a fourth MOS transistor, a fifth MOS transistor, a sixth MOS transistor, a seventh MOS transistor, an eighth MOS transistor, a ninth MOS transistor, a tenth MOS transistor, and a digital power supply;

3. The analog-to-digital converter for partial discharge ultrasonic detection of claim 1, wherein the comparator is a two-tail current type dynamic latching comparator.

4. Analog-to-digital converter for partial discharge ultrasonic detection according to claim 1, characterized in that the comparator is in particular adapted to:

comparing the input signal and a reference signal bit by bit;

5. The analog-to-digital converter for partial discharge ultrasonic detection according to claim 1, wherein the algorithm logic controller is a successive approximation algorithm logic controller for implementing a successive approximation algorithm.

6. The analog-to-digital converter for partial discharge ultrasonic detection according to claim 5, wherein said successive approximation algorithm logic controller comprises a logic controller and a timing generator.

7. Analog-to-digital converter for partial discharge ultrasonic detection according to claim 1, characterized in that said arithmetic logic controller is specifically configured to:

8. The analog-to-digital converter for partial discharge ultrasonic detection according to claim 1, wherein said arithmetic logic controller supports synchronous logic or asynchronous logic.

9. The analog-to-digital converter for partial discharge ultrasonic detection according to claim 1, wherein the comparator is a one-bit analog-to-digital converter.

10. The analog-to-digital converter for partial discharge ultrasonic detection of claim 1, wherein the capacitive array comprises a plurality of sets of parallel capacitive structures and a single intermediate capacitance electrically connected;