CN116846391A - Low-offset low-power consumption dynamic comparator based on double calibration - Google Patents
Low-offset low-power consumption dynamic comparator based on double calibration Download PDFInfo
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/10—Calibration or testing
- H03M1/1009—Calibration
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/45—Differential amplifiers
- H03F3/45071—Differential amplifiers with semiconductor devices only
- H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
- H03F3/45179—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using MOSFET transistors as the active amplifying circuit
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/22—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
- H03K5/24—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/002—Provisions or arrangements for saving power, e.g. by allowing a sleep mode, using lower supply voltage for downstream stages, using multiple clock domains or by selectively turning on stages when needed
Abstract
The invention relates to a low-offset low-power consumption dynamic comparator based on double calibration. The clock generation circuit generates a first-stage calibration clock CLK1, a second-stage calibration clock CLK2 and a counter RESET signal RESET according to a comparator clock CLKC and a control signal CA, and the comparator successively completes twice calibration according to the change of the three signals and then enters a comparison state. The built-in comparator is composed of the dynamic pre-amplifier and the dynamic latch, static power consumption is not needed to be considered, and the scheme of changing the substrate potential twice by the 5bit DAC calibration unit finally enables the invention to achieve the effects of low offset and low power consumption.
Description
Technical Field
The invention relates to a low-offset low-power consumption dynamic comparator based on double calibration.
Background
With the rapid development of information and communication technologies, digital signal processing technologies are widely used in various fields. Various advanced adaptive algorithms all need to convert signals into digital forms for processing, and replace the traditional analog circuits to complete corresponding functions. However, most signals in nature are analog signals, so an analog-to-digital converter (ADC) is required to convert the analog signals to digital signals. The current analog-to-digital converter is widely applied to the fields of broadband communication, medical monitoring, audio processing and the like, and is an essential key circuit module in modern electronic equipment.
There are three classical nyquist ADCs: flashADC, pipelineADC and SARADC, while sigma-delta ADCs are over-sampled ADCs, different ADCs have different characteristics and uses. The sigma-delta ADC can reach the resolution of 24bit or higher precision by an oversampling technology and a noise shaping technology, but has slower speed, and is mainly applied to the audio frequency field. The FlashADC structure is simple and fast, but the number of internal devices increases exponentially with the resolution, and the FlashADC structure is mainly applied to the fields of high speed and low precision. The pipeline ADC is formed by cascading a plurality of ADC pipeline stages with the same working flow, each stage works alternately in a pipeline mode, high conversion rate can be realized, but the power consumption is larger, and the pipeline ADC is mainly used in the video field. The SARADC structure is relatively simple, the digitizing degree is high, the process compatibility is good, the sampling rate is medium and low, the resolution is about 12 bits on average, the energy efficiency is good, and the SARADC structure becomes an ADC structure commonly used in the wearable intelligent equipment and medical field.
In order to meet the market demand of products, SARADC is currently tending to have low power consumption and high precision. In high-precision SARADC, the precision is limited by the offset of the comparator, and the offset of the comparator mainly comes from the offset of the production process, the offset caused by the environmental change and the offset caused by the structure and the working point setting of the comparator, so the design of the low-offset comparator is important. Currently, the on-chip calibration circuits of the comparator mainly include Input Offset Storage (IOS), output Offset Storage (OOS), charge pump calibration, DAC calibration, and the like. The pre-amplifier of IOS technology and OOS technology is a static structure, and introduces a static current, resulting in a larger power consumption and a longer response time. Charge pump calibration is difficult to control the calibration accuracy. DAC calibration can generate area waste if the number of bits is too large, and can also introduce large power consumption.
Disclosure of Invention
The invention aims to reduce the offset voltage of a high-precision SARADC comparator and ensure that a system has lower power consumption, so that the low-offset low-power consumption dynamic comparator based on double calibration is provided, two 5-bit DACs are multiplexed in sequence to change the substrate potential to finish twice calibration, lower power consumption and smaller area can be realized, and higher calibration precision is achieved.
In order to achieve the above purpose, the technical scheme of the invention is as follows: a low-offset low-power consumption dynamic comparator based on double calibration comprises a comparator input unit, a clock generation circuit, a dynamic pre-amplifier, a dynamic latch and a DAC calibration unit; the input end of the comparator input unit is used as the input end voltage signal and the input of the input common-mode voltage signal, the output end of the comparator input unit is connected with the input end of the dynamic pre-amplifier, the input end of the clock generating circuit is used as the control signal and the input of the comparator clock signal so as to generate a first calibration clock, a second calibration clock and a counter reset signal as the control signals of the DAC calibration unit; the comparator clock signal is also used as a control signal of the dynamic pre-amplifier and the DAC calibration unit, the output end of the dynamic pre-amplifier is connected with the input end of the dynamic latch, the output signal of the output end of the dynamic latch is used as the input signal of the input end of the DAC calibration unit, and the output signal of the output end of the DAC calibration unit is used as the substrate calibration voltage of the first stage and the substrate calibration voltage of the second stage respectively.
In one embodiment of the present invention, the comparator input unit is composed of two selectors, wherein the input of one selector is the first input terminal voltage signal V ip And input common mode voltage signal V cm1 The input of the other selector is the second input terminal voltage signal V in And input common mode voltage signal V cm1 The output terminals of the two selectors serve as the output terminals of the comparator input unit, and output an output signal (V + ，V - )。
In one embodiment of the present invention, the dynamic pre-amplifier is composed of transistors M1, M2, M3, M4 and M5; the output of the comparator input unit outputs a signal (V + ，V - ) The input of the dynamic pre-amplifier is connected with the grid electrodes of the differential input pair transistors M2 and M3; the drains of M2 and M4 are connected, the drains of M3 and M5 are connected, and the drains are used as output ends of the dynamic pre-amplifier to output signals (on 1, op 1); m4 and M5 sources are connected to ground potential; the sources of the differential input pair transistors M2 and M3 are connected with the drain of M1, the source of M1 is connected with a power supply, M4 and M5 are used as switching tubes for controlling the working states of the dynamic pre-amplifier, and the clock signal CLKC of the comparator acts on the gates of M1, M4 and M5.
In one embodiment of the present invention, the dynamic latch is composed of transistors M6, M7, M8, M9, M10, M11, M12 and M13; the output end of the dynamic pre-amplifier outputs signals (on 1, op 1) as input signals, which are respectively connected with the grids of M8, M10, M9 and M11, the drains of M8 and M9 are respectively connected with the drains of M10, M12, M11 and M13, the sources of M8 and M9 are respectively connected with the drains of M6 and M7, and the grids of M6 and M7 are respectively connected with the grids of M12 and M13; sources of M6, M7 are connected to ground potential, sources of M10, M11, M12 and M13 are connected to supply voltage; the grid electrodes of M6 and M12 are connected with the drain electrodes of M9, M11 and M13, the grid electrodes of M7 and M13 are connected with the drain electrodes of M8, M10 and M12, and are respectively used as output signals (VOUTP, VOUTN) of the output ends of the dynamic latches; the output signals (on 1, op 1) of the output ends of the dynamic pre-amplifier control the grid electrodes of M8, M9, M10 and M11, and control the on and off of the grid electrodes.
In one embodiment of the invention, DAC calibrationThe unit consists of a counter, an R-2RDAC array and a switched capacitor network; the clock signal CLKC of the comparator, the output signal VOUTP of the output end of the dynamic latch and the counter RESET signal RESET are used as the input signals of the counter, the binary code output by the counter and the reference voltage V ref Common mode voltage V cm2 And the first calibration clock CLK1 is used as an input signal of the R-2RDAC array, the output end of the R-2RDAC array is connected with a switched capacitor network, and the switched capacitor network comprises four transistors and four capacitors C BP0 、C BN0 、C BP1 、C BN1 The drain electrode of each transistor is respectively connected with the output end of the R-2RDAC array, the source electrode of each transistor is respectively used as four substrate voltage output ends of the DAC calibration unit, and the source electrode of each transistor is respectively connected with the output end of the R-2RDAC array through four capacitors C BP0 、C BN0 、C BP1 、C BN1 Each transistor is connected to the ground potential, and is controlled to be turned on and off by a first calibration clock CLK1, a second calibration clock CLK2, the first calibration clock CLK1 and the second calibration clock CLK2 in sequence, and under the control of the first calibration clock CLK1 and the second calibration clock CLK2, the two calibration is completed successively, and finally four substrate voltages V are generated BP0 、V BN0 、V BP1 And V BN1 。
In an embodiment of the present invention, the specific working principle of the dynamic comparator composed of the dynamic pre-amplifier and the dynamic latch is as follows: when the clock signal CLKC of the comparator is at a high level, the dynamic comparator works in a reset state, M4 and M5 in the dynamic pre-amplifier are conducted, drain voltages of M4 and M5 are directly pulled to the ground, and output signals (on 1 and op 1) of the output end of the dynamic pre-amplifier are at zero potential; in the dynamic latch, M10 and M11 are conducted, M8 and M9 are cut off, and output signals (VOUTP, VOUTN) at the output end of the dynamic latch are pulled to a power supply potential; when the clock signal CLKC of the comparator is in a low level, the dynamic comparator works in a comparison state, M1 in the dynamic pre-amplifier is conducted, and the charging speeds to the on1 and on2 nodes are different according to the different input signals; m10 and M11 in the dynamic latch are cut off, M8 and M9 are conducted, and V is assumed + >V - Thus on1<op1, final VOUTP is highLevel, VOUTN is low.
In an embodiment of the present invention, the twice calibration method specifically includes: the clock generation circuit generates a first calibration clock CLK1, a second calibration clock CLK2 and a counter RESET signal RESET according to the input control signal CA and the comparison clock signal CLKC; in the comparator calibration phase, the two analog input signals of the comparator are set to the input common mode voltage signal V by the input selector under the comparison clock signal CLKC of a given frequency cm1 Assuming that the comparator itself is out of order, the output will be at high and low levels; the positive end output of the comparator is used as the counting trigger level of a counter in the DAC calibration unit, and the output binary code is given to the R-2R DAC array and converted into corresponding analog voltage; first, when the control signal CA is low, the clock generation circuit will set the first calibration clock CLK1 and the second calibration clock CLK2 to low, the counter RESET signal RESET to high, and C in the switched capacitor network BP0 、C BN0 、C BP1 And C BN1 Will be fixed at a voltage based on the initial output signal of the R-2R DAC array; when the first calibration is started, the first calibration clock CLK1 and the counter RESET signal RESET are low, the second calibration clock CLK2 and the control signal CA are high, and the counter counts correspondingly according to the output result of the comparator, at this time C BP0 And C BN0 The voltage drop across it will follow the output voltage variation of the R-2RDAC array; the substrate voltages of M2 and M3 are changed, which is equivalent to changing the threshold voltage V of the transistor TH The charging speed of the nodes at two sides is changed, so that offset voltage correction is completed; before the first calibration is finished and the second calibration is started, the counter RESET signal RESET is changed to a high level again, and the counter is RESET; at the beginning of the second calibration, the first calibration clock CLK1 is high and the second calibration clock CLK2 and counter RESET signal RESET are low, at which time C BP1 And C BN1 The voltage drop across the array varies according to the variation of the output voltage of the R-2R DAC array, and C BP0 And C BN0 Will not change any more; when the second calibration is finished, C BP1 And C BN1 The pressure drop across will also be maintainedIs unchanged; thereafter, the first calibration clock CLK1 and the second calibration clock CLK2 will both remain high, C BP0 、C BN0 、C BP1 And C BN1 The voltage on the voltage source is fixed, and the calibration is completed;
during the normal operation phase of the comparator, the selector sets the input voltage to V ip And V in At this time, the offset voltage of the comparator is approximately zero, if V ip >V in Output result VOUTP is high level, VOUTN is low level, otherwise output VOUTP is low level, VOUTN is high level.
In one embodiment of the present invention, the minimum accuracy of the first calibration is greater than the minimum accuracy of the second calibration, and the minimum calibration step size of the first calibration is smaller than the minimum calibration step size of the second calibration, and the gate switch is controlled by the first calibration clock CLK1 under the condition that the minimum step size of the two calibrations is changed by setting the gate switch in the R-2RDAC array.
Under the control of the calibration clock, the invention firstly carries out twice calibration on the comparator, and after the calibration is completed, the offset existing in the comparator is greatly reduced. In order to achieve the calibration effect of the invention, the traditional single-stage calibration scheme for changing the substrate potential through the DAC needs to use more than 8bit DAC, but the invention can be completed by only using 5bit DAC, thereby saving the area and the power consumption of the circuit and simultaneously providing higher calibration precision.
Compared with the prior art, the invention has the following beneficial effects: the invention discloses a low-offset low-power consumption dynamic comparator based on double calibration, which comprises five modules, namely a comparator input unit, a dynamic pre-amplifier, a dynamic latch, a DAC calibration unit and a clock generation circuit. The dynamic comparator adopts the 5-bit DAC to change the substrate potential to calibrate the dynamic pre-amplifier and the dynamic latch twice, so that the energy consumption and the area of the DAC are greatly reduced, higher calibration precision can be provided, and the low-offset low-power-consumption two-stage dynamic comparator suitable for high-precision SARADC is realized. The invention has great application prospect in high-precision ADC, especially SARADC.
Drawings
Fig. 1 is an overall block diagram of a dynamic comparator.
Fig. 2 is a block diagram of a dynamic comparator system.
Fig. 3 is a circuit diagram of a comparator input unit.
Fig. 4 is a circuit diagram of a dynamic pre-amplifier.
Fig. 5 is a circuit diagram of a dynamic latch.
Fig. 6 is a system block diagram of a DAC calibration unit.
Detailed Description
The technical scheme of the invention is specifically described below with reference to the accompanying drawings.
The invention relates to a low-offset low-power consumption dynamic comparator based on double calibration, which comprises a comparator input unit, a clock generation circuit, a dynamic pre-amplifier, a dynamic latch and a DAC calibration unit, wherein the clock generation circuit is used for generating a clock signal; the input end of the comparator input unit is used as the input end voltage signal and the input of the input common-mode voltage signal, the output end of the comparator input unit is connected with the input end of the dynamic pre-amplifier, the input end of the clock generating circuit is used as the control signal and the input of the comparator clock signal so as to generate a first calibration clock, a second calibration clock and a counter reset signal as the control signals of the DAC calibration unit; the comparator clock signal is also used as a control signal of the dynamic pre-amplifier and the DAC calibration unit, the output end of the dynamic pre-amplifier is connected with the input end of the dynamic latch, the output signal of the output end of the dynamic latch, the reference voltage signal and the common-mode voltage signal are used as input signals of the input end of the DAC calibration unit, and the output signal of the output end of the DAC calibration unit is used as the substrate calibration voltage of the first stage and the substrate calibration voltage of the second stage respectively.
The following is a specific implementation procedure of the present invention.
The invention provides a double calibration scheme based on substrate potential programming, which sequentially multiplexes two 5bit DACs to change the substrate potential to finish twice calibration, can realize lower power consumption and smaller area, and has higher calibration precision.
In order to reduce offset voltage of high-precision SARADC comparator and simultaneously to reduce offset voltage of high-precision SARADC comparatorThe invention provides a low-offset low-power consumption dynamic comparator based on double calibration, which is shown in figure 1. The dynamic Comparator 0 (Comparator) comprises two input voltages 1 (V ip ,V in ) An input common mode voltage 2 (V cm1 ) A control signal 3 (CA), a comparison clock signal 4 (CLKC), a pair of output signals 5 (VOUTP, VOUTN), a calibration module reference voltage 6 (V ref ) And a calibration module common-mode input voltage 7 (V cm2 ). The system block diagram is shown in fig. 2, which includes five parts, a comparator Input unit 8 (Input), a clock generation circuit 9 (clk_generator), a dynamic Pre-amplifier 10 (Pre-amp), a dynamic Latch 11 (Latch), and a DAC calibration unit 12 (DAC calibration). The input signal 1 and the common mode voltage 2 are taken as input signals of the input unit 8, and the output signal 13 of the input unit 8 is taken as input signal of the preamplifier 10. The control signal 3 and the comparator clock 4 serve as the first calibration clock 15, the second calibration clock 16 and the counter reset signal 17 generated as input signals to the clock generation circuit 9 as control signals to the DAC calibration unit 12. The comparator clock 4 is used as a control signal for the pre-amplifier 10 and the DAC calibration unit 12, the output signal 14 of the pre-amplifier 10 is used as an input for the dynamic latch 11, the output signal VOUTP of the dynamic latch 11, the reference voltage 6 and the common mode voltage 7 are used as input signals for the DAC calibration unit 12, the output signals 18, 19 of the DAC calibration unit 12 are used as substrate calibration voltages for the first stage, and the 20, 21 are used as substrate calibration voltages for the second stage.
The specific structure of the input unit is shown in fig. 3, and mainly consists of two Selectors (MUXs). Wherein the input of one selector is V ip And V cm1 The input of the other selector being V in And V cm1 The outputs of the two selectors constitute 13 (V + ，V - )。
The dynamic pre-amplifier 10 has a specific structure shown in fig. 4, and is composed of transistors M1, M2, M3, M4 and M5. The output signal 13 (V of the comparator input unit + ，V - ) The input to the pre-amplifier is connected to the gates of the differential input pair transistors M2, M3. M2 and M4 drain electrodes are connected, and the same is true of M3 and M5, and the two are used as pre-preparationThe amplifier outputs a signal 14 (on 1, op 1). The sources of M4 and M5 are connected to ground potential. The source ends of the input pair transistors M2 and M3 are connected with the drain electrode of the M1, the source electrode of the M1 is connected with a power supply, and the M4 and M5 serve as switching tubes to control the working state of the circuit. The clock signal CLKC acts on the gates of M1, M4, M5.
The specific structure of the dynamic latch 11 is shown in fig. 5, and is composed of M6, M7, M8, M9, M10, M11, M12 and M13. The pre-amplifier output signals 14 (on 1, op 1) are respectively connected with the gates of M8, M10, M9 and M11 as input signals, the drains of M8 and M9 are respectively connected with the drains of M10, M12, M11 and M13, the sources of M8 and M9 are respectively connected with the drains of M6 and M7, and the gates of M6 and M7 are respectively connected with the gates of M12 and M13. The sources of M6, M7 are connected to ground potential, and the sources of M10, M11, M12 and M13 are connected to the supply voltage. In order to form a positive feedback latch, the gates of M6, M12 are connected to the drains of M9, M11 and M13, and, due to circuit symmetry, the gates of M7, M13 are also connected to the drains of M8, M10 and M12 and serve as output signals 5 (VOUTP, VOUTN), respectively. The pre-amplifier output signal 14 (on 1, op 1) controls the gates of M8, M9, M10 and M11, which are turned on and off.
The DAC calibration unit 12 is specifically configured as shown in FIG. 6, and is composed of a Counter, an R-2RDAC array, and a switched capacitor network. CLKC, VOUTP and RESET are used as input signals for the counter, the binary code output by the counter, reference voltage 6 (V ref ) Common mode voltage 7 (V cm2 ) And CLK1 is used as an input signal of R-2RDAC, and under the control of a clock, calibration is completed twice successively, and finally four substrate voltages V are generated BP0 、V BN0 、V BP1 And V BN1 。
The specific working principle of the dynamic comparator consisting of the dynamic pre-amplifier and the dynamic latch is as follows: when CLKC is high, the comparator is operated in a reset state, M4, M5 is turned on in the dynamic pre-amplifier 10, the drain voltages of M4, M5 are pulled directly to ground, and the pre-amplifier output signal 14 (on 1, op 1) is at zero potential. In the dynamic latch 7, M10 and M11 are turned on, M8 and M9 are turned off, and the latch output signal 5 (VOUTP, VOUTN) is pulled to the power supply potential. When CLKC is low, the comparator is operated in comparison state, pre-chargeIn the amplifier, M1 is conducted, and the charging speeds to the on1 and on2 nodes are different according to the input signals. M10 and M11 in the dynamic latch 7 are cut off, M8 and M9 are switched on, and V is assumed + >V - Thus on1<op1, final VOUTP is high level and VOUTN is low level.
The present invention has two calibrations in total, and the clock generation circuit 9 generates the first calibration clock CLK1 and the second calibration clock CLK2 and the counter RESET signal RESET from the inputted CA and CLKC signals. In the comparator calibration stage, two analog input signals of the comparator are set to V by an input selector under a clock signal with a given frequency cm1 It is assumed that the comparator itself is out of order, so that the output will appear high and low. And taking the positive end output of the comparator as the counting trigger level of a counter in the DAC calibration unit, and giving the output binary code to the R-2RDAC array and converting the binary code into corresponding analog voltage. First, when CA is low, the clock generation circuit will set CLK1 and CLK2 low and the RESET signal will be high, thus C BP0 、C BN0 、C BP1 And C BN1 Will be fixed at a voltage based on the initial output signal of the R-2R DAC array. When the first calibration starts, CLK1 and RESET are low, CLK2 and CA are high, and the counter counts accordingly according to the output of the comparator, C BP0 And C BN0 The voltage drop across it will follow the output voltage variation of the R-2 RDAC. The substrate voltages of M2 and M3 are changed, which is equivalent to changing the threshold voltage V of the transistor TH The charging speed of the nodes at two sides is changed, so that offset voltage correction is completed. The RESET signal goes high again before the first calibration ends and the second calibration begins, resetting the counter. At the beginning of the second calibration, CLK1 is high and CLK2 and RESET are low, at which time C BP1 And C BN1 The voltage drop across the R-2RDAC array will vary according to the variation of the output voltage of the R-2RDAC array, and C BP0 And C BN0 Will not change. When the second calibration is finished, C BP1 And C BN1 The pressure drop across will also remain unchanged. Thereafter, CLK1 and CLK2 will both remain high and the voltages on the four capacitors will be fixedAnd (5) quasi-completion. The full range of the first-stage calibration substrate voltage is required to be capable of calibrating offset voltage of the comparator, and the minimum precision of the first-stage calibration is larger than that of the second-stage calibration, so that the second-stage calibration can be guaranteed to further repair the residual quantity after the first-stage calibration is finished. The minimum calibration step size of the first stage is smaller than the minimum calibration step size of the second stage because of the presence of the first stage gain, the change in the substrate voltages of the first and second stages being equivalent to a different effect on the input. The minimum step size of the two calibrations is changed by setting the gating switch in the R-2RDAC array, which is controlled by CLK 1.
During the normal operation phase of the comparator, the selector sets the input voltage to V ip And V in At this time, the offset voltage of the comparator is approximately zero, if V ip >V in Output result VOUTP is high level, VOUTN is low level, otherwise output VOUTP is low level, VOUTN is high level.
Under the control of the calibration clock, the comparator is calibrated twice, and after the calibration is completed, the offset existing in the comparator is greatly reduced. In order to achieve the calibration effect of the invention, the traditional single-stage calibration scheme for changing the substrate potential through the DAC needs to use more than 8bit DAC, but the invention can be completed by only using 5bit DAC, thereby saving the area and the power consumption of the circuit and simultaneously providing higher calibration precision.
The above is a preferred embodiment of the present invention, and all changes made according to the technical solution of the present invention belong to the protection scope of the present invention when the generated functional effects do not exceed the scope of the technical solution of the present invention.
Claims (8)
1. The low-offset low-power consumption dynamic comparator based on double calibration is characterized by comprising a comparator input unit, a clock generation circuit, a dynamic pre-amplifier, a dynamic latch and a DAC calibration unit; the input end of the comparator input unit is used as the input end voltage signal and the input of the input common-mode voltage signal, the output end of the comparator input unit is connected with the input end of the dynamic pre-amplifier, the input end of the clock generating circuit is used as the control signal and the input of the comparator clock signal so as to generate a first calibration clock, a second calibration clock and a counter reset signal as the control signals of the DAC calibration unit; the comparator clock signal is also used as a control signal of the dynamic pre-amplifier and the DAC calibration unit, the output end of the dynamic pre-amplifier is connected with the input end of the dynamic latch, the output signal of the output end of the dynamic latch is used as the input signal of the input end of the DAC calibration unit, and the output signal of the output end of the DAC calibration unit is used as the substrate calibration voltage of the first stage and the substrate calibration voltage of the second stage respectively.
2. The low offset and low power consumption dynamic comparator according to claim 1, wherein the comparator input unit comprises two selectors, wherein the input of one selector is the first input terminal voltage signal V ip And input common mode voltage signal V cm1 The input of the other selector is the second input terminal voltage signal V in And input common mode voltage signal V cm1 The output terminals of the two selectors serve as the output terminals of the comparator input unit, and output an output signal (V + ，V - )。
3. The low offset and low power consumption dynamic comparator based on dual calibration of claim 2, wherein the dynamic pre-amplifier is comprised of transistors M1, M2, M3, M4 and M5; the output of the comparator input unit outputs a signal (V + ，V - ) The input of the dynamic pre-amplifier is connected with the grid electrodes of the differential input pair transistors M2 and M3; the drains of M2 and M4 are connected, the drains of M3 and M5 are connected, and the drains are used as output ends of the dynamic pre-amplifier to output signals (on 1, op 1); m4 and M5 sources are connected to ground potential; the sources of the differential input pair transistors M2 and M3 are connected with the drain of M1, the source of M1 is connected with a power supply, M4 and M5 are used as switching tubes for controlling the working states of the dynamic pre-amplifier, and the clock signal CLKC of the comparator acts on the gates of M1, M4 and M5.
4. A low offset low power dynamic comparator according to claim 3, wherein the dynamic latch is comprised of transistors M6, M7, M8, M9, M10, M11, M12 and M13; the output end of the dynamic pre-amplifier outputs signals (on 1, op 1) as input signals, which are respectively connected with the grids of M8, M10, M9 and M11, the drains of M8 and M9 are respectively connected with the drains of M10, M12, M11 and M13, the sources of M8 and M9 are respectively connected with the drains of M6 and M7, and the grids of M6 and M7 are respectively connected with the grids of M12 and M13; sources of M6, M7 are connected to ground potential, sources of M10, M11, M12 and M13 are connected to supply voltage; the grid electrodes of M6 and M12 are connected with the drain electrodes of M9, M11 and M13, the grid electrodes of M7 and M13 are connected with the drain electrodes of M8, M10 and M12, and are respectively used as output signals (VOUTP, VOUTN) of the output ends of the dynamic latches; the output signals (on 1, op 1) of the output ends of the dynamic pre-amplifier control the grid electrodes of M8, M9, M10 and M11, and control the on and off of the grid electrodes.
5. The low-offset low-power consumption dynamic comparator based on double calibration according to claim 4, wherein the DAC calibration unit consists of a counter, an R-2RDAC array and a switched capacitor network; the clock signal CLKC of the comparator, the output signal VOUTP of the output end of the dynamic latch and the counter RESET signal RESET are used as the input signals of the counter, the binary code output by the counter and the reference voltage V ref Common mode voltage V cm2 And the first calibration clock CLK1 is used as an input signal of the R-2RDAC array, the output end of the R-2RDAC array is connected with a switched capacitor network, and the switched capacitor network comprises four transistors and four capacitors C BP0 、C BN0 、C BP1 、C BN1 The drain electrode of each transistor is respectively connected with the output end of the R-2RDAC array, the source electrode of each transistor is respectively used as four substrate voltage output ends of the DAC calibration unit, and the source electrode of each transistor is respectively connected with the output end of the R-2RDAC array through four capacitors C BP0 、C BN0 、C BP1 、C BN1 Each transistor is connected to the ground potential and is controlled to be turned on and off by a first calibration clock CLK1, a second calibration clock CLK2, the first calibration clock CLK1 and the second calibration clock CLK2 in sequence, and the first calibration clockUnder the control of CLK1 and the second calibration clock CLK2, two calibrations are completed in sequence, and four substrate voltages V are finally generated BP0 、V BN0 、V BP1 And V BN1 。
6. The low-offset low-power consumption dynamic comparator based on double calibration according to claim 4, wherein the specific working principle of the dynamic comparator consisting of the dynamic pre-amplifier and the dynamic latch is as follows: when the clock signal CLKC of the comparator is at a high level, the dynamic comparator works in a reset state, M4 and M5 in the dynamic pre-amplifier are conducted, drain voltages of M4 and M5 are directly pulled to the ground, and output signals (on 1 and op 1) of the output end of the dynamic pre-amplifier are at zero potential; in the dynamic latch, M10 and M11 are conducted, M8 and M9 are cut off, and output signals (VOUTP, VOUTN) at the output end of the dynamic latch are pulled to a power supply potential; when the clock signal CLKC of the comparator is in a low level, the dynamic comparator works in a comparison state, M1 in the dynamic pre-amplifier is conducted, and the charging speeds to the on1 and on2 nodes are different according to the different input signals; m10 and M11 in the dynamic latch are cut off, M8 and M9 are conducted, and V is assumed + >V - Thus on1<op1, final VOUTP is high level and VOUTN is low level.
7. The low-offset low-power consumption dynamic comparator based on double calibration according to claim 5, wherein the twice calibration mode is specifically: the clock generation circuit generates a first calibration clock CLK1, a second calibration clock CLK2 and a counter RESET signal RESET according to the input control signal CA and the comparison clock signal CLKC; in the comparator calibration phase, the two analog input signals of the comparator are set to the input common mode voltage signal V by the input selector under the comparison clock signal CLKC of a given frequency cm1 Assuming that the comparator itself is out of order, the output will be at high and low levels; the positive end output of the comparator is used as the counting trigger level of a counter in the DAC calibration unit, and the output binary code is given to the R-2RDAC array and converted into corresponding analog voltage; first, when the control signal CA is low, the clock generating circuitThe first calibration clock CLK1 and the second calibration clock CLK2 are set low and the counter RESET signal RESET is set high, C in the switched capacitor network BP0 、C BN0 、C BP1 And C BN1 Will be fixed at a voltage based on the initial output signal of the R-2R DAC array; when the first calibration is started, the first calibration clock CLK1 and the counter RESET signal RESET are low, the second calibration clock CLK2 and the control signal CA are high, and the counter counts correspondingly according to the output result of the comparator, at this time C BP0 And C BN0 The voltage drop across it will follow the output voltage variation of the R-2RDAC array; the substrate voltages of M2 and M3 are changed, which is equivalent to changing the threshold voltage V of the transistor TH The charging speed of the nodes at two sides is changed, so that offset voltage correction is completed; before the first calibration is finished and the second calibration is started, the counter RESET signal RESET is changed to a high level again, and the counter is RESET; at the beginning of the second calibration, the first calibration clock CLK1 is high and the second calibration clock CLK2 and counter RESET signal RESET are low, at which time C BP1 And C BN1 The voltage drop across the array varies according to the variation of the output voltage of the R-2R DAC array, and C BP0 And C BN0 Will not change any more; when the second calibration is finished, C BP1 And C BN1 The pressure drop across will also remain unchanged; thereafter, the first calibration clock CLK1 and the second calibration clock CLK2 will both remain high, C BP0 、C BN0 、C BP1 And C BN1 The voltage on the voltage source is fixed, and the calibration is completed;
during the normal operation phase of the comparator, the selector sets the input voltage to V ip And V in At this time, the offset voltage of the comparator is approximately zero, if V ip >V in Output result VOUTP is high level, VOUTN is low level, otherwise output VOUTP is low level, VOUTN is high level.
8. The low offset low power dynamic comparator according to claim 7, wherein the minimum accuracy of the first calibration is greater than the minimum accuracy of the second calibration, and the minimum calibration step size of the first calibration is smaller than the minimum calibration step size of the second calibration, the minimum step size of the two calibrations being changed by setting a gating switch in the R-2RDAC array, the gating switch being controlled by the first calibration clock CLK 1.
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| CN117526740B (en) * | 2024-01-02 | 2024-03-12 | 苏州锴威特半导体股份有限公司 | Voltage comparator for correcting offset voltage |
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