CN111446965A - Energy-efficient full-dynamic comparator applied to SAR ADC - Google Patents
Energy-efficient full-dynamic comparator applied to SAR ADC Download PDFInfo
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Abstract
The invention discloses an energy-efficient full-dynamic comparator applied to an SAR ADC, which comprises a pre-amplification circuit, a latch circuit and a pre-amplification stage control circuit, wherein the pre-amplification circuit, the latch circuit and the pre-amplification stage control circuit are connected in a three-stage cascade mode through an input tube. The pre-amplification stage control circuit turns off a tail current tube in the pre-amplification circuit after the latch circuit outputs the comparison result, and sets a high level or a low level on an output node of the pre-amplification circuit according to the comparison result, so that unnecessary amplification operation of the pre-amplification circuit after comparison is finished is avoided, the latch result is maintained, and the power consumption of the comparator is further reduced on the premise of not influencing the performance of the comparator. In addition, the characteristic of cascade amplification of the pre-amplification circuit improves the pre-amplification gain and simultaneously reduces the equivalent noise of the pre-amplification stage and the latch stage at the input end; the circuit is controlled by adopting a single-phase clock signal, so that the clock load is reduced; the circuit has no static power consumption in all working phases.
Description
Technical Field
The invention relates to the field of digital-analog hybrid integrated circuit design, in particular to an energy-efficient full-dynamic comparator design suitable for SAR ADC.
Background
In recent years, with the development of very large scale integrated circuits, wireless communication and internet of things technologies, wireless sensor networks are widely applied, such as biomedical systems, environmental monitoring, mobile devices, wearable devices and the like. In these applications, the external signal collected by the wireless sensor needs to be converted into a digital signal by an analog-to-digital converter. The wireless sensor network node is generally powered by a small battery or an energy collection system, and in order to prolong the working time of equipment, the design of low power consumption of the ADC is significant. The SAR ADC is widely used in low power consumption designs due to its natural advantage of no operational amplifier architecture. The comparator is a key module in the SAR ADC, and the power consumption of the comparator is reduced while the working performance of the comparator is ensured, so that the overall power consumption of the SARADC can be effectively reduced.
The comparator widely applied in the low-power-consumption SAR ADC is a traditional two-stage full-dynamic comparator which comprises a pre-amplification stage and a latch stage, but the traditional structure reduces the noise of the comparator by increasing the capacitance load of an output node of the pre-amplification stage, and the cost of quadruple power consumption is needed when the input reference noise voltage is reduced by half. The cascade input comparator is an energy-efficient full-dynamic comparator structure, and the gain of the pre-amplification stage is improved by amplifying through a cascade input tube in the pre-amplification stage, the equivalent noise of the pre-amplification stage and the latch stage at the input end is reduced, and the power consumption is lower than that of the traditional structure under the same noise performance. However, for the comparator used in the SAR ADC, the comparator is not reset immediately after the comparison is completed, which is particularly serious in the synchronous SAR ADC. In the cascade input comparator, the pre-amplifier stage does not complete full swing charging and discharging when the latch stage outputs the comparison result in most cases, especially the change of the output node voltage of the pre-amplifier stage may be very different from the full swing, and the continuous operation of the pre-amplifier stage after the comparison result is generated may cause unnecessary power consumption. Therefore, it is of great significance to continue the research of the energy-efficient full dynamic comparator on the basis.
Disclosure of Invention
The technical problem to be solved by the present invention is to overcome the defects of the prior art, and provide an energy-efficient fully dynamic comparator suitable for an SAR ADC, to solve the problem that the pre-amplification stage in the cascade input comparator continues to work unnecessarily after the latch stage outputs the comparison result, and to further reduce the power consumption generated by the comparator.
The invention specifically adopts the following technical scheme to solve the technical problems:
an energy-efficient full dynamic comparator suitable for an SAR ADC comprises a pre-amplifying circuit, a latch circuit and a pre-amplifying stage control circuit, wherein the pre-amplifying circuit comprises a tail current tube controlled by the pre-amplifying stage control circuit, a three-stage cascade pre-amplifying input geminate transistor, a CMOS transmission gate controlled by an externally input comparison completion signal and a reset circuit controlled by a clock signal, which are sequentially connected; the latch circuit comprises a positive feedback latch formed by two NAND gates; the pre-amplification stage control circuit comprises a pre-amplification stage tail current tube control circuit and a pre-amplification stage output node setting circuit;
the pre-amplifying circuit amplifies the input signal in a comparison stage; the latch circuit performs positive feedback latch on the output result of the pre-amplifying circuit to obtain a comparison result; after the comparison result is obtained, an externally input comparison completion signal turns off a CMOS transmission gate in the pre-amplification circuit, the pre-amplification stage control circuit turns off a tail current tube in the pre-amplification circuit, and high-level or low-level setting is carried out on an output node of the pre-amplification circuit according to the comparison result, so that the latch circuit is guaranteed to keep the comparison result.
Further, in the pre-amplifying circuit: the tail current tube is a first MOS tube, the three-stage cascade pre-amplification input geminate transistors comprise second to seventh MOS tubes, the CMOS transmission gate comprises eighth to eleventh MOS tubes, the reset circuit comprises twelfth to seventeenth MOS tubes, the first to eighth MOS tubes and the eleventh MOS tube are PMOS tubes, and the ninth and tenth MOS tubes and the twelfth to seventeenth MOS tubes are NMOS tubes;
the grid electrode of the first MOS tube is connected with the output node of the pre-amplification stage control circuit, the source electrode of the first MOS tube is connected with the power supply, and the drain electrode of the first MOS tube is respectively connected with the source electrode of the second MOS tube and the source electrode of the third MOS tube; the grid electrode of the second MOS tube is connected with the first differential input signal, and the connection point of the drain electrode of the second MOS tube and the source electrode of the fourth MOS tube is connected with the drain electrode of the fourteenth MOS tube; the grid electrode of the third MOS tube is connected with a second differential input signal, and the connection point of the drain electrode of the third MOS tube and the source electrode of the fifth MOS tube is connected with the drain electrode of the fifteenth MOS tube; the grid electrode of the fourth MOS tube is connected with the first differential input signal, and the connection point of the drain electrode of the fourth MOS tube and the source electrode of the sixth MOS tube is connected with the drain electrode of the thirteenth MOS tube; the grid electrode of the fifth MOS tube is connected with the second differential input signal, and the connection point of the drain electrode of the fifth MOS tube and the source electrode of the seventh MOS tube is connected with the drain electrode of the sixteenth MOS tube; a grid electrode of the sixth MOS tube is connected with the first differential input signal, and a drain electrode of the sixth MOS tube is respectively connected with a source electrode of the eighth MOS tube and a source electrode of the ninth MOS tube; the grid electrode of the seventh MOS tube is connected with the second differential input signal, and the drain electrode of the seventh MOS tube is respectively connected with the source electrode of the tenth MOS tube and the source electrode of the eleventh MOS tube; the grid electrode of the eighth MOS tube is connected with a first comparison completion signal input from the outside, the drain electrode of the eighth MOS tube is respectively connected with the drain electrode of the ninth MOS tube and the drain electrode of the twelfth MOS tube, and the connection point of the eighth MOS tube and the drain electrode is used as a first output node of the pre-amplifying circuit; the grid electrode of the ninth MOS tube is connected with a second comparison completion signal input from the outside; the grid electrode of the tenth MOS tube is connected with a second comparison completion signal input from the outside; the drain electrode of the tenth MOS tube is respectively connected with the drain electrode of the eleventh MOS tube and the drain electrode of the seventeenth MOS tube, and the connection point of the tenth MOS tube and the seventeenth MOS tube is used as a second output node of the pre-amplifying circuit; the grid electrode of the eleventh MOS tube is connected with a first comparison completion signal input from the outside; the grid electrode of the twelfth MOS tube is connected with a clock signal; the source electrode of the twelfth MOS tube is grounded; the grid electrode of the thirteenth MOS tube is connected with a clock signal; the source electrode of the thirteenth MOS tube is grounded; the grid electrode of the fourteenth MOS tube is connected with a clock signal; the source electrode of the fourteenth MOS tube is grounded; the grid electrode of the fifteenth MOS tube is connected with a clock signal; the source electrode of the fifteenth MOS tube is grounded; the grid electrode of the sixteenth MOS tube is connected with a clock signal; the source electrode of the sixteenth MOS tube is grounded; the grid of the seventeenth MOS tube is connected with a clock signal; and the source electrode of the seventeenth MOS tube is grounded.
Furthermore, the latch circuit comprises eighteenth to twenty-fifth MOS (metal oxide semiconductor) tubes forming two NAND gates, wherein the twentieth, twenty-first, twenty-fourth and twenty-fifth MOS tubes are PMOS tubes, and the eighteenth, nineteen, twenty-second and twenty-third MOS tubes are NMOS tubes;
the connection point of the grid electrode of the eighteenth MOS tube and the grid electrode of the twenty-fourth MOS tube is connected with the first output node of the pre-amplifying circuit; the source electrode of the eighteenth MOS tube is connected with the drain electrode of the twenty-second MOS tube; the drain electrode of the eighteenth MOS tube is respectively connected with the drain electrode of the twentieth MOS tube, the grid electrode of the twenty-first MOS tube, the grid electrode of the twenty-third MOS tube and the drain electrode of the twenty-fourth MOS tube, and the connection point of the drain electrodes is used as the first output end of the comparator; the connection point of the grid of the nineteenth MOS tube and the grid of the twenty-fifth MOS tube is connected with the second output node of the pre-amplifying circuit; the source electrode of the nineteenth MOS tube is connected with the drain electrode of the twenty-third MOS tube; the drain electrode of the nineteenth MOS tube is respectively connected with the drain electrode of the twenty-first MOS tube, the grid electrode of the twentieth MOS tube, the grid electrode of the twelfth MOS tube and the drain electrode of the twenty-fifth MOS tube, and the connection point of the nineteenth MOS tube and the grid electrode of the twenty-fifth MOS tube is used as the second output end of the comparator; the source electrode of the twentieth MOS tube is connected with the power supply; the source electrode of the twenty-first MOS tube is connected with a power supply; the source electrode of the twenty-second MOS tube is grounded; the source electrode of the twenty-third MOS tube is grounded; the source electrode of the twenty-fourth MOS tube is connected with a power supply; the source electrode of the twenty-fifth MOS tube is connected with a power supply.
Further, in the pre-amplification stage control circuit: the pre-amplification stage tail current tube control circuit comprises twenty-sixth to twenty-eighth MOS tubes, the pre-amplification stage output node setting circuit comprises twenty-ninth to thirty-eighth MOS tubes, the twenty-sixth, twenty-seventh, twenty-ninth to thirty-first and thirty-fourth to thirty-sixth MOS tubes are PMOS tubes, and the twenty-eighth, thirty-second, thirty-third, thirty-seventh and thirty-eighth MOS tubes are NMOS tubes;
the grid electrode of the twenty-sixth MOS tube is connected with a second comparison completion signal input from the outside; the source electrode of the twenty-sixth MOS tube is connected with a power supply; the drain electrode of the twenty-sixth MOS tube is respectively connected with the source electrode of the twenty-seventh MOS tube and the source electrode of the twenty-eighth MOS tube, and the connection point of the twenty-sixth MOS tube and the source electrode of the twenty-eighth MOS tube is used as an output node of the pre-amplification stage control circuit; the grid electrode of the twenty-seventh MOS tube is connected with a first comparison completion signal input from the outside; the drain electrode of the twenty-seventh MOS tube is connected with a clock signal; the grid electrode of the twenty-eight MOS tube is connected with a second comparison completion signal input from the outside; the drain electrode of the twenty-eight MOS tube is connected with a clock signal; the grid electrode of the twenty-ninth MOS tube is connected with a clock signal; the source electrode of the twenty-ninth MOS tube is connected; the drain electrode of the twenty-ninth MOS tube is connected with the source electrode of the thirty-fifth MOS tube; the grid electrode of the thirty-third MOS tube is connected with the first output end of the comparator; the drain electrode of the thirty-first MOS tube is connected with the source electrode of the thirty-first MOS tube; the grid electrode of the thirty-first MOS tube is connected with a second comparison completion signal input from the outside; the connection point of the drain electrode of the thirty-first MOS tube and the drain electrode of the thirty-second MOS tube is connected with the first output node of the pre-amplifying circuit; the grid electrode of the third twelve MOS tube is connected with a first comparison completion signal input from the outside; the source electrode of the thirty-second MOS tube is connected with the drain electrode of the thirty-third MOS tube; the grid electrode of the thirteenth MOS tube is connected with the first output end of the comparator; the source electrode of the thirty-third MOS tube is grounded; the grid electrode of the thirty-fourth MOS tube is connected with a clock signal; the source electrode of the thirty-fourth MOS tube is connected with a power supply; the drain electrode of the thirty-fourth MOS tube is connected with the source electrode of the thirty-fifth MOS tube; the grid electrode of the fifteenth MOS tube is connected with the second output end of the comparator; the drain electrode of the thirty-fifth MOS tube is connected with the source electrode of the thirty-sixth MOS tube; the grid electrode of the sixteenth MOS tube is connected with a second comparison completion signal input from the outside; the drain electrode of the thirty-sixth MOS tube is connected with the drain electrode of the thirty-seventh MOS tube through a connection point and a second output node of the pre-amplifying circuit; the grid electrode of the third seventeen MOS tube is connected with a first comparison completion signal input from the outside; the source electrode of the thirty-seventh MOS tube is connected with the drain electrode of the thirty-eighth MOS tube; the grid electrode of the third eighteen MOS tube is connected with the second output end of the comparator; and the source electrode of the thirty-eighth MOS tube is grounded.
By adopting the technical scheme, the invention can produce the following technical effects:
compared with a cascade input comparator, the high-energy-efficiency full-dynamic comparator applicable to the SAR ADC provided by the invention has the advantages that a tail current tube in the pre-amplifying circuit is turned off after the latch circuit outputs a comparison result, and meanwhile, the pre-amplifying stage control circuit sets a high level or a low level to an output node of the pre-amplifying circuit according to the comparison result so as to keep the latch result, so that unnecessary work of the pre-amplifying circuit after the comparison is finished is avoided, and the power consumption of the comparator is further reduced on the premise of not influencing the performance of the comparator. In addition, the high-energy-efficiency full-dynamic comparator suitable for the SAR ADC inherits the power consumption advantage of a cascade input comparator to the traditional two-stage full-dynamic comparator, the characteristic of cascade amplification of a pre-amplification circuit improves pre-amplification gain, and meanwhile, equivalent noise of a pre-amplification stage and a latch stage at the input end is reduced; the single-phase clock signal is adopted, so that the clock load is reduced; the circuit has no static power consumption in all working phases.
Drawings
FIG. 1 is a circuit schematic of a cascaded input comparator;
FIG. 2 is a block diagram of the present invention and its general architecture for use in a SAR ADC;
FIG. 3 is a schematic circuit diagram of an energy-efficient full dynamic comparator applied to a SAR ADC according to the present invention;
FIG. 4 is a waveform diagram of the input and output of the cascaded input comparator;
FIG. 5 is a waveform diagram of the input and output of the energy-efficient full dynamic comparator applied to the SAR ADC according to the present invention;
FIG. 6 is a graph of the output spectrum of a cascade input comparator applied to a 10-bit SAR ADC;
fig. 7 is a graph of an output spectrum of an energy-efficient full dynamic comparator applied to a SAR ADC according to the present invention applied to a 10-bit SAR ADC.
Detailed Description
The invention will be further described with reference to the accompanying drawings.
Fig. 1 shows a cascade input comparator, which mainly includes a pre-amplifying circuit and a latch circuit. The pre-amplifying circuit comprises a tail current tube M1, differential input tubes M2, M3, M4, M5, M6 and M7, reset tubes M8, M9, M10, M11, M12 and M13, wherein M1, M2, M3, M4, M5, M6 and M7 are PMOS tubes, and M8, M9, M10, M11, M12 and M13 are NMOS tubes. The latch circuit comprises M14, M15, M16, M17, M18, M19, M20 and M21 which form two NAND gates, wherein M16, M17, M20 and M21 are PMOS tubes, and M14, M15, M18 and M19 are NMOS tubes.
The specific structure of the cascade input comparator is as follows:
the source of M is connected with the source of M, the drain of M is connected with the source of M and the source of M, the grid of M is connected with a differential input signal Vip, the drain of M is connected with the source of M, the connection point of the drain of M is connected with the drain of M, the grid of M is connected with the differential input signal Vip, the drain of M is connected with the drain of M as the output node Vop of the preamplification circuit, the drain of M is connected with the drain of M as the output node Von of the preamplification circuit, the grid of M is connected with the clock signal C, the drain of M is connected with the drain of M, the source of M is connected with the clock signal Von, the drain of M is connected with the drain of the clock signal C, the drain of M is connected with the source of the clock signal VDD, the drain of M, the source of M, the drain of M is connected with the source of the clock signal VDD, the source of M, the drain of M, the source of M is connected with the source of the clock signal C, the drain of the source of the preamplifier circuit, the drain of M is connected with the drain of the M, the drain of the clock signal M is connected with the source of the clock signal VDD, the drain of the M, the drain of the source of the M, the preamplifier circuit, the drain of the M, the source of the M is connected with the source of the drain of the M, the source of the drain of the M, the source of the drain of the M, the drain.
The method comprises the steps of firstly, carrying out a single-phase clock control on a latch circuit, carrying out a cascade input comparator, carrying out a single-phase clock control on the latch circuit, carrying out a single-phase clock control on the cascade input comparator, the single-phase clock control on the cascade input comparator, carrying out the single-phase clock control on the cascade input comparator, carrying out the cascade input of the cascade input comparator, carrying out the cascade input of the cascade.
Fig. 2 is a block diagram of an energy-efficient fully dynamic comparator and its overall structure applied in an SAR ADC. The high-energy-efficiency full-dynamic comparator mainly comprises a pre-amplifying circuit, a latch circuit and a pre-amplifying stage control circuit, and the structure adopts a full-differential structure, so that the influence of environmental factors on the circuit structure of the whole comparator is effectively inhibited. The pre-amplification circuit pre-amplifies the differential input signals Vip and Vin of the comparator; the latch circuit latches according to the output node Vop and Von of the pre-amplifying circuit to obtain comparison results OUTP and OUTN; after the comparison result is generated, the pre-amplification stage control circuit controls the pre-amplification circuit according to the comparison result and the comparison completion signals CMP and CMP1, and unnecessary work of the pre-amplification stage is avoided.
The overall structure of the energy-efficient fully dynamic comparator provided by the invention when applied to the SAR ADC is the same as that of the traditional two-stage dynamic comparator and the cascade input comparator. As shown in fig. 2, the SAR ADC employs synchronous timing and the clock generation circuit provides clock signals for the sampling switches, comparators, and digital control logic. When the sampling clock arrives, the sampling switch samples the analog input quantity to the upper polar plate of the capacitor DAC, the upper polar plate of the capacitor DAC is connected with the input end of the comparator, and the lower polar plate is controlled by the digital control logic circuit. The comparator compares the voltage of the upper plate of the capacitor DAC, the output signal of the comparator forms a comparison completion signal CMP through an exclusive-OR gate, the CMP provides a trigger signal for the digital control logic circuit through a plurality of inverters, the exclusive-OR gate and the inverters are inherent circuits in the SARADC structure and are not related to the type of the comparator, namely CMP and CMP1 are inherent signals in the SAR ADC. And after the digital control logic circuit is triggered, the lower polar plate of the DAC capacitor is controlled to form corresponding reference voltage according to the output signal of the comparator, and then the next comparison is carried out until all comparison results are output to form a complete digital code.
Fig. 3 is a schematic circuit diagram of an energy-efficient fully dynamic comparator applied to a SAR ADC according to the present invention, which mainly includes a pre-amplifier circuit, a latch circuit, and a pre-amplifier stage control circuit. The pre-amplifying circuit comprises a tail current tube controlled by a pre-amplifying stage control circuit, a three-stage cascade pre-amplifying input geminate transistor, a CMOS transmission gate controlled by an externally input comparison completion signal and a reset circuit controlled by a clock signal; the latch circuit comprises a positive feedback latch formed by two NAND gates and has a reset function; the pre-amplification stage control circuit comprises a pre-amplification stage tail current tube control circuit and a pre-amplification stage output node setting circuit.
The pre-amplification circuit amplifies the input signal in a comparison stage, and the pre-amplification gain is improved by using a three-stage cascade structure of an input tube; the latch circuit performs positive feedback latch on the output result of the pre-amplifying circuit to obtain a comparison result; after the comparison result is obtained, an externally input comparison completion signal turns off a CMOS transmission gate in the pre-amplification circuit, the pre-amplification stage control circuit turns off a tail current tube in the pre-amplification circuit, and high-level or low-level setting is carried out on an output node of the pre-amplification circuit according to the comparison result, so that the latch circuit is guaranteed to keep the comparison result.
The pre-amplifying circuit comprises a tail current tube M1, differential input tubes M2, M3, M4, M5, M6 and M7, CMOS transmission gates M8, M9, M10 and M11, reset tubes M12, M13, M14, M15, M16 and M17, wherein M1, M2, M3, M4, M5, M6, M7, M8 and M11 are PMOS tubes, and M9, M10, M12, M13, M14, M15, M16 and M17 are NMOS tubes.
The clock signal pre-amplifying circuit comprises a M, a M gate, a M drain, a M source, a M drain, a M source, a M drain, a M source, a M drain, a M clock signal, a clock signal.
The latch circuit comprises M18, M19, M20, M21, M22, M23, M24 and M25 which form two NAND gates, wherein M20, M21, M24 and M25 are PMOS tubes, and M18, M19, M22 and M23 are NMOS tubes.
The grid of the M18 is connected with the grid of the M24 and is connected with the output node Vop of the pre-amplifying circuit; the source of M18 is connected with the drain of M22; the drain of M18 is connected with the drain of M20, the gate of M21, the gate of M23 and the drain of M24 respectively, and the connection point is used as a comparator output signal OUTP; the grid of the M19 is connected with the grid of the M25 and is connected with the output node Von of the pre-amplifying circuit; the source of M19 is connected with the drain of M23; the drain of M19 is connected with the drain of M21, the gate of M20, the gate of M22 and the drain of M25 respectively, and the connection point is used as a comparator output signal OUTN; the source of M20 is connected with VDD; the source of M21 is connected with VDD; the source of M22 is grounded; the source of M23 is grounded; the source of M24 is connected with VDD; the source of M25 is connected to VDD.
The pre-amplification stage control circuit comprises M26, M27 and M28 which form a pre-amplification stage tail current tube control circuit, and M29, M30, M31, M32, M33, M34, M35, M36, M37 and M38 which form a pre-amplification stage output node setting circuit, wherein M26, M27, M29, M30, M31, M34, M35 and M36 are PMOS tubes, and M28, M32, M33, M37 and M38 are NMOS tubes.
The gate of M26 is connected to the comparison completion signal CMP1 inputted from the outside, the source of M26 is connected to VDD, the drain of M26 is connected to the source of M26 and the source of M26, the connection point is used as the output node C26 KP of the pre-amplification stage control circuit, the gate of M26 is connected to the comparison completion signal CMP inputted from the outside, the drain of M26 is connected to the clock signal C26K, the gate of M26 is connected to the comparison completion signal CMP 26 inputted from the outside, the drain of M26 is connected to the source of M26, the gate of M26 is connected to the comparator output signal OUTP, the drain of M26 is connected to the source of M26, the gate of M26 is connected to the comparison completion signal CMP 26K, the source of M26 is connected to the drain of M26, the drain of M26 is connected to the output node Vop of the pre-amplification stage control circuit, the drain of M26 is connected to the drain of M26, the comparison completion signal CMP 26, the drain of M26 is connected to the drain of the comparison circuit, the drain of M26 is connected to the drain of the comparison completion signal CMP 26, the drain of the comparison circuit, the drain of M26 is connected to the drain of the comparison circuit, the comparison output node M26, the drain of the comparison output node M26 is connected to the comparison completion signal CMP 26, the drain of the comparison output node M26, the drain of the comparison output signal CMP 26, the comparison output node M26, the drain of the comparison output node M26 is connected to the drain of the comparison output node M26, the comparison output signal CMP 26, the drain of the M26, the drain of the comparison output node M26, the.
The energy-efficient full-dynamic comparator applied to the SAR ADC provided by the invention realizes resetting and comparison by adopting a single-phase clock.
When the clock signal C K is in a high level, the comparator is in a reset state, the initial time CMP is in a high level, the CMP is in a low level, the C KP is in a high level, a tail current tube M of the pre-amplifying circuit is in a cut-off state, the reset tubes M, M and M are conducted, nodes Vop, Von of the pre-amplifying circuit are all discharged to a low level through the reset tubes, and simultaneously M and M are in a cut-off state, static current of VDD to the ground through Vop, M or Von and M is avoided, M and M in the pre-amplifying circuit is conducted after the output nodes Vop and Von of the pre-amplifying circuit are in a low level, M and M in the latch circuit are conducted, the comparator output signals OUTP and OUTN are charged to VDD, the CMP is changed to a low level and a high level after OUTP and OUTN are charged to VDD, the clock signal C K is transmitted to the C KP through M and M, the C KP is still in a high level, M is still in a cut-off state, and simultaneously, a connection point of M, M and M are discharged to a low level through a.
The method comprises the steps of receiving a clock signal C K, a voltage regulator, a voltage.
Compared with the cascade input comparator shown in fig. 1, the high-energy-efficiency full-dynamic comparator applied to the SAR ADC of the present invention turns off the tail current tube in the pre-amplifying circuit after the latch circuit outputs the comparison result, and the pre-amplifying stage control circuit sets the output node of the pre-amplifying circuit at a high level or a low level according to the comparison result to maintain the latch result, thereby avoiding unnecessary amplification operation after the comparison of the pre-amplifying circuit is completed, and further reducing the power consumption of the comparator without affecting the performance of the comparator. In addition, the characteristic of cascade amplification of the pre-amplification circuit improves the pre-amplification gain, simultaneously reduces the equivalent noise of the pre-amplification stage and the latch stage at the input end, and inherits the power consumption advantage of the cascade input comparator to the traditional two-stage full dynamic comparator; the single-phase clock signal is adopted, so that the clock load is reduced; the circuit has no static power consumption in all working phases.
Fig. 4 shows the input and output waveforms of the cascaded input comparator. The clock signal frequency of the comparator is 2.2MHz, the VDD is 600mV, the common mode input voltage of the comparator is 300mV, and the differential mode input voltage is 30 mV. The waveforms at the various nodes of the comparators are shown in fig. 4, and it can be seen that the differential mode voltages increase sequentially from Vop1 and Von1 to Vop and Von, confirming that the cascaded input comparators can improve the gain of the pre-amplifier stage. However, when OUTn goes low, the comparator will not reset immediately, and at this time, Vop1, Von1, Vop2, Von2, Vop and Von all do not complete full swing charging, especially the Vop voltage at the node is small, and VDD continues to charge these nodes, which may generate unnecessary power consumption.
Fig. 5 is a waveform diagram of input and output of the high-energy-efficiency full-dynamic comparator applied to the SAR ADC according to the present invention, where the clock signal frequency of the comparator is 2.2MHz, VDD is 600mV, the common-mode input voltage of the comparator is 300mV, and the differential-mode input voltage is 30 mV., waveforms of respective nodes of the comparator are shown in fig. 5, it can be seen that the differential-mode voltages sequentially increase from Vop1 and Von1 to Vop and Von before OUTn becomes low level, which proves that the high-energy-efficiency full-dynamic comparator provided by the present invention can increase the gain of the pre-amplifier stage, inherit the power consumption advantage of the cascade input comparator to the conventional two-stage dynamic comparator after OUTn becomes low level, C L KP is turned to low level, the pre-amplifier stage stops charging, at the same time Vop is set to low level and Von is set to high level to maintain the result, and it can be seen that Vop1, Von1, Vop2, Von2 and Vop are all fully charged at the full swing of the cascade input comparator, which saves most power consumption.
Fig. 6 is a graph of an output spectrum of a cascade input comparator applied to a 10-bit SAR ADC. The ADC power supply voltage is 600mV, the sampling rate is 200KHz, the common mode voltage is 300mV, and the input signal frequency is 100 KHz. As can be seen from the spectrogram, the effective digit of the ADC reaches 9.95 bits, the spurious-free dynamic range reaches 76.42dBc, and the power consumption of the cascade input comparator is measured to be 29.6 nW.
Fig. 7 is a graph of an output spectrum of an energy-efficient full dynamic comparator applied to a 10-bit SAR ADC according to the present invention. The ADC power supply voltage is 600mV, the sampling rate is 200KHz, the common mode voltage is 300mV, and the input signal frequency is 100 KHz. As can be seen from the frequency spectrum diagram, the effective digit of the ADC reaches 9.94 bits, and the spurious-free dynamic range reaches 78.69dBc, so that the energy-efficient full-dynamic comparator provided by the invention basically cannot influence the system performance. The measurement shows that the power consumption of the high-energy-efficiency full-dynamic comparator provided by the invention is 24.3nW, and is reduced by 17.9 percent compared with the power consumption of a cascade input comparator. Therefore, the invention can achieve higher energy efficiency on the basis of cascading input comparators.
The embodiments of the present invention have been described in detail with reference to the drawings, but the present invention is not limited to the above embodiments, and various changes can be made without departing from the spirit of the present invention within the knowledge of those skilled in the art.
Claims (4)
1. An energy-efficient full dynamic comparator applied to SAR ADC is characterized in that: the pre-amplifying circuit comprises a tail current tube controlled by the pre-amplifying stage control circuit, three-stage cascaded pre-amplifying input geminate transistors, a CMOS transmission gate controlled by an externally input comparison completion signal and a reset circuit controlled by a clock signal, which are connected in sequence; the latch circuit comprises a positive feedback latch formed by two NAND gates; the pre-amplification stage control circuit comprises a pre-amplification stage tail current tube control circuit and a pre-amplification stage output node setting circuit;
the pre-amplifying circuit amplifies the input signal in a comparison stage; the latch circuit performs positive feedback latch on the output result of the pre-amplifying circuit to obtain a comparison result; after the comparison result is obtained, an externally input comparison completion signal turns off a CMOS transmission gate in the pre-amplification circuit, the pre-amplification stage control circuit turns off a tail current tube in the pre-amplification circuit, and high-level or low-level setting is carried out on an output node of the pre-amplification circuit according to the comparison result, so that the latch circuit is guaranteed to keep the comparison result.
2. The energy-efficient full dynamic comparator applied to the SAR ADC in claim 1, wherein: in the pre-amplification circuit: the tail current tube is a first MOS tube, the three-stage cascade pre-amplification input geminate transistors comprise second to seventh MOS tubes, the CMOS transmission gate comprises eighth to eleventh MOS tubes, the reset circuit comprises twelfth to seventeenth MOS tubes, the first to eighth MOS tubes and the eleventh MOS tube are PMOS tubes, and the ninth and tenth MOS tubes and the twelfth to seventeenth MOS tubes are NMOS tubes;
the grid electrode of the first MOS tube is connected with the output node of the pre-amplification stage control circuit, the source electrode of the first MOS tube is connected with the power supply, and the drain electrode of the first MOS tube is respectively connected with the source electrode of the second MOS tube and the source electrode of the third MOS tube; the grid electrode of the second MOS tube is connected with the first differential input signal, and the connection point of the drain electrode of the second MOS tube and the source electrode of the fourth MOS tube is connected with the drain electrode of the fourteenth MOS tube; the grid electrode of the third MOS tube is connected with a second differential input signal, and the connection point of the drain electrode of the third MOS tube and the source electrode of the fifth MOS tube is connected with the drain electrode of the fifteenth MOS tube; the grid electrode of the fourth MOS tube is connected with the first differential input signal, and the connection point of the drain electrode of the fourth MOS tube and the source electrode of the sixth MOS tube is connected with the drain electrode of the thirteenth MOS tube; the grid electrode of the fifth MOS tube is connected with the second differential input signal, and the connection point of the drain electrode of the fifth MOS tube and the source electrode of the seventh MOS tube is connected with the drain electrode of the sixteenth MOS tube; a grid electrode of the sixth MOS tube is connected with the first differential input signal, and a drain electrode of the sixth MOS tube is respectively connected with a source electrode of the eighth MOS tube and a source electrode of the ninth MOS tube; the grid electrode of the seventh MOS tube is connected with the second differential input signal, and the drain electrode of the seventh MOS tube is respectively connected with the source electrode of the tenth MOS tube and the source electrode of the eleventh MOS tube; the grid electrode of the eighth MOS tube is connected with a first comparison completion signal input from the outside, the drain electrode of the eighth MOS tube is respectively connected with the drain electrode of the ninth MOS tube and the drain electrode of the twelfth MOS tube, and the connection point of the eighth MOS tube and the drain electrode is used as a first output node of the pre-amplifying circuit; the grid electrode of the ninth MOS tube is connected with a second comparison completion signal input from the outside; the grid electrode of the tenth MOS tube is connected with a second comparison completion signal input from the outside; the drain electrode of the tenth MOS tube is respectively connected with the drain electrode of the eleventh MOS tube and the drain electrode of the seventeenth MOS tube, and the connection point of the tenth MOS tube and the seventeenth MOS tube is used as a second output node of the pre-amplifying circuit; the grid electrode of the eleventh MOS tube is connected with a first comparison completion signal input from the outside; the grid electrode of the twelfth MOS tube is connected with a clock signal; the source electrode of the twelfth MOS tube is grounded; the grid electrode of the thirteenth MOS tube is connected with a clock signal; the source electrode of the thirteenth MOS tube is grounded; the grid electrode of the fourteenth MOS tube is connected with a clock signal; the source electrode of the fourteenth MOS tube is grounded; the grid electrode of the fifteenth MOS tube is connected with a clock signal; the source electrode of the fifteenth MOS tube is grounded; the grid electrode of the sixteenth MOS tube is connected with a clock signal; the source electrode of the sixteenth MOS tube is grounded; the grid of the seventeenth MOS tube is connected with a clock signal; and the source electrode of the seventeenth MOS tube is grounded.
3. The energy-efficient full dynamic comparator applied to the SAR ADC in claim 1, wherein: the latch circuit comprises eighteenth to twenty-fifth MOS (metal oxide semiconductor) tubes forming two NAND gates, wherein the twentieth, twenty-first, twenty-fourth and twenty-fifth MOS tubes are PMOS tubes, and the eighteenth, nineteen, twenty-second and twenty-third MOS tubes are NMOS tubes;
the connection point of the grid electrode of the eighteenth MOS tube and the grid electrode of the twenty-fourth MOS tube is connected with the first output node of the pre-amplifying circuit; the source electrode of the eighteenth MOS tube is connected with the drain electrode of the twenty-second MOS tube; the drain electrode of the eighteenth MOS tube is respectively connected with the drain electrode of the twentieth MOS tube, the grid electrode of the twenty-first MOS tube, the grid electrode of the twenty-third MOS tube and the drain electrode of the twenty-fourth MOS tube, and the connection point of the drain electrodes is used as the first output end of the comparator; the connection point of the grid of the nineteenth MOS tube and the grid of the twenty-fifth MOS tube is connected with the second output node of the pre-amplifying circuit; the source electrode of the nineteenth MOS tube is connected with the drain electrode of the twenty-third MOS tube; the drain electrode of the nineteenth MOS tube is respectively connected with the drain electrode of the twenty-first MOS tube, the grid electrode of the twentieth MOS tube, the grid electrode of the twelfth MOS tube and the drain electrode of the twenty-fifth MOS tube, and the connection point of the nineteenth MOS tube and the grid electrode of the twenty-fifth MOS tube is used as the second output end of the comparator; the source electrode of the twentieth MOS tube is connected with the power supply; the source electrode of the twenty-first MOS tube is connected with a power supply; the source electrode of the twenty-second MOS tube is grounded; the source electrode of the twenty-third MOS tube is grounded; the source electrode of the twenty-fourth MOS tube is connected with a power supply; the source electrode of the twenty-fifth MOS tube is connected with a power supply.
4. The energy-efficient full dynamic comparator applied to the SAR ADC in claim 1, wherein: in the pre-amplifier stage control circuit: the pre-amplification stage tail current tube control circuit comprises twenty-sixth to twenty-eighth MOS tubes, the pre-amplification stage output node setting circuit comprises twenty-ninth to thirty-eighth MOS tubes, the twenty-sixth, twenty-seventh, twenty-ninth to thirty-first and thirty-fourth to thirty-sixth MOS tubes are PMOS tubes, and the twenty-eighth, thirty-second, thirty-third, thirty-seventh and thirty-eighth MOS tubes are NMOS tubes;
the grid electrode of the twenty-sixth MOS tube is connected with a second comparison completion signal input from the outside; the source electrode of the twenty-sixth MOS tube is connected with a power supply; the drain electrode of the twenty-sixth MOS tube is respectively connected with the source electrode of the twenty-seventh MOS tube and the source electrode of the twenty-eighth MOS tube, and the connection point of the twenty-sixth MOS tube and the source electrode of the twenty-eighth MOS tube is used as an output node of the pre-amplification stage control circuit; the grid electrode of the twenty-seventh MOS tube is connected with a first comparison completion signal input from the outside; the drain electrode of the twenty-seventh MOS tube is connected with a clock signal; the grid electrode of the twenty-eight MOS tube is connected with a second comparison completion signal input from the outside; the drain electrode of the twenty-eight MOS tube is connected with a clock signal; the grid electrode of the twenty-ninth MOS tube is connected with a clock signal; the source electrode of the twenty-ninth MOS tube is connected with a power supply; the drain electrode of the twenty-ninth MOS tube is connected with the source electrode of the thirty-fifth MOS tube; the grid electrode of the thirty-third MOS tube is connected with the first output end of the comparator; the drain electrode of the thirty-first MOS tube is connected with the source electrode of the thirty-first MOS tube; the grid electrode of the thirty-first MOS tube is connected with a second comparison completion signal input from the outside; the connection point of the drain electrode of the thirty-first MOS tube and the drain electrode of the thirty-second MOS tube is connected with the first output node of the pre-amplifying circuit; the grid electrode of the third twelve MOS tube is connected with a first comparison completion signal input from the outside; the source electrode of the thirty-second MOS tube is connected with the drain electrode of the thirty-third MOS tube; the grid electrode of the thirteenth MOS tube is connected with the first output end of the comparator; the source electrode of the thirty-third MOS tube is grounded; the grid electrode of the thirty-fourth MOS tube is connected with a clock signal; the source electrode of the thirty-fourth MOS tube is connected with a power supply; the drain electrode of the thirty-fourth MOS tube is connected with the source electrode of the thirty-fifth MOS tube; the grid electrode of the fifteenth MOS tube is connected with the second output end of the comparator; the drain electrode of the thirty-fifth MOS tube is connected with the source electrode of the thirty-sixth MOS tube; the grid electrode of the sixteenth MOS tube is connected with a second comparison completion signal input from the outside; the drain electrode of the thirty-sixth MOS tube is connected with the drain electrode of the thirty-seventh MOS tube through a connection point and a second output node of the pre-amplifying circuit; the grid electrode of the third seventeen MOS tube is connected with a first comparison completion signal input from the outside; the source electrode of the thirty-seventh MOS tube is connected with the drain electrode of the thirty-eighth MOS tube; the grid electrode of the third eighteen MOS tube is connected with the second output end of the comparator; and the source electrode of the thirty-eighth MOS tube is grounded.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112290949A (en) * | 2020-09-21 | 2021-01-29 | 西安电子科技大学 | Common mode level switches high-speed comparator |
| CN114301480A (en) * | 2022-01-14 | 2022-04-08 | 中国人民解放军国防科技大学 | High-speed sampling circuit and SerDes receiver comprising same |
| CN116470889A (en) * | 2023-04-10 | 2023-07-21 | 北京大学 | Comparator circuit, analog-digital converter and electronic equipment |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101282117A (en) * | 2007-04-05 | 2008-10-08 | 中国科学院微电子研究所 | Dynamic comparer |
| CN107483033A (en) * | 2017-07-31 | 2017-12-15 | 天津大学 | A kind of low power consumption comparator structure of band disappearance conditioning function |
| CN110445494A (en) * | 2019-08-20 | 2019-11-12 | 东南大学 | A kind of automatic shutoff comparator suitable for non-loop structure SAR ADC |
-
2020
- 2020-04-14 CN CN202010289536.5A patent/CN111446965B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101282117A (en) * | 2007-04-05 | 2008-10-08 | 中国科学院微电子研究所 | Dynamic comparer |
| CN107483033A (en) * | 2017-07-31 | 2017-12-15 | 天津大学 | A kind of low power consumption comparator structure of band disappearance conditioning function |
| CN110445494A (en) * | 2019-08-20 | 2019-11-12 | 东南大学 | A kind of automatic shutoff comparator suitable for non-loop structure SAR ADC |
Non-Patent Citations (2)
| Title |
|---|
| HSIEH S E等: "A 0.44-fJ/conversion-Step 11-bit 600-kS/s SAR ADC With semi-resting DAC" * |
| 孙帆等: "一种新型的12位SAR ADC设计" * |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112290949A (en) * | 2020-09-21 | 2021-01-29 | 西安电子科技大学 | Common mode level switches high-speed comparator |
| CN112290949B (en) * | 2020-09-21 | 2023-02-24 | 西安电子科技大学 | Common mode level switches high-speed comparator |
| CN114301480A (en) * | 2022-01-14 | 2022-04-08 | 中国人民解放军国防科技大学 | High-speed sampling circuit and SerDes receiver comprising same |
| CN114301480B (en) * | 2022-01-14 | 2024-02-13 | 中国人民解放军国防科技大学 | High-speed sampling circuit and SerDes receiver comprising same |
| CN116470889A (en) * | 2023-04-10 | 2023-07-21 | 北京大学 | Comparator circuit, analog-digital converter and electronic equipment |
| CN116470889B (en) * | 2023-04-10 | 2024-04-16 | 北京大学 | Comparator circuit, analog-digital converter and electronic equipment |
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