CN112448721B - Low-power consumption comparator with low delay distortion characteristic of self-bias circuit - Google Patents

Low-power consumption comparator with low delay distortion characteristic of self-bias circuit Download PDF

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CN112448721B
CN112448721B CN201910805369.2A CN201910805369A CN112448721B CN 112448721 B CN112448721 B CN 112448721B CN 201910805369 A CN201910805369 A CN 201910805369A CN 112448721 B CN112448721 B CN 112448721B
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comparator
transistors
capacitor
electrode
drain electrode
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CN112448721A (en
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徐江涛
史晓琳
聂凯明
高静
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Tianjin University Marine Technology Research Institute
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/22—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
    • H03K5/24—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
    • H03K5/2472—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using field effect transistors
    • H03K5/2481—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using field effect transistors with at least one differential stage
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/22—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
    • H03K5/24—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
    • H03K5/2472—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using field effect transistors
    • H03K5/249—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using field effect transistors using clock signals
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

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  • Nonlinear Science (AREA)
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  • Analogue/Digital Conversion (AREA)
  • Manipulation Of Pulses (AREA)
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Abstract

A low-power consumption comparator with a self-bias circuit and low delay distortion characteristic is composed of 10 MOSFET transistors M1-M10, two capacitors CP and CN and six switches SW 1-SW 6; transistors M1-M4 are input stages of the comparator, two transistors M5 and M6 are current limiters of the input stages of the comparator, and M7-M10 are bias stages of the comparator. The gates of transistors M5 and M6 are connected to M7 and M10 in the bias stage so that the current flowing through M5, M6 is of a certain value. The gates of transistors M8, M9 are connected to the gates of transistors M5, M6, M7 and M10, thereby forming a current mirror structure that can effectively limit the current through the input stage. The comparator can effectively realize high conversion precision, is applicable to asynchronous ADCs, can ensure the precision of the data used for recording the digital signals and the time stamp used for generating the digital signals in the ADCs, and enlarges the application occasions of the ADCs.

Description

Low-power consumption comparator with low delay distortion characteristic of self-bias circuit
Technical Field
The invention belongs to the field of analog integrated circuits, and particularly relates to a low-power consumption comparator with a self-bias circuit and low delay distortion characteristic.
Background
The ADC converts an analog input, such as voltage or current, to a digital output, which may be a digital signal. In a typical linear ADC, the minimum and maximum values of the digital code that it produces may be determined by the maximum and minimum values of the input analog signal. The input analog signal is limited by the high and low operating voltages of the ADC. The intermediate analog input signal is linearly mapped and quantized into a digital signal by the ADC. In a conventional ADC, an analog input signal is collected by a digital-to-analog converter (Dig ital-to-a na log converter, DAC).
The output of the DAC is coupled to a clock comparator, which compares at a particular time according to a clock signal. The clock comparator is polled at a particular time within a clock cycle to determine whether the input signal is greater than or less than a predetermined signal. The comparison process proceeds according to the result of the clock comparator.
In a conventional ADC, an analog input signal is sampled into a digital-to-analog converter (DAC). The output of the DAC is coupled to a clock comparator, which compares at a particular time according to a clock signal. The clock comparator is polled at a particular time within a clock cycle to determine whether the input signal is greater than or less than a predetermined signal. The comparison process proceeds according to the result of the clock comparator.
In an asynchronous ADC, the analog input signal is not sampled like a conventional ADC, where the input signal is sampled at a specific time. In an asynchronous ADC, the analog input is compared to a reference signal, which may be stationary or continuous. The stationary reference comprises a direct current reference signal and the continuous reference comprises an alternating current reference signal. The comparator in an asynchronous ADC must operate in a continuous mode, meaning that it produces an output on the input signal that is equal to the reference signal, without the need for a clock to determine when sampling occurs. To achieve an accurate analog-to-digital converted version, the two tuples of the numbers and the time stamps generated by the analog-to-digital converter must be accurate. Any delay of the comparator results in an error in the analog-to-digital conversion.
Fig. 1 is a schematic diagram of a conventional low power comparator. The operation voltage of the comparator is GND to VDD. Wherein differential inputs Vinp and Vinn are the positive and negative inputs of the comparator, respectively, and differential outputs Voutp and Voutn are the positive and negative outputs of the comparator, respectively. When the positive input voltage is greater than the negative input voltage, the comparator toggles, i.e., the positive output voltage Voutp approaches VDD, and the negative output voltage Voutn may approach GND.
The comparator is composed of four transistors M1-M4, the source stages of the transistors M1 and M3 are connected to VDD, and the sources of the transistors M2 and M4 are connected to GND. Such a conventional comparator has several drawbacks: the comparator does not implement a complete differential because it does not have any common node or virtual ground. Moreover, the leakage current through the comparator is a strong function of the VDD to GND voltage difference and the voltage transition magnitudes at the inputs Vinp and Vinn. Furthermore, the comparator is sensitive to common mode voltage variations between the voltages at the inputs. Due to these drawbacks, the delay distortion of the comparator is high, and asynchronous ADC is not applicable. Therefore, the patent proposes a low power consumption comparator with low delay distortion characteristics of a self-bias circuit, thereby effectively realizing high conversion accuracy.
Disclosure of Invention
Aiming at the problems existing in the prior art, the invention provides the low-power consumption comparator with the low delay distortion characteristic of the self-bias circuit, which does not need to provide bias voltage externally, has common mode nodes and virtual ground, and is beneficial to reducing the delay distortion of the comparator, thereby effectively realizing high conversion precision.
A low-power consumption comparator with low delay distortion characteristic of a self-bias circuit is shown in a figure 2, and comprises 10 MOSFET transistors M1-M10, two capacitors CP and CN and six switches SW 1-SW 6, wherein M1, M3, M5, M7 and M8 are P-type MOSFETs, and M2, M4, M6, M9 and M10 are N-type MOSFETs. The specific connection relation is as follows: the source electrode of M5 and the source electrode of M7 are connected with a power supply VDD, the grid electrode of M5 is connected with the grid electrode of M7, and the drain electrode of M5 is connected with the source electrodes of M1 and M3; the drain electrode of M3 is connected with the drain electrode of M4 and is used as the positive output end Voutp of the comparator, and the grid electrode of M3 is connected with the grid electrode of M4; the source electrode of M4 and the source electrode of M2 are connected with the drain electrode of M6; the drain electrode of the M1 is connected with the drain electrode of the M2 and serves as a negative output end Voutn of the comparator, and the grid electrode of the M1 is connected with the grid electrode of the M2; the M6 source electrode and the M10 source electrode are connected with GND; the grid electrode of M8 is connected with the grid electrode of M9 and the grid electrodes of M5, M6, M7 and M10; the drain electrode of M8 is connected with the drain electrode of M9; the switch SW1 is bridged between the drain and the gate of M3; the switch SW2 is bridged between the drain electrode and the grid electrode of the M1; the positive input voltage Vinp of the comparator is connected to the left plate of the capacitor CP through a switch SW3, and the common mode voltage VCM of the comparator is connected to the left plate of the capacitor CP through a switch SW 4; the right plate of the capacitor CP is connected to the gate of M1; the comparator negative input voltage Vinn is connected to the right plate of the capacitor CN through a switch SW5, and the comparator common-mode voltage VCM is connected to the left plate of the capacitor CN through a switch SW 6; the left plate of the capacitor CN is connected to the gate of M3.
A low-power consumption comparator with low delay distortion characteristic of a self-bias circuit specifically works as follows: transistors M1-M4 are input stages of the comparator, two transistors M5 and M6 are current limiters of the input stages of the comparator, and M7-M10 are bias stages of the comparator. The gates of transistors M5 and M6 are connected to M7 and M10 in the bias stage such that the current through M5, M6 is of a particular value, which is related to the aspect ratio of M7-M10. The gates of transistors M8, M9 are connected to the gates of transistors M5, M6, M7 and M10, thereby forming a current mirror structure that can effectively limit the current through the input stage.
Figure SMS_1
1 and->
Figure SMS_2
2 are two non-overlapping clocks. When->
Figure SMS_3
When 1 is high, SW1, SW2, SW4, SW6 are closed and the common mode voltage VCM is picked up to the left plate of capacitor CP and the right plate of capacitor CN, respectively. The common mode voltage of the input stage of the comparator is sampled to the right plate of capacitor CP and the left plate of capacitor CN by closed SW1 and SW2, respectively. In this process, any offset on both sides of the input stage due to mismatch is eliminated, thereby achieving self-biasing of the comparator. When->
Figure SMS_4
When 2 is high, the switches SW3 and SW5 are in the closed state and the other switches are in the open state, which is used to implement the comparator function. When the voltages Vinp and Vinn are equal to the common mode voltage VCM, the output voltage is equal to the common mode voltage VCM. When the input voltages Vinp and Vinn are not equal to the common mode voltage VCM, the output voltage fluctuates centered around the common mode voltage VCM.
A low power consumption comparator having a low delay distortion characteristic of a self-bias circuit, thereby effectively realizing high conversion accuracy. The accuracy of the binary groups generated by the ADC, namely the data used for recording the digital signals and the time stamp used for generating the digital signals, is ensured, and the application occasion of the ADC is further enlarged.
Drawings
FIG. 1 is a schematic diagram of a conventional low power comparator circuit;
fig. 2 is a low power comparator with low delay distortion characteristics for a self-biasing circuit according to the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more clear, a specific description of embodiments of the present invention will be given below with reference to examples. In this example, M1, M3, M5, M7, M8 are PMOS transistors, M2, M4, M6, M9, M10 are NMOS transistors. The specific relation of the width-to-length ratios of the transistors in the comparator is as follows: m5/m7=m6/m10=2×m1/m8=2×m3/m8=2×m2/m9=2×m4/M9. The gate length of each MOS tube is 180nm; m5, M7, M8 gate width is 1um; m1 and M3 have a gate width of 500nm; the gate width of M6, M9 and M10 is 700nm; the gate width of M2 and M4 is 350nm. The capacitance of the capacitors CP and CN were both 200fF. Two non-overlapping clocks
Figure SMS_5
Figure SMS_5
1 and->
Figure SMS_6
The 2 period is 200ns and the duty cycle is 50%. The common mode voltage VCM is equal to the arithmetic mean of Vinp and Vinn. The current flowing through the branch formed by transistors M1 and M2 is half that flowing through transistors M5 and M6, the other half flowing through the branch formed by transistors M3 and M4. When Vinp is greater than Vinn, transistor M2 gradually turns on more than transistor M1, thereby causing the output voltage Voutn to decrease. Similarly, transistor M3 gradually turns on more than transistor M4, thereby making the output voltage Voutp higher. The total average current of the comparator was 1uA and the average power was 3.3uW. />

Claims (2)

1. A low power comparator having low delay distortion characteristics from a bias circuit, characterized by: the transistor comprises 10 MOSFET transistors M1-M10, two capacitors CP and CN and six switches SW 1-SW 6, wherein M1, M3, M5, M7 and M8 are P-type MOSFETs, M2, M4, M6, M9 and M10 are N-type MOSFETs, and the specific relation of the width-to-length ratios of the transistors is as follows: m5/m7=m6/m10=2×m1/m8=2×m3/m8=2×m2/m9=2×m4/M9, and the gate length of each MOS transistor is 180nm; m5, M7, M8 gate width is 1um; m1 and M3 have a gate width of 500nm; the gate width of M6, M9 and M10 is 700nm; m2 and M4 have a gate width of 350nm; the source electrode of M5 and the source electrode of M7 are connected with a power supply VDD, the grid electrode of M5 is connected with the grid electrode of M7, and the drain electrode of M5 is connected with the source electrodes of M1 and M3; the drain electrode of M3 is connected with the drain electrode of M4 and is used as the positive output end Voutp of the comparator, and the grid electrode of M3 is connected with the grid electrode of M4; the source electrode of M4 and the source electrode of M2 are connected with the drain electrode of M6; the drain electrode of the M1 is connected with the drain electrode of the M2 and serves as a negative output end Voutn of the comparator, and the grid electrode of the M1 is connected with the grid electrode of the M2; the M6 source electrode and the M10 source electrode are connected with GND; the grid electrode of M8 is connected with the grid electrode of M9 and the grid electrodes of M5, M6, M7 and M10; the drain electrode of M8 is connected with the drain electrode of M9; the switch SW1 is bridged between the drain and the gate of M3; the switch SW2 is bridged between the drain electrode and the grid electrode of the M1; the positive input voltage Vinp of the comparator is connected to the left plate of the capacitor CP through a switch SW3, and the common mode voltage VCM of the comparator is connected to the left plate of the capacitor CP through a switch SW 4; the right plate of the capacitor CP is connected to the gate of M1; the negative input voltage Vinn of the comparator is connected to the right plate of the capacitor CN through a switch SW5, and the common-mode voltage VCM of the comparator is connected to the left plate of the capacitor CN through a switch SW 6; the left plate of the capacitor CN is connected to the gate of M3.
2. A low power comparator with low delay distortion characteristics of a self-biasing circuit as recited in claim 1, wherein: the specific working principle is as follows: transistors M1-M4 are input stages of the comparator, two transistors M5 and M6 are current limiters of the input stages of the comparator, and M7-M10 are bias stages of the comparator; the gates of transistors M5 and M6 are connected to M7 and M10 in the bias stage, so that the current flowing through M5, M6 is a specific value, which is related to the width-to-length ratio of M7-M10; the gates of transistors M8, M9 are connected to the gates of transistors M5, M6, M7, and M10, thereby forming a current mirror structure that can effectively limit the current through the input stage;
Figure QLYQS_1
1 and->
Figure QLYQS_2
2 is two non-overlapping clocks; when->
Figure QLYQS_3
When 1 is high, SW1, SW2, SW4 and SW6 are closed, and the common-mode voltage VCM is respectively collected to the left polar plate of the capacitor CP and the right polar plate of the capacitor CN; the common mode voltage of the input stage of the comparator is sampled to the right plate of the capacitor CP and the left plate of the capacitor CN by means of the closed SW1 and SW2, respectively; in the process, any offset caused by mismatch at two sides of the input stage is eliminated, so that the self-bias of the comparator is realized; when->
Figure QLYQS_4
When 2 is high, the switches SW3 and SW5 are in a closed state, and the other switches are in an open state, so that the function of the comparator is realized; when the voltages Vinp and Vinn are equal to the common mode voltage VCM, the output voltage is equal to the common mode voltage VCM; when the input voltages Vinp and Vinn are not equal to the common mode voltage VCM, the output voltage fluctuates centering on the common mode voltage VCM; two non-overlapping clocks
Figure QLYQS_5
1 and->
Figure QLYQS_6
The 2 period is 200ns and the duty cycle is 50%. />
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CN114448424B (en) * 2022-01-14 2023-05-23 电子科技大学 Low-voltage comparator with bias
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