CN110034762B - Sampling frequency adjustable analog-digital converter - Google Patents
Sampling frequency adjustable analog-digital converter Download PDFInfo
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- CN110034762B CN110034762B CN201910327093.1A CN201910327093A CN110034762B CN 110034762 B CN110034762 B CN 110034762B CN 201910327093 A CN201910327093 A CN 201910327093A CN 110034762 B CN110034762 B CN 110034762B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
- H03M1/08—Continuously compensating for, or preventing, undesired influence of physical parameters of noise
- H03M1/0845—Continuously compensating for, or preventing, undesired influence of physical parameters of noise of power supply variations, e.g. ripple
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/124—Sampling or signal conditioning arrangements specially adapted for A/D converters
- H03M1/1245—Details of sampling arrangements or methods
- H03M1/126—Multi-rate systems, i.e. adaptive to different fixed sampling rates
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Abstract
The invention discloses an analog-to-digital converter with adjustable sampling frequency, which comprises a non-overlapping clock, a bootstrap switch, an operational amplifier, an internal clock generating unit, a DAC control logic unit, an asynchronous delay logic module, a DAC capacitor array, a delay logic module, a first delay selector and a second delay selector; the invention adopts the first delay selector and the second delay selector, the first delay selector and the second delay selector both adopt three same delay times, and different asynchronous clocks are formed by selecting delay time modes, so that the adjustable sampling frequency is achieved; the invention adopts the first-stage operational amplifier and the second-stage latch as the comparator, which can prevent flyback noise and improve the comparison speed.
Description
Technical Field
The present invention relates to the field of integrated circuits, and in particular, to an analog-to-digital converter with adjustable sampling frequency.
Background
The a/D converter is an important bridge connecting the Analog system and the digital signal processing system, and is widely applied in the fields of digital signal processing technology and wireless communication, so that the demand for ADCs (Analog-to-digital converter) based on CMOS technology is increasing, especially ADCs with high speed, high precision, low power consumption and low cost. A SAR (Successive Approximation Register, successive approximation type) a/D conversion circuit is a common circuit, and the sampling frequency is fixed, and the sampling frequency cannot be adjusted.
Disclosure of Invention
The invention aims to solve the technical problem of providing an analog-to-digital converter with adjustable sampling frequency aiming at the defects of the background technology.
The invention adopts the following technical scheme for solving the technical problems:
the analog-to-digital converter with the adjustable sampling frequency comprises a delay logic module, a comparator, a successive approximation register, a DAC capacitor array, a first delay selector and a second delay selector; one end of the delay logic module is connected with the Valid signal of the comparator, and the other end of the delay logic module is connected with the input end of the second delay selector; the input end of the first delay selector is connected with the output end of the comparator, and the other end of the first delay selector is connected with the output end of the second delay selector and the input end of the successive approximation register. An analog-to-digital converter with adjustable sampling frequency according to claim 1, characterized in that: the comparator comprises a front-stage operational amplifier and a secondary latch; in the front-stage operational amplifier, the grid electrodes of M9 and M10 are connected with input signals VIP and VIN, the output ends of the front-stage operational amplifier are respectively connected to the grid electrodes of M3 and M4 in the secondary latch, and are used as the input signals of the secondary latch, and VOUTP and VOUTN are output signals of the secondary latch, and after the VOUTP and VOUTN are inverted, the output signals are subjected to NAND gate operation to obtain Valid signals.
Further: the first delay selector and the second delay selector both use 3 kinds of same delays (a designer can also use a plurality of different delays according to the needs, and the specific situation is determined according to the needs).
Further: the first delay selector and the second delay selector both comprise 3 delay units and 3 delay selector switches; the 3 delay units are mutually connected in series, one end of the delay selector switch1 is connected with the input end of the delay unit delay time1, and the other end of the delay selector switch1 is connected with the output end of the delay unit delay time 3; one end of the delay selector switch2 is connected with the input end of the delay unit delay 2, and the other end of the delay selector switch2 is connected with the output end of the delay 3; one end of the delay selector switch3 is connected with the input end of the delay unit delay 3, and the other end of the delay selector switch3 is connected with the output end of the delay 3.
Further: the delay unit consists of two inverters which are connected in series, and the input end of the second-stage inverter is connected with the output end of the first-stage inverter.
Further: the delay selector switch circuit is formed by combining input signals A and B, an inverter circuit and a NOR gate circuit, wherein A and B are external digital input signals; in switch1, the signal A is connected with the input end of an inverter, the output end of the inverter is connected with one input end of a NOR gate circuit, the signal B is connected with the input end of another inverter, and the output end of the inverter is connected with the other input end of the NOR gate circuit; in switch2, the signal A is connected with one input end of the NOR gate circuit, the signal B is connected with the input end of the inverter, and the output end of the inverter is connected with the other input end of the NOR gate circuit; in switch3, the a signal is connected to an input of an inverter, an output of which is connected to one input of a nor gate, and the B signal is connected to the other input of the nor gate. When both A and B are high, the NOR gate outputs high; in switch2, the signal A is connected with one input end of the NOR gate circuit, the signal B is connected with the input end of the inverter, the output end of the inverter is connected with the other input end of the NOR gate circuit, and when A is low level and B is high level, the NOR gate circuit outputs high level; in switch3, the a signal is connected to an input terminal of an inverter, an output terminal of the inverter is connected to an input terminal of the nor gate, the B signal is connected to another input terminal of the nor gate, and the nor gate outputs a high level when a is high and B is low.
Further: the DAC capacitor array adopts a monotonic capacitor switching process, and meanwhile, the capacitor array adopts five-five segmented capacitors.
Further: the delay logic module consists of 1 PMOS tube, 10 NMOS tube circuits connected in parallel, 1 NOT gate circuit, 1 AND gate circuit and 1 OR gate circuit, wherein the Valid signal is connected to the grid electrodes of the PMOS tubes through the NOT gate circuit, the drain electrodes of the PMOS tubes are connected with the drain electrodes of all NMOS tubes and one input end of the AND gate circuit, the C1 signal is connected to the other input end of the AND gate circuit, the output end of the AND gate circuit is connected to one input end of the OR gate circuit, the SAMPLE signal is connected with the grid electrode of one NMOS tube and is connected to the other input end of the OR gate circuit, and the S2-S10 signals are respectively connected with the grid electrodes of the other 9 NMOS tubes.
The invention also comprises a non-overlapping clock, a bootstrap switch, an internal clock generating unit, a DAC control logic unit, an asynchronous delay logic module and a DAC capacitor array, wherein the CLK input end of the non-overlapping clock is connected with a sampling signal, and the CLK_1N output end and the CLK_2N output end of the non-overlapping clock are respectively connected with the CLK_1N input end and the CLK_2N input end of the bootstrap switch; the Vin input end of the bootstrap switch is connected with an input signal, and the Vout output end of the bootstrap switch is respectively connected with the VIN input end of the comparator and the output end of the DAC capacitor array; the Vbias bias end of the comparator is connected with the bias voltage module, two output ends of the comparator are connected with two input ends of an AND gate on one hand, and are correspondingly connected with the OUTN output end and the OUTP output end of the DAC control logic unit respectively on the other hand, and the Valid output end of the comparator is connected with the Valid input end of the internal clock generation unit and the Valid input end of the asynchronous delay logic module respectively; the sampling input end of the internal clock generating unit is connected with a sampling signal, the C1 output end to the C10 output end are respectively and correspondingly connected with the C1 input end to the C10 input end of the DAC control logic unit, and meanwhile, the C1-C10 ends of the internal clock generating unit are also respectively and correspondingly connected with the C1-C10 ends of the asynchronous delay logic module; the CAP_N output end of the DAC control logic unit is connected with the input end of the corresponding DAC capacitor array, and the CNi end and the CPi end of the DAC control logic unit are respectively connected with the CNi input end and the CPi input end of the asynchronous delay logic module; the S2-S10 output end of the asynchronous delay logic module is connected with the corresponding S2-S10 input end, and the V_CLC output end of the asynchronous delay logic module is connected with the V_CLC input end of the comparator; the external reference voltage Vref is connected with the Vref input end of the DAC control logic unit.
Compared with the prior art, the technical scheme provided by the invention has the following technical effects:
1. the invention adopts the first delay selector and the second delay selector, and the first delay selector and the second delay selector both adopt three same delays, thereby realizing adjustable sampling frequency;
2. the comparator adopted by the invention comprises a front-stage operational amplifier and a second-stage latch, and can prevent flyback noise and improve the comparison speed.
Drawings
FIG. 1 is a block diagram of the overall system of the present invention;
FIG. 2 is a circuit diagram of a comparator of the present invention;
FIG. 3 is a circuit diagram of a non-overlapping clock of the present invention;
FIG. 4 is a circuit diagram of a bootstrap switch of the present invention;
FIG. 5 is a circuit diagram of an internal clock generation unit of the present invention;
FIG. 6 is a circuit diagram of DAC control logic unit of the present invention;
FIG. 7 is a circuit diagram of an asynchronous delay logic module of the present invention;
FIG. 8 is a circuit diagram of a delay selector;
fig. 9 is a circuit diagram of a delay selector switch.
Detailed Description
As shown in FIG. 1, the analog-to-digital converter with adjustable sampling frequency comprises a delay logic module, a first delay selector and a second delay selector, wherein one end of the delay logic module is connected with a Valid signal of a comparator, and the other end of the delay logic module is connected with the input end of the second delay selector; the input end of the first delay selector is connected with the output end of the comparator, and the other end of the first delay selector is connected with the output end of the second delay selector and the input end of the successive approximation register. The analog-to-digital converter with adjustable sampling frequency further comprises a non-overlapping clock, a bootstrap switch, an internal clock generating unit, a DAC control logic unit, an asynchronous delay logic module and a DAC capacitor array, wherein the CLK input end of the non-overlapping clock is connected with a sampling signal.
As shown in fig. 2, the Vbias bias terminal of the comparator is connected with a bias voltage module, two output terminals VOUTP and VOUTN of the comparator are respectively connected with an OUTN output terminal and an OUTP output terminal of the DAC control logic unit after being inverted on one hand, and a Valid output terminal of the comparator is respectively connected with a Valid input terminal of the internal clock generating unit and a Valid input terminal of the asynchronous delay logic module.
As shown in fig. 4, the CLK input terminal of the non-overlapping clock is connected to the sampling signal, and the clk_1n output terminal and the clk_2n output terminal of the non-overlapping clock are respectively connected to the clk_1n input terminal and the clk_2n input terminal of the bootstrap switch; the Vin input end of the bootstrap switch is connected with an input signal, and the Vout output end of the bootstrap switch is respectively connected with the VIN input end of the comparator and the output end of the DAC capacitor array.
As shown in fig. 5, the SAMPLE input end of the internal clock generating unit is connected with the sampling signal, the C1 output end to the C10 output end are respectively and correspondingly connected with the C1 input end to the C10 input end of the DAC control logic unit, and meanwhile, the C1-C10 ends of the internal clock generating unit are respectively and correspondingly connected with the C1-C10 ends of the asynchronous delay logic module.
As shown in fig. 6, the cap_n output end of the DAC control logic unit is connected to the input end of the corresponding DAC capacitor array, the CNi end and the CPi end of the DAC control logic unit are respectively connected to the CNi input end and the CPi input end of the asynchronous delay logic module, and the peripheral reference voltage Vref is connected to the Vref input end of the DAC control logic unit.
As shown in fig. 7, the outputs S2 to S10 of the asynchronous delay logic module are connected to the corresponding inputs S2 to S10, and the v_clc output is connected to the v_clc input of the comparator.
As shown in fig. 1, the invention adopts a monotonicity capacitance switching process, and meanwhile, the capacitance array adopts five-five segmented capacitors, so that the power consumption is reduced, the layout area is further reduced, and the measured power consumption is 0.775mW and is smaller than that of a circuit with the same structure. Compared with the traditional structure, the monotonic capacitor array has the advantages that the power consumption is only about 81%, and the power consumption is further reduced by the segmented capacitors. The monotonic capacitive switching process has the characteristics that: 1. the fully differential structure can inhibit power supply noise, and the common mode inhibition ratio is also good; 2. the input end is sampled to obtain voltage (VIP, VIN), and the voltage directly enters the first comparison without consuming energy. Assuming that VIP > VIN, valid signal is high, the internal clock signal is triggered, the highest signal bit (MSB) of the corresponding P terminal is 1, the corresponding capacitor is connected to ground, and the other terminal remains unchanged, at this time vip=vip-Vref/2; after a period of time, the comparator resets, the input enters the comparison, and this cycle is maintained until the Least Significant Bit (LSB) bit is asserted.
As shown in fig. 1, a sampling frequency-adjustable analog-to-digital converter has the following basic principle: when the sampling clock is high, the upper polar plate of the capacitor array samples the input voltages VIP and VIN through the bootstrap switch, and the lower polar plate of the capacitor is connected to the reference level. When the sampling clock becomes low level, the sampling is ended and the conversion stage is entered. The input end of the comparator compares the sampling values, and the output result is sent to the SAR logic control unit through the first delay selector to control the level of each capacitor lower pole plate of the DAC capacitor array, and is sent to the delay logic module and the second delay selector to enable the comparator to enter a reset state. It is to be appreciated that the input of the first comparator is directly compared. Assuming that VIN is greater than VIP, the first internal clock triggers, the VIN end capacitor switch is grounded, the DAC capacitor array redistributes, the voltage of the input end with large voltage decreases, the capacitor switch is grounded, vin=vin-Vref/2, VIP remains unchanged, the capacitor switch is connected with Vref, after the comparator resets, the second comparison starts, and the cycle is sequentially performed for 10 times. The structure follows "compare first, then change": the comparator compares and the capacitor array charge redistributes. The comparison means that after the sampling is finished, the comparator directly compares the two input voltages, the connection of the lower polar plate of the highest-order capacitor at one end is changed according to the comparison result, the DAC capacitor array is stabilized, the comparator performs the second comparison, the level of the next highest-order capacitor array is changed again, and the cycle is always 10 times. The circuit optimizing part adopts the basic principle of a first delay selector and a second delay selector: by selecting the types of the first delay selector (such as 300ns/600ns/900 ns) and the second delay selector (such as 300ns/600ns/900 ns), the occupation time of the high level and the low level of the asynchronous clock can be adjusted, so that the sampling frequency is further influenced, and the adjustable sampling frequency is realized.
As shown in fig. 2, the comparator adopted by the invention comprises a front-stage operational amplifier and a secondary latch, and can prevent flyback noise and improve the comparison speed; comparator circuit theory of operation: when V_CLC is high, valid is low; when v_clc is low, the M3 and M4 terminals compare the two input voltages, and since the cross coupling formed by M5 and M6 has a positive feedback effect, one of the terminals VOUTN and VOUTP becomes high, the other terminal becomes low, valid becomes high, and triggers the internal clock signal Ci. Assuming Vin > Vip, i.e. the voltage at node 3 rises faster than that at node 4, positive feedback is formed inside the circuit when the voltage at node 3 increases to turn on the M6 tube, and eventually node 3 rises to a higher level value, node 4 discharges to 0, and the entire comparison process is completed. The v_clc signal then goes high again and the comparator enters a reset phase.
As shown in fig. 3, the linearity of the sample-hold circuit can be improved by adding a non-overlapping clock to the sample-hold circuit; because the two-phase clock generated by the inverter has a larger overlapping part, the MOS tube is still conducted when the sampling switch is turned off, so that the charge stored on the capacitor is partially disappeared, the gate-source voltage of the bootstrap switch is changed, the nonlinear error of the switch is introduced, and the switch linearity of S/H is reduced. In the non-overlapping clocks, CLK can generate two paths of inverse non-overlapping clocks CLK_1N, CLK_2N, CLK_1N are clocks in phase with CLK, and CLK_2N is a non-overlapping reverse phase clock of CLK_1N, so that overlapping can be effectively avoided, and the linearity of S/H is improved.
FIG. 4 shows a bootstrap switch circuit according to the present invention, when CLK_1N is low, sampling switch M10 is turned off, M1, M3, M4, M8, M9 are turned on, the rest of the tubes are turned off, the voltage of node 1 is charged to VDD, the voltage of node 2 is charged to ground, node 3 is charged to VDD, node 4 is discharged to ground, and the capacitive charge is VDD C; when CLK_1N is high, sampling switch M10 is turned on, M7, M5, M6 are turned on, the gate terminal voltage of the sampling tube is equal to VDD+vin, and Vout is equal to Vin.
Fig. 5 shows an internal clock generating unit circuit used in the present invention, and the basic operation principle of the circuit is: when the SAMPLE signal is high, the data conversion system is in the sampling phase, the internal clocks C1-C10 are all low, and the Valid signal is also low. When the SAMPLE signal is low level, the system enters a conversion stage, the comparator starts to work, when the output level values are different, the Valid signal becomes high level, the D trigger selects rising edge triggering, and the rising edge of the Valid signal triggers the D trigger array, so that C1 becomes high level. The V_CLC signal enables the comparator to reset, the VOUTN and the VOUTP are both changed into low level, the Valid is changed from high level to low level, after a period of delay, the V_CLC signal is changed into low level, the comparator starts to work again, when the output of the comparator is different in level, the Valid signal is changed from low level to high level, the rising edge triggers the D trigger array, the C2 is changed into high level, the circuit sequentially works, and finally the C10 is also changed into high level. Since the sampling signal is connected to the SET terminal of the D flip-flop, when the system enters the next sampling stage, i.e. the SAMPLE signal is again high, the internal clocks C1-C10 of the circuit are all reset to low.
As shown in fig. 6, the DAC control logic unit operates on the principle: the internal clock signal Ci is delayed by a time before being input to the and gate in order to ensure that the clock Ci again turns on the two-input and gate after the OUTN (OUTP) has completely stabilized. Assuming that Ci has been transferred to the and gate at the beginning of the change of OUTN (OUTP), OUTN (OUTP) changes from high to low, since the value of OUTN (OUTP) at the beginning of the change is higher, the capacitive driving signal voltage will rise from low, but will eventually still settle at low, i.e. the capacitive driving signal voltage will contain a sharp pulse signal that will lengthen the settling time of the DAC, thereby reducing the overall system slew rate.
As shown in fig. 7, in order to overcome the defect that the synchronous clock control circuit needs an internal clock n+1 (or n+2) times as a circuit main clock, the invention adopts a novel asynchronous delay logic module, the asynchronous clock can be generated through the internal logic circuit, and the asynchronous delay logic module adopted by the invention can normally generate as long as the delay time of the delay circuit is ensured to be longer than the charge and discharge time of a corresponding capacitor array; the working principle of the asynchronous delay logic module is as follows: in the sampling stage, valid signal is low level, in the conversion stage, valid is high in the first comparison, internal clock sequence C1 becomes high, C1 triggers DAC control logic unit, CAPRIve_ni (pi) has one end signal to become high, capacitor array redistributes, asynchronous delay logic module S2 becomes high, asynchronous signal V_CLC becomes low, comparator resets, in the second comparison, valid signal becomes high, C2 is low, point A is connected with VDD and GND, point A can be regarded as low at this time, C2 becomes high, S2 becomes low, V_CLC becomes low, and 10 times of circulation are performed in turn. The asynchronous delay logic module starts to work after the capacitor is charged and discharged, and the ADC can work normally as long as the delay time of the delay circuit is ensured to be longer than the charge and discharge time of the corresponding capacitor array.
The asynchronous delay logic module generates an asynchronous control signal according to the internal time sequence. After the sampling is finished, the system enters a conversion stage, the SAMPLE signal changes to a low level, at the moment, A, B is all low level, V_CLC changes from a high level to a low level, the comparator starts to compare the level values of the differential input ends, and when the output levels at the two ends of the comparator differ by a large voltage value, the Valid signal changes from the low level to the high level. The level of the Valid signal changes from low to high, on one hand, C1 of the internal clock generation unit is triggered to change from low level to high level, and the rising edge of C1 triggers corresponding capacitors in the DAC control logic unit to charge and discharge; on the other hand, the Valid signal at high level causes the power supply to charge node A, which will be charged to V due to the absence of other discharge paths DD When C1 changes to high level, node B changes from low level to high level, i.e. V_CLC signal changes from low level to high level. The V_CLC signal with high level value resets the comparator, the two ends output low level, the Valid signal becomes low level, namely the nodes A and V are turned off DD Is provided. When the capacitor driving signals capdrive_n1 and capdrive_p1 are different, i.e. one end of the capacitor driving signal is changed from low level to high level, the corresponding capacitor starts to discharge to ground, and the different capacitor driving signals change S2 from low level to high level, and node A is changed from V DD Discharging to ground, the V_CLC signal changes from high level to low level by a certain delay, and the comparator enters a comparison state. After the comparator finishes comparison, the Valid signal is changed from low level to high level by the different level values output from the two ends. On the one hand, after a certain time delay, the rising edge of the Valid signal triggers the internal clock to generate a singleA cell that changes C2 from low to high; on the other hand, since the Valid signal goes high, the conductive path is formed between the nodes a to VDD, but at this time S2 remains high, i.e., the conductive path between the node a and ground, and the size of the P-pipe is the same as that of the N-pipe in the asynchronous delay logic cell, it is known that the level value of the node a is small although it has both the path to VDD and the path to ground, and the level value is regarded as low. When the C2 level value changes to the high level, the level value of S2 changes from the high level to the low level, and the node a has only a conductive path to VDD at this time. After a delay, V_CLC becomes high level, the comparator is reset, the same two low level values are output, the Valid signal becomes low level again, and the paths of the nodes A and VDD are cut off. When C2 causes one of the capacitor driving signals Capdrive_n2 and Capdrive_p2 to become high, i.e. a certain capacitor starts to discharge to ground, S3 also becomes high, node A is defined by level value V DD After a delay, the V_CLC signal level becomes low, and the comparator enters the comparison stage again. The cycle was repeated 10 times in sequence.
Fig. 8 is a first delay selector and a second delay selector circuit, the circuit comprising 3 delay cells, each delay cell being capable of delaying 300ns. When switch1 is closed, switch2 and switch3 are disconnected, and at the moment, point A and point B are directly conducted without delay; when switch2 is closed, switch1 and switch3 are disconnected, a delay unit is connected into the circuit, and the delay is 300ns; when switch3 is closed, switch1 and switch2 are disconnected, two delay units connected in series are connected in the circuit, and the delay time is 600ns; when switch1, switch2 and switch3 are all disconnected, three delay units connected in series are connected into the circuit, and the delay is 900ns;
FIG. 9 shows delay selector switch circuits, each of which can be seen as a combination of an input logic block and a NOR gate logic block, with switch1 on and switch2 and switch3 off when A and B are both high; when A is low level and B is high level, switch2 is turned on, and switch1 and switch3 are turned off; when A is high level and B is low level, switch3 is turned on, and switch1 and switch2 are turned off; the control of the delay selection circuit is realized by the control mode.
It will be understood by those skilled in the art that, unless otherwise defined, all terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the prior art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
The above embodiments are only for illustrating the technical idea of the present invention, and the protection scope of the present invention is not limited thereto, and any modification made on the basis of the technical scheme according to the technical idea of the present invention falls within the protection scope of the present invention. The embodiments of the present invention have been described in detail with reference to the drawings, but the present invention is not limited to the above embodiments, and various changes can be made without departing from the spirit of the present invention within the knowledge of one of ordinary skill in the art.
Claims (1)
1. The utility model provides an adjustable analog-to-digital converter of sampling frequency, includes delay logic module, comparator, successive approximation register, DAC electric capacity array, its characterized in that: the system also comprises a first delay selector and a second delay selector; one end of the delay logic module is connected with the Valid signal of the comparator, and the other end of the delay logic module is connected with the input end of the second delay selector; the input end of the first delay selector is connected with the output end of the comparator, and the other end of the first delay selector is connected with the output end of the second delay selector and the input end of the successive approximation register;
the comparator comprises a front-stage operational amplifier and a secondary latch; in the front-stage operational amplifier, the grid electrodes of M9 and M10 are connected with input signals VIP and VIN, the output ends of the front-stage operational amplifier are respectively connected with the grid electrodes of M3 and M4 in the secondary latch, and are used as the input signals of the secondary latch, and VOUTP and VOUTN are output signals of the secondary latch, and after the VOUTP and VOUTN are inverted, the output signals are subjected to NAND gate operation to obtain Valid signals;
the first delay selector and the second delay selector adopt 3 same delays;
the first delay selector and the second delay selector both comprise 3 delay units and 3 delay selector switches, and the 3 delay units are respectively: the delay 1, delay 2, delay 3,3 delay selector switches are respectively: switch1, switch2, switch3; the 3 delay units are mutually connected in series, one end of the switch1 is connected with the input end of the delay 1, and the other end of the switch1 is connected with the output end of the delay 3; one end of the switch2 is connected with the input end of the delay 2, and the other end of the switch2 is connected with the output end of the delay 3; one end of the switch3 is connected with the input end of the delay 3, and the other end of the switch3 is connected with the output end of the delay 3;
the delay unit consists of two inverters which are connected in series, and the input end of the second-stage inverter is connected with the output end of the first-stage inverter; the delay selector switch circuit is formed by combining input signals A and B, an inverter circuit and a NOR gate circuit, wherein A and B are external digital input signals; in switch1, the signal A is connected with the input end of an inverter, the output end of the inverter is connected with one input end of a NOR gate circuit, the signal B is connected with the input end of another inverter, and the output end of the inverter is connected with the other input end of the NOR gate circuit; in switch2, the signal A is connected with one input end of the NOR gate circuit, the signal B is connected with the input end of the inverter, and the output end of the inverter is connected with the other input end of the NOR gate circuit; in switch3, the signal A is connected with the input end of an inverter, the output end of the inverter is connected with one input end of a NOR gate circuit, and the signal B is connected with the other input end of the NOR gate circuit;
the DAC capacitor array adopts a monotonic capacitor switching process, and meanwhile, the capacitor array adopts five-five segmented capacitors.
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| CN110632842B (en) * | 2019-09-25 | 2020-12-04 | 中国电子科技集团公司第二十四研究所 | Vernier-structured ADC (analog to digital converter) based on time and linear controlled delay unit |
| CN111162785B (en) * | 2020-01-15 | 2023-04-07 | 广东药科大学 | Time division multiplexing sampling circuit and method for analog-digital converter |
| CN112929026B (en) * | 2021-01-18 | 2022-06-03 | 电子科技大学 | SARADC based on variable comparator delay loop |
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