CN209787154U - Analog-digital converter with adjustable sampling frequency - Google Patents
Analog-digital converter with adjustable sampling frequency Download PDFInfo
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- CN209787154U CN209787154U CN201920561078.9U CN201920561078U CN209787154U CN 209787154 U CN209787154 U CN 209787154U CN 201920561078 U CN201920561078 U CN 201920561078U CN 209787154 U CN209787154 U CN 209787154U
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Abstract
the utility model discloses an analog-digital converter with adjustable sampling frequency, which comprises a non-overlapping clock, a bootstrap switch, an operational amplifier, an internal clock generating unit, a DAC control logic unit, an asynchronous delay logic module, a DAC capacitor array, a delay logic module, a first delay selector and a second delay selector; the utility model adopts the first delay selector and the second delay selector, the first delay selector and the second delay selector adopt three kinds of same delay time, and different asynchronous clocks are formed by selecting a delay time mode, thereby achieving adjustable sampling frequency; the utility model discloses in adopt one-level fortune to put and latch as the comparator with the second grade, can prevent the flyback noise, improve comparison speed.
Description
Technical Field
the invention relates to the technical field of integrated circuits, in particular to an analog-to-digital converter with adjustable sampling frequency.
Background
The a/D converter is an important bridge for connecting an Analog system and a digital signal processing system, and is widely applied in the fields of digital signal processing technology and wireless communication, so that the demand for an Analog-to-digital converter (ADC) based on a CMOS process is increasing, especially for an ADC with high speed, high precision, low power consumption and low cost. An SAR (Successive Approximation Register) a/D conversion circuit is a commonly used circuit, and the sampling frequency is fixed and cannot be adjusted.
disclosure of Invention
The invention provides an analog-to-digital converter with adjustable sampling frequency, aiming at the defects of the background technology.
The invention adopts the following technical scheme for solving the technical problems:
An analog-to-digital converter with adjustable sampling frequency comprises a delay logic module, a comparator, a successive approximation register, a DAC capacitor array, a first delay selector and a second delay selector; one end of the delay logic module is connected with a Valid signal of the comparator, and the other end of the delay logic module is connected with the input end of the second delay selector; the input end of the first delay selector is connected with the output end of the comparator, and the other end of the first delay selector is connected with the output end of the second delay selector and the input end of the successive approximation register.
Further: the comparator comprises a preceding stage operational amplifier and a second stage latch; in the preceding operational amplifier, gates of M9 and M10 are connected with input signals VIP and VIN, an output end of the preceding operational amplifier is respectively connected with gates of M3 and M4 in the secondary latch to serve as input signals of the secondary latch, VOUTP and VOUTN are output signals of the secondary latch, and after the VOUTP and VOUTN are inverted, operation is performed through a NAND gate circuit to obtain a Valid signal.
Further: the first delay selector and the second delay selector both use 3 identical delays (a designer can also use a plurality of different delays according to requirements, and the specific situation depends on the requirements).
Further: the first delay selector and the second delay selector both comprise 3 delay units and 3 delay selector switches; the 3 delay units are connected in series, one end of a delay selector switch1 is connected with the input end of the delay unit delaytime1, and the other end of the delay selector switch1 is connected with the output end of the delay unit delaytime 3; one end of the delay selector switch2 is connected with the input end of the delay unit delaytime2, and the other end of the delay selector switch2 is connected with the output end of the delaytime 3; one end of the delay selector switch3 is connected to the input end of the delay unit delaytime3, and the other end of the delay selector switch3 is connected to the output end of the delay unit delaytime 3.
Further: the delay unit is composed of two phase inverters which are connected in series, and the input end of the second-stage phase inverter is connected with the output end of the first-stage phase inverter.
Further: the delay selector switch circuit is formed by combining input signals A and B, an inverter circuit and a NOR gate circuit, wherein A and B are external digital input signals; in the delay selector switch1, the signal A is connected with the input end of an inverter, the output end of the inverter is connected with one input end of a NOR gate circuit, the signal B is connected with the input end of another inverter, and the output end of the inverter is connected with the other input end of the NOR gate circuit; in the delay selector switch2, the signal A is connected with one input end of an NOR gate circuit, the signal B is connected with the input end of an inverter, and the output end of the inverter is connected with the other input end of the NOR gate circuit; in the delay selector switch3, the a signal is connected to an input terminal of an inverter, an output terminal of the inverter is connected to one input terminal of a nor gate, and the B signal is connected to the other input terminal of the nor gate. When A and B are both high level, the NOR gate circuit outputs high level; in the delay selector switch2, a signal a is connected to one input end of a nor gate circuit, a signal B is connected to an input end of an inverter, an output end of the inverter is connected to the other input end of the nor gate circuit, and when a is low level and B is high level, the nor gate circuit outputs high level; in the delay selector switch3, the a signal is connected to an input terminal of an inverter, an output terminal of the inverter is connected to one input terminal of a nor gate, the B signal is connected to the other input terminal of the nor gate, and the nor gate outputs a high level when a is a high level and B is a low level.
further: the DAC capacitor array adopts a monotonicity capacitor switching process, and meanwhile, the capacitor array adopts a five-fifth segment capacitor.
further: the delay logic module comprises 1 PMOS tube, 10 NMOS tube circuits connected in parallel, 1 NOT gate circuit, 1 AND gate circuit and 1 OR gate circuit, a Valid signal is connected to the grid electrode of the PMOS tube through the NOT gate circuit, the drain electrodes of the PMOS tube are connected with the drain electrodes of all the NMOS tubes and one input end of the AND gate circuit, a C1 signal is connected to the other input end of the AND gate circuit, the output end of the AND gate circuit is connected to one input end of the OR gate circuit, a SAMPLE signal is connected with the grid electrode of one NMOS tube and is connected to the other input end of the OR gate circuit, and S2-S10 signals are respectively connected with the grid electrodes of the rest 9 NMOS tubes.
The invention also comprises a non-overlapping clock, a bootstrap switch, an internal clock generation unit, a DAC control logic unit, an asynchronous delay logic module and a DAC capacitor array, wherein the CLK input end of the non-overlapping clock is connected with the sampling signal, and the CLK _1N output end and the CLK _2N output end of the non-overlapping clock are respectively connected with the CLK _1N input end and the CLK _2N input end of the bootstrap switch; the Vin input end of the bootstrap switch is connected with an input signal, and the Vout output end of the bootstrap switch is respectively connected with the VIN input end of the comparator and the output end of the DAC capacitor array; the Vbias bias end of the comparator is connected with the bias voltage module, two output ends of the comparator are connected with two input ends of an AND gate on one hand, and are correspondingly connected with an OUTN output end and an OUTP output end of the DAC control logic unit on the other hand, and a Valid output end of the comparator is respectively connected with a Valid input end of the internal clock generation unit and a Valid input end of the asynchronous delay logic module; the SAMPLE input end of the internal clock generation unit is connected with a sampling signal, the output end of C1 to the output end of C10 are correspondingly connected with the input end of C1 to the input end of C10 of the DAC control logic unit respectively, and meanwhile, the ends C1 to C10 of the internal clock generation unit are correspondingly connected with the ends C1 to C10 of the asynchronous delay logic module respectively; the CAP _ N output end of the DAC control logic unit is connected with the input end of the corresponding DAC capacitor array, and the CNi end and the CPi end of the DAC control logic unit are respectively connected with the CNi input end and the CPi input end of the asynchronous delay logic module; the output ends of S2 to S10 of the asynchronous delay logic module are connected with the corresponding input ends of S2 to S10, and the V _ CLC output end of the asynchronous delay logic module is connected with the V _ CLC input end of the comparator; and the external reference voltage Vref is connected with the Vref input end of the DAC control logic unit.
compared with the prior art, the invention adopting the technical scheme has the following technical effects:
1. The sampling frequency is adjustable by adopting the first delay selector and the second delay selector which both adopt three identical delays;
2. The comparator adopted by the invention comprises the preceding-stage operational amplifier and the second-stage latch, so that the flyback noise can be prevented, and the comparison speed can be improved.
Drawings
FIG. 1 is a block diagram of the overall system of the present invention;
FIG. 2 is a circuit diagram of the comparator of the present invention;
FIG. 3 is a circuit diagram of a non-overlapping clock of the present invention;
FIG. 4 is a circuit diagram of the bootstrap switch of the present invention;
FIG. 5 is a circuit diagram of an internal clock generation unit of the present invention;
FIG. 6 is a circuit diagram of a DAC control logic unit of the present invention;
FIG. 7 is a circuit diagram of an asynchronous delay logic module of the present invention;
FIG. 8 is a circuit diagram of a delay selector;
Fig. 9 is a circuit diagram of the delay selector switch.
Detailed Description
As shown in fig. 1, an analog-to-digital converter with adjustable sampling frequency includes a delay logic module, a first delay selector and a second delay selector, wherein one end of the delay logic module is connected to a Valid signal of a comparator, and the other end of the delay logic module is connected to an input end of the second delay selector; the input end of the first delay selector is connected with the output end of the comparator, and the other end of the first delay selector is connected with the output end of the second delay selector and the input end of the successive approximation register. The analog-digital converter with the adjustable sampling frequency further comprises a non-overlapping clock, a bootstrap switch, an internal clock generation unit, a DAC control logic unit, an asynchronous delay logic module and a DAC capacitor array, wherein the CLK input end of the non-overlapping clock is connected with a sampling signal.
as shown in fig. 2, the Vbias offset of the comparator is connected to the offset voltage module, two output terminals VOUTP and VOUTN of the comparator are inverted on the one hand and used as two input terminals of the and gate, on the other hand, are respectively connected to the OUTN output terminal and the OUTP output terminal of the DAC control logic unit, and the Valid output terminal of the comparator is respectively connected to the Valid input terminal of the internal clock generation unit and the Valid input terminal of the asynchronous delay logic module.
As shown in fig. 4, the CLK input terminal of the non-overlap clock is connected to the sampling signal, and the CLK _1N output terminal and the CLK _2N output terminal of the non-overlap clock are respectively connected to the CLK _1N input terminal and the CLK _2N input terminal of the bootstrap switch; and a Vin input end of the bootstrap switch is connected with an input signal, and a Vout output end of the bootstrap switch is respectively connected with a VIN input end of the comparator and an output end of the DAC capacitor array.
As shown in fig. 5, the SAMPLE input terminal of the internal clock generation unit is connected to the sampling signal, the output terminal of C1 to the output terminal of C10 are respectively connected to the input terminals of C1 to C10 of the DAC control logic unit, and the terminals C1 to C10 of the internal clock generation unit are also respectively connected to the terminals C1 to C10 of the asynchronous delay logic module.
As shown in fig. 6, the CAP _ N output end of the DAC control logic unit is connected to the input end of the corresponding DAC capacitor array, the CNi end and the CPi end of the DAC control logic unit are respectively connected to the CNi input end and the CPi input end of the asynchronous delay logic module, and the external reference voltage Vref is connected to the Vref input end of the DAC control logic unit.
As shown in FIG. 7, the outputs S2-S10 of the asynchronous delay logic block are coupled to the corresponding inputs S2-S10, and the V _ CLC output is coupled to the V _ CLC input of the comparator.
As shown in FIG. 1, the invention adopts a monotonicity capacitance switching process, and the capacitance array adopts a five-fifth segment capacitance, so that the power consumption is reduced, the layout area is further reduced, and the measured power consumption is 0.775mW which is less than the power consumption of a circuit with the same structure. Compared with the traditional structure, the power consumption of the monotonicity capacitor array is only about 81%, and the sectional capacitor further reduces the power consumption. The monotonicity capacitance switching process has the characteristics that: 1. the fully differential structure can suppress power supply noise, and the common mode rejection ratio is also good; 2. the input end obtains the voltage (VIP, VIN) after sampling, and the voltage directly enters the first comparison without consuming energy. Assuming that VIP is greater than VIN, the Valid signal is high, an internal clock signal is triggered, the highest signal bit (MSB) corresponding to the P end is 1, the corresponding capacitor is connected to the ground, and the other end is kept unchanged, wherein VIP is VIP-Vref/2; over time, the comparator resets and the input enters the comparison, holding this cycle until the Least Significant Bit (LSB) bit is asserted.
As shown in fig. 1, the basic principle of an analog-to-digital converter with adjustable sampling frequency is as follows: when the sampling clock is high, the upper electrode plate of the capacitor array samples input voltages VIP and VIN through the bootstrap switch, and the lower electrode plate of the capacitor is connected to a reference level. When the sampling clock changes to low level, the sampling is finished and the conversion stage is entered. The input end of the comparator compares the sampling values, and the output result is sent to the SAR logic control unit through the first delay selector to control the level of each capacitor lower plate of the DAC capacitor array on one hand, and is sent to the delay logic module and the second delay selector on the other hand, so that the comparator enters a reset state. It is to be understood that the inputs of the first comparator are compared directly. And if VIN is larger than VIP, triggering by the first internal clock, grounding a VIN-end capacitance switch, redistributing a DAC capacitance array, reducing the voltage of the input end with large voltage, grounding the capacitance switch, keeping VIN-Vref/2, keeping VIP unchanged, connecting the capacitance switch with Vref, resetting the comparator, starting the second comparison, and sequentially circulating for 10 times. The structure follows "compare first, then change": the comparator compares and the capacitor array charge is redistributed. The first comparison means that after sampling is finished, the comparator directly compares two input voltages, the connection of the lower electrode plate of the highest-order capacitor at one end is changed according to a comparison result, when the DAC capacitor array is stabilized, the comparator carries out second comparison, the level of the second highest-order capacitor array is changed again, and the cycle is carried out for 10 times all the time. The circuit optimization part adopts the basic principle of a first delay selector and a second delay selector: by selecting the type of the first delay selector (such as 300ns/600ns/900ns) and the type of the second delay selector (such as 300ns/600ns/900ns), the occupation time of high and low levels of the asynchronous clock can be adjusted, so that the sampling frequency is further influenced, and the adjustable sampling frequency is realized.
As shown in fig. 2, the comparator used in the present invention includes a pre-stage operational amplifier and a secondary latch, which can prevent the flyback noise and increase the comparison speed; the working principle of the comparator circuit is as follows: when V _ CLC is high, Valid is low; when V _ CLC is low, M3 and M4 terminals compare two input voltages, and because the cross coupling formed by M5 and M6 has a positive feedback effect, one end of VOUTN and VOUTP is high, the other end is low, Valid is high, and the internal clock signal Ci is triggered. Assuming that Vin > Vip, i.e. the voltage at node 3 rises faster than that at node 4, when the voltage at node 3 increases to turn on the M6 transistor, a positive feedback is formed inside the circuit, and finally node 3 rises to a higher level, node 4 discharges to 0, and the whole comparison process is completed. The V _ CLC signal then goes high again and the comparator enters a reset phase.
as shown in FIG. 3, the non-overlap clock is added to the sample-and-hold circuit to improve the linearity of the sample-and-hold circuit; the two-phase clock generated by the phase inverter has a larger overlapping part, so that the MOS tube is still conducted when the sampling switch is turned off, and the charges stored on the capacitor partially disappear, thereby changing the gate-source voltage of the bootstrap switch, introducing the nonlinear error of the switch and reducing the switch linearity of S/H. In the non-overlapped clock, the CLK can generate two reverse non-overlapped clocks CLK _1N, CLK _2N, wherein CLK _1N is the clock in phase with the CLK, and CLK _2N is the non-overlapped reverse clock of CLK _1N, thus effectively avoiding overlapping and improving the linearity of S/H.
fig. 4 is a bootstrap switch circuit adopted in the present invention, when CLK _1N is at low level, the sampling switch M10 is turned off, M1, M3, M4, M8, and M9 are turned on, the rest of the transistors are turned off, the voltage at the node 1 is charged to VDD, the voltage at the node 2 is charged to ground, the node 3 is charged to VDD, and the node 4 is discharged to ground, where the capacitance charge amount is VDD × C; when CLK _1N is high, the sampling switch M10 is turned on, M7, M5 and M6 are turned on, the gate voltage of the sampling tube is equal to VDD + Vin, and Vout is equal to Vin.
Fig. 5 is a circuit of an internal clock generating unit used in the present invention, and the basic operation principle of the circuit is as follows: when the SAMPLE signal is high, the data conversion system is in the sampling phase, the internal clocks C1-C10 are all low, and the Valid signal is also low. When the SAMPLE signal is at a low level, the system enters a conversion stage, the comparator starts to work, when the output level values are different, the Valid signal changes to a high level, the D flip-flop selects rising edge triggering, and the rising edge of the Valid signal triggers the D flip-flop array, so that C1 changes to a high level. The V _ CLC signal resets the comparator, VOUTN and VOUTP are changed into low level, so that Valid is changed from high level to low level, after a period of delay, the V _ CLC signal is changed into low level, the comparator starts to work again, when different levels are output, the Valid signal is changed from low level to high level, the rising edge triggers the D flip-flop array, so that C2 is changed into high level, the circuit works in sequence, and finally C10 is also changed into high level. Since the sampling signal is connected to the SET terminal of the D flip-flop, the circuit internal clocks C1-C10 are all reset to low when the system enters the next sampling phase, i.e., the SAMPLE signal is high again.
as shown in fig. 6, the DAC control logic unit works according to the following principle: a time delay is passed before the internal clock signal Ci is input to the and gate, which is to ensure that the clock Ci opens the two-input and gate again after outn (outp) is completely stable. Assuming that Ci is transmitted to the and gate when outn (outp) just starts to change, outn (outp) changes from high level to low level, because the level value of outn (outp) is higher at the beginning of the change, the capacitor driving signal voltage will rise from low level, but will still stabilize at low level finally, i.e. the capacitor driving signal voltage will include a sharp pulse signal, and the pulse peak will prolong the settling time of DAC, thereby reducing the switching speed of the whole system.
As shown in fig. 7, in order to overcome the defect that the synchronous clock control circuit needs N +1 (or N +2) times of internal clock as the circuit main clock, the asynchronous delay control circuit adopts a new asynchronous delay logic module, and the asynchronous clock can be generated through the internal logic circuit; the working principle of the asynchronous delay logic module is as follows: in the sampling stage, the Valid signal is low, in the conversion stage, during the first comparison, the Valid signal is high, the internal clock sequence C1 goes high, C1 triggers the DAC control logic unit, CAPDrive _ ni (pi) has a signal at one end going high, the capacitor array redistributes, the asynchronous delay logic module S2 goes high, the asynchronous signal V _ CLC goes low, the comparator resets, during the second comparison, the Valid signal goes high, when C2 is low, the point a is connected to VDD and GND, the point a can be regarded as low, C2 goes high, S2 goes low, V _ CLC goes low, and the cycle is sequentially performed for 10 times. The asynchronous delay logic module starts to work after the capacitor is charged and discharged, and the ADC can work normally as long as the delay time of the delay circuit is ensured to be longer than the charging and discharging time of the corresponding capacitor array.
The asynchronous delay logic module generates an asynchronous control signal according to the internal timing sequence. After sampling is finished, the system enters a conversion stage, the SAMPLE signal is changed into a low level, A, B is the low level at the moment, V _ CLC is changed from a high level to a low level, the comparator starts to compare level values of the differential input end, and when the output levels at two ends of the comparator are different by a large voltage value, the Valid signal is changed from the low level to the high level. On one hand, C1 triggering the internal clock generation unit changes from low level to high level, and the rising edge of C1 triggers corresponding capacitors in the DAC control logic unit to charge and discharge; another one isOn the other hand, the high level Valid signal causes the power supply to charge the node A, and the node A is charged to V due to the absence of other discharge pathsDDWhen waiting until C1 goes high, node B goes from low to high, i.e., the V _ CLC signal goes from low to high. The high value V _ CLC signal resets the comparator, the two ends output low level, the Valid signal changes into low level, namely, the nodes A and V are turned offDDthe passage of (2). When the capacitance driving signal CapDrive _ n1 is different from CapDrive _ p1, i.e. one end of the capacitance driving signal changes from low level to high level, the corresponding capacitance starts to discharge to ground, and the different capacitance driving signals make S2 change from low level to high level, and the node A changes from V to high levelDDDischarging to the ground, and changing the V _ CLC signal from high level to low level through a certain delay, the comparator enters a comparison state. After the comparator completes comparison, the Valid signal is changed from low level to high level again due to different level values output by the two ends. On one hand, after a certain time delay, the rising edge of the Valid signal triggers the internal clock generation unit, so that the C2 changes from low level to high level; on the other hand, since the Valid signal goes high, a conductive path is formed between the node a and VDD, but S2 is still high at this time, that is, there is still a conductive path between the node a and ground, and the size of the P-transistor in the asynchronous delay logic unit is the same as that of the N-transistor, it can be seen that the level value is still small and can be regarded as a low level value although the node a has both a path to VDD and a path to ground at this time. When the level of C2 changes to high, the level of S2 changes from high to low, and node A has only a conduction path to VDD. After a time delay, V _ CLC goes high, the comparator resets, outputs the same two low values, the Valid signal goes low again, and the path between node a and VDD is cut off. When the capacitor driving signal CapDrive _ n2 or CapDrive _ p2 is changed to high level by C2, i.e. a certain bit of capacitor starts to discharge to ground, S3 is also changed to high level, and the node a is changed from the level value VDDAfter a time delay, the level of the V _ CLC signal changes to low level, and the comparator enters the comparison stage again. The cycle was repeated 10 times in sequence.
Fig. 8 shows a first delay selector circuit and a second delay selector circuit, which comprise 3 delay units, each of which can delay 300 ns. When the delay selector switch1 is turned off, the delay selector switch2 and the delay selector switch3 are turned off, and the point a and the point B are directly turned on without delay; when the delay selector switch2 is turned off, the delay selector switch1 and the delay selector switch3 are disconnected, and a delay unit is connected into the circuit for delaying for 300 ns; when the delay selector switch3 is turned off, the delay selector switch1 and the delay selector switch2 are disconnected, two delay units connected in series are connected into the circuit, and the delay is 600 ns; when the delay selector switch1, the delay selector switch2 and the delay selector switch3 are all disconnected, three delay units connected in series are connected into the circuit, and the delay is 900 ns;
Fig. 9 is a delay selector switch circuit, each of which can be regarded as a combination of an input logic block and a nor gate logic block, and when both a and B are at high level, the delay selector switch1 is turned on, and the delay selector switch2 and the delay selector switch3 are turned off; when a is a low level and B is a high level, the delay selector switch2 is turned on, and the delay selector switch1 and the delay selector switch3 are turned off; when a is high level and B is low level, the delay selector switch3 is turned on, and the delay selector switch1 and the delay selector switch2 are turned off; the control of the delay selection circuit is realized through the control mode.
It will be understood by those skilled in the art that, unless otherwise defined, all terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the prior art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
the above embodiments are only for illustrating the technical idea of the present invention, and the protection scope of the present invention is not limited thereby, and any modifications made on the basis of the technical scheme according to the technical idea of the present invention fall within the protection scope of the present invention. The embodiments of the present invention have been described in detail with reference to the drawings, but the present invention is not limited to the above embodiments, and various changes can be made within the knowledge of those skilled in the art without departing from the gist of the present invention.
Claims (7)
1. An analog-to-digital converter with adjustable sampling frequency comprises a delay logic module, a comparator, a successive approximation register and a DAC capacitor array, and is characterized in that: the system also comprises a first delay selector and a second delay selector; one end of the delay logic module is connected with a Valid signal of the comparator, and the other end of the delay logic module is connected with the input end of the second delay selector; the input end of the first delay selector is connected with the output end of the comparator, and the other end of the first delay selector is connected with the output end of the second delay selector and the input end of the successive approximation register.
2. The analog-to-digital converter with adjustable sampling frequency of claim 1, wherein: the comparator comprises a preceding stage operational amplifier and a second stage latch; in the preceding operational amplifier, gates of M9 and M10 are connected with input signals VIP and VIN, an output end of the preceding operational amplifier is respectively connected with gates of M3 and M4 in the secondary latch to serve as input signals of the secondary latch, VOUTP and VOUTN are output signals of the secondary latch, and after the VOUTP and VOUTN are inverted, operation is performed through a NAND gate circuit to obtain a Valid signal.
3. The analog-to-digital converter with adjustable sampling frequency of claim 1, wherein: the first delay selector and the second delay selector adopt 3 identical delays.
4. A sampling frequency adjustable analog-to-digital converter according to claim 3, characterized in that: the first delay selector and the second delay selector both comprise 3 delay units and 3 delay selector switches, and the 3 delay units are respectively: the delay unit delaytime1, the delay unit delaytime2, the delay unit delaytime3, and the 3 delay selector switches are respectively: a delay selector switch1, a delay selector switch2 and a delay selector switch 3; the 3 delay units are connected in series, one end of a delay selector switch1 is connected with the input end of the delay unit delaytime1, and the other end of the delay selector switch1 is connected with the output end of the delay unit delaytime 3; one end of the delay selector switch2 is connected with the input end of the delay unit delaytime2, and the other end of the delay selector switch2 is connected with the output end of the delay unit delaytime 3; one end of the delay selector switch3 is connected to the input end of the delay unit delaytime3, and the other end of the delay selector switch3 is connected to the output end of the delay unit delaytime 3.
5. The analog-to-digital converter with adjustable sampling frequency of claim 4, wherein: the delay unit is composed of two phase inverters which are connected in series, and the input end of the second-stage phase inverter is connected with the output end of the first-stage phase inverter.
6. The analog-to-digital converter with adjustable sampling frequency of claim 4, wherein: the delay selector switch circuit is formed by combining input signals A and B, an inverter circuit and a NOR gate circuit, wherein A and B are external digital input signals; in the delay selector switch1, the signal A is connected with the input end of an inverter, the output end of the inverter is connected with one input end of a NOR gate circuit, the signal B is connected with the input end of another inverter, and the output end of the inverter is connected with the other input end of the NOR gate circuit; in the delay selector switch2, the signal A is connected with one input end of an NOR gate circuit, the signal B is connected with the input end of an inverter, and the output end of the inverter is connected with the other input end of the NOR gate circuit; in the delay selector switch3, the a signal is connected to an input terminal of an inverter, an output terminal of the inverter is connected to one input terminal of a nor gate, and the B signal is connected to the other input terminal of the nor gate.
7. The analog-to-digital converter with adjustable sampling frequency of claim 1, wherein: the DAC capacitor array adopts a monotonicity capacitor switching process, and meanwhile, the capacitor array adopts a five-fifth segment capacitor.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN110034762A (en) * | 2019-04-23 | 2019-07-19 | 南京邮电大学 | A kind of adjustable analog-digital converter of sample frequency |
| CN112929026A (en) * | 2021-01-18 | 2021-06-08 | 电子科技大学 | SARADC based on variable comparator delay loop |
| CN114884508A (en) * | 2022-05-27 | 2022-08-09 | 山东大学 | Low-power-consumption SAR ADC based on common-mode level switch switching and working method thereof |
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2019
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110034762A (en) * | 2019-04-23 | 2019-07-19 | 南京邮电大学 | A kind of adjustable analog-digital converter of sample frequency |
| CN110034762B (en) * | 2019-04-23 | 2024-03-26 | 南京邮电大学 | Sampling frequency adjustable analog-digital converter |
| CN112929026A (en) * | 2021-01-18 | 2021-06-08 | 电子科技大学 | SARADC based on variable comparator delay loop |
| CN114884508A (en) * | 2022-05-27 | 2022-08-09 | 山东大学 | Low-power-consumption SAR ADC based on common-mode level switch switching and working method thereof |
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