CN114826271B - High-speed dynamic parallel logic circuit applied to SAR ADC - Google Patents
High-speed dynamic parallel logic circuit applied to SAR ADC Download PDFInfo
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- CN114826271B CN114826271B CN202210409458.7A CN202210409458A CN114826271B CN 114826271 B CN114826271 B CN 114826271B CN 202210409458 A CN202210409458 A CN 202210409458A CN 114826271 B CN114826271 B CN 114826271B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/34—Analogue value compared with reference values
- H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
- H03M1/46—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter
- H03M1/462—Details of the control circuitry, e.g. of the successive approximation register
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- H—ELECTRICITY
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- H03K19/01—Modifications for accelerating switching
- H03K19/017—Modifications for accelerating switching in field-effect transistor circuits
- H03K19/01728—Modifications for accelerating switching in field-effect transistor circuits in synchronous circuits, i.e. by using clock signals
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/34—Analogue value compared with reference values
- H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
- H03M1/46—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter
- H03M1/466—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter using switched capacitors
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Abstract
The invention discloses a high-speed dynamic parallel logic circuit applied to an SAR ADC, which has the characteristics of high speed, parallelism and low power consumption. The traditional asynchronous SAR ADC logic needs to wait for the arrival of a bit selection signal and then perform capacitor inversion, and then perform next comparison, so that the logic delay of bit selection is generated to prolong the two comparison gaps, thereby slowing down the highest operable speed of the SAR ADC and limiting the sampling rate of the SAR ADC. According to the invention, the parallel logic is adopted to control the overturn of the capacitor array, and after the comparison result is obtained by the comparator, the capacitor overturn signal is immediately generated, so that the defect that the speed of the traditional asynchronous SAR ADC logic is limited due to logic delay is avoided by generating the bit selection signal first and then overturning.
Description
Technical Field
The invention belongs to the technical field of analog circuit design, and particularly relates to a high-speed dynamic parallel logic circuit applied to an SAR ADC.
Background
As shown in fig. 1, in the logic timing diagram of the conventional asynchronous SAR ADC, one conversion period is composed of a comparator delay, a logic delay, and a DAC setup delay, wherein the comparator delay is determined by the speed of the comparator, and the DAC setup delay is determined by the driving switch and the capacitor size. The DAC is set up after the logic delay of the SAR ADC logic to generate the bit select signal, so the time of one conversion period is extended, slowing down.
Disclosure of Invention
In view of the above, the present invention proposes a parallel SAR ADC control logic, as shown in fig. 2. The DAC establishment process is immediately carried out after the result is obtained by the comparator, so that logic delay is omitted, the time required by one converter period is shortened, and the overall conversion speed is improved.
According to the invention, the bit selection turn-off signal is generated to replace the bit selection turn-on signal of the traditional SAR ADC logic, and after the DAC is established, the control channel of the current bit is turned off, so that the capacitor inversion control signal of the previous bit is not influenced by the subsequent comparison. And the control logic of the next stage is input to the control logic of the next stage by sequentially changing the bit selection turn-off signal into high level, so that the control of the next stage is sequentially enabled.
The invention adopts the technical scheme that the transistor comprises a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, a tenth transistor M10, an eleventh transistor M11, a twelfth transistor M12, a first NAND gate NAND1 and a second NAND gate NAND2, wherein
The source electrode of the first transistor M1 is connected with the power supply VDD, the drain electrode of the first transistor M1 is connected with the drain electrode of the second transistor M2, the grid electrodes of the fourth transistor M4 and the sixth transistor M6, and the grid electrodes of the fourth transistor M4 and the sixth transistor M6 are connected with the first control signal D;
the source electrode of the second transistor M2 is connected with the drain electrode of the third transistor M3, the drain electrode is connected with the drain electrode of the first transistor M1, and the grid electrode is connected with the second control signal Valid and the grid electrode of the fifth transistor M5;
the source electrode of the third transistor M3 is grounded, the drain electrode is connected with the source electrode and the grid electrode of the second transistor M2 are connected with the first control signal D;
the source electrode of the fourth transistor M4 is connected with the power supply VDD, the drain electrode of the fourth transistor M5 is connected with the source electrode of the fifth transistor M5, and the grid electrode of the fourth transistor M6 is connected with the grid electrodes of the first transistor M1 and the second transistor M2;
the source electrode of the fifth transistor M5 is connected with the drain electrode of the fourth transistor M4, the drain electrode is connected with the third output signal Q and is connected with the drain electrodes of the sixth transistor M6, the gates of the ninth transistor M9 and the tenth transistor M10, and the gates are connected with the second control signal Valid and the gate electrode of the second transistor M2;
the source electrode of the sixth transistor M6 is grounded, the drain electrode is connected with the third output signal Q, the grid electrode is connected with the grid electrode of the fourth transistor M4, the drain electrodes of the first transistor M1 and the second transistor M2;
the source electrode of the seventh transistor M7 is connected with the power supply VDD, the drain electrode of the seventh transistor M9 is connected with the source electrode, and the grid electrode of the seventh transistor M7 is connected with the output of the first NAND gate NAND 1;
the source electrode of the eighth transistor M8 is connected with the power supply VDD, the drain electrode of the eighth transistor M10 is connected with the source electrode, and the grid electrode of the eighth transistor M8 is connected with the output of the second NAND gate NAND 2;
the source electrode of the ninth transistor M9 is connected with the drain electrode of the seventh transistor M7, and the drain electrode is connected with the drain electrode of the eleventh transistor M11 and the first output signal N; the grid electrode is connected with the drain electrodes of the fifth transistor M5 and the sixth transistor M6 and is connected with a third output signal Q;
the source of the tenth transistor M10 is connected with the drain of the eighth transistor M8, and the drain is connected with the drain of the twelfth transistor M12 and the second output signal P; the grid electrode is connected with the drain electrodes of the fifth transistor M5 and the sixth transistor M6 and is connected with a third output signal Q;
the source electrode of the eleventh transistor M11 is grounded, the drain electrode of the eleventh transistor M9 is connected with the drain electrode of the ninth transistor M9 and the first output signal N, and the grid electrode of the eleventh transistor M is connected with the third control signal CLks;
the source electrode of the twelfth transistor M12 is grounded, the drain electrode is connected with the drain electrode of the tenth transistor M10 and the second output signal P, and the gate electrode is connected with the third control signal CLks;
the input of the first NAND gate NAND1 is connected with a first input signal VIN and a first control signal D, and the output of the first NAND gate NAND1 is connected with the gate of the seventh transistor M7;
the input of the second NAND gate NAND2 is connected with a second input signal VIP and a first control signal D, and the output of the second NAND gate NAND2 is connected with the grid electrode of the eighth transistor M8;
the first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, the fifth transistor M5 and the sixth transistor M6 form a dynamic D flip-flop, the trigger input signal of which is the first control signal D, the clock driving signal is the second control signal Valid, the second control signal Valid is generated by the output end of the comparator through the or gate, once the output of the comparator is Valid, the Valid signal becomes high level, otherwise, the Valid signal becomes low level. The dynamic D flip-flop has the functions of generating a bit selection turn-off function and providing a trigger signal for the next-stage parallel logic, and when the second control signal Valid jumps from a high level to a low level, the third output signal Q is pulled high, so that the ninth transistor M9 and the tenth transistor M10 are not conducted, the output result of the later comparator is ensured not to influence the overturning of the previous-bit capacitor, and the function of bit non-selection is realized.
The seventh transistor M7, the eighth transistor M8, the ninth transistor M9, the tenth transistor M10, the eleventh transistor M11, the twelfth transistor M12, the first NAND gate NAND1, and the second NAND gate NAND2 constitute a capacitance inversion logic. The first control signal D is a third output signal Q generated by a previous capacitor control logic; n and P are respectively a first output signal and a second output signal, and the connection combination logic respectively controls the overturning of the corresponding bit capacitors at the positive end and the negative end of the differential capacitor array; the third control signal clk is a sampling signal for resetting the first output signal N and the second output signal P to ground.
The circuit has the advantages of high speed, parallelism and low power consumption. The traditional asynchronous SAR ADC logic needs to wait for the arrival of a bit selection signal and then perform capacitor inversion, and then perform next comparison, so that the logic delay of bit selection is generated to prolong the two comparison gaps, thereby slowing down the highest operable speed of the SAR ADC and limiting the sampling rate of the SAR ADC. According to the invention, the parallel logic is adopted to control the overturn of the capacitor array, and after the comparison result is obtained by the comparator, the capacitor overturn signal is immediately generated, so that the defect that the speed of the traditional asynchronous SAR ADC logic is limited due to logic delay is avoided by generating the bit selection signal first and then overturning.
Drawings
FIG. 1 is a timing diagram of conventional SAR ADC control logic;
FIG. 2 is a high-speed dynamic parallel logic circuit for SAR ADC according to the present invention;
FIG. 3 is an example of a 6-bit SAR ADC control logic constructed using the high speed dynamic parallel logic circuit of the present invention;
FIG. 4 is a timing diagram of an example 6-bit SAR ADC control logic constructed using the high-speed dynamic parallel logic circuit of the present invention;
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the following detailed description will be made with reference to the accompanying drawings and detailed description.
The invention is applied to a high-speed dynamic parallel logic circuit of an SAR ADC, which comprises a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, a tenth transistor M10, an eleventh transistor M11, a twelfth transistor M12, a first NAND gate NAND1 and a second NAND gate NAND2, wherein the source electrode of the first transistor M1 is connected with a power supply VDD, the drain electrode of the second transistor M2 is connected with the drain electrode of the first transistor M4 and the gate electrode of the sixth transistor M6, and the gate electrode of the first transistor M12 is connected with a first control signal D; the source electrode of the second transistor M2 is connected with the drain electrode of the third transistor M3, the drain electrode is connected with the drain electrode of the first transistor M1, and the grid electrode is connected with the second control signal Valid and the grid electrode of the fifth transistor M5; the source electrode of the third transistor M3 is grounded, the drain electrode is connected with the source electrode and the grid electrode of the second transistor M2 are connected with the first control signal D; the source electrode of the fourth transistor M4 is connected with the power supply VDD, the drain electrode of the fourth transistor M5 is connected with the source electrode of the fifth transistor M5, and the grid electrode of the fourth transistor M6 is connected with the grid electrodes of the first transistor M1 and the second transistor M2; the source electrode of the fifth transistor M5 is connected with the drain electrode of the fourth transistor M4, the drain electrode is connected with the third output signal Q and is connected with the drain electrodes of the sixth transistor M6, the gates of the ninth transistor M9 and the tenth transistor M10, and the gates are connected with the second control signal Valid and the gate electrode of the second transistor M2; the source electrode of the sixth transistor M6 is grounded, the drain electrode is connected with the third output signal Q, the grid electrode is connected with the grid electrode of the fourth transistor M4, the drain electrodes of the first transistor M1 and the second transistor M2; the source electrode of the seventh transistor M7 is connected with the power supply VDD, the drain electrode of the seventh transistor M9 is connected with the source electrode, and the grid electrode of the seventh transistor M7 is connected with the output of the first NAND gate NAND 1; the source electrode of the eighth transistor M8 is connected with the power supply VDD, the drain electrode of the eighth transistor M10 is connected with the source electrode, and the grid electrode of the eighth transistor M8 is connected with the output of the second NAND gate NAND 2; the source electrode of the ninth transistor M9 is connected with the drain electrode of the seventh transistor M7, and the drain electrode is connected with the drain electrode of the eleventh transistor M11 and the first output signal N; the grid electrode is connected with the drain electrodes of the fifth transistor M5 and the sixth transistor M6 and is connected with a third output signal Q; the source of the tenth transistor M10 is connected with the drain of the eighth transistor M8, and the drain is connected with the drain of the twelfth transistor M12 and the second output signal P; the grid electrode is connected with the drain electrodes of the fifth transistor M5 and the sixth transistor M6 and is connected with a third output signal Q; the source electrode of the eleventh transistor M11 is grounded, the drain electrode of the eleventh transistor M9 is connected with the drain electrode of the ninth transistor M9 and the first output signal N, and the gate electrode of the eleventh transistor M is connected with the third control signal Clks; the source electrode of the twelfth transistor M12 is grounded, the drain electrode is connected with the drain electrode of the tenth transistor M10 and the second output signal P, and the gate electrode is connected with the third control signal Clks; the input of the first NAND gate NAND1 is connected with a first input signal VIN and a first control signal D, and the output of the first NAND gate NAND1 is connected with the gate of the seventh transistor M7; the input of the second NAND gate NAND2 is connected with a second input signal VIP and a first control signal D, and the output of the second NAND gate NAND2 is connected with the grid electrode of the eighth transistor M8;
the high-speed dynamic parallel logic circuit shown in fig. 2 can better describe the operation mode of the invented circuit by combining the 6-bit SAR ADC control logic shown in fig. 3 and the timing diagram shown in fig. 4: the 6-bit SAR ADC control logic in the third drawing consists of 6 high-speed dynamic parallel logic circuits which are invented and are sequentially expressed as C1-C6, and the first control logic at the leftmost side controls the first bit capacitor in the DAC array and sequentially controls the latter several bits capacitors to the right. Clks_B is the inverse of the sampling signal Clks, and Clks_B is the input of the first control signal D of the first capacitance control logic. When the sampling signal clk is at a high level, the comparator is reset, and OUTP and OUTN shown in fig. 4 are that the positive output terminal and the negative output terminal of the comparator are both reset to a low level, so the second control signal Valid is at a low level; the SAR ADC samples, at this time, the eleventh transistor M11 and the twelfth transistor M12 are turned on, pull the first output signal N and the second output signal P to ground, the first output signal N and the second output signal P of the 6 control logics are in reset states, the lower electrode plates of all the capacitors at the positive terminal and the negative terminal of the capacitor array are all ground, and the gates of the ninth transistor M9 and the tenth transistor M10 in C1 to C6 are low level, so they are turned on. While the outputs of the first NAND gate NAND1 and the second NAND gate NAND2 are both high, so neither the seventh transistor M7 nor the eighth transistor M8 is turned on.
When the sampling signal Clks is low, the comparator enable signal Clkc is at high level, and the comparator starts to compare; clks_b is high, so the first control signal D of the control logic C1 is high, pulling the drain of the third transistor M3 to ground. After the result of the comparator, the comparator obtains an output result, one of the positive and negative output terminals OUTP and OUTN of the comparator is at a high level and one of the positive and negative output terminals OUTP and OUTN of the comparator is at a low level, so that one of the first input signal VIN and the second input signal VIP of the first NAND gate NAND1 and the second NAND gate NAND2 of C1 to C6 is at a high level and one of the first control signal D of C1 is at a low level, at this time, the outputs of the first NAND gate NAND1 and the second NAND gate NAND2 are controlled by the first input signal VIN and the second input signal VIP, one of the first control signal D of the first NAND gate NAND1 and the second NAND gate NAND2 of C2 to C6 is still at a low level, and both the outputs are still at a high level, so that neither the seventh transistor M7 nor the eighth transistor M8 are turned on. The outputs of the first NAND gate NAND1 and the second NAND gate NAND2 in C1 are high and low due to the difference between the first input signal VIN and the second input signal VIP, and because the ninth transistor M9 and the tenth transistor M10 are turned on at this time, one end of the first output signal N and one end of the second output signal P are quickly pulled up, and the capacitor lower plate controlled by the first output signal N and the second output signal P is quickly charged to the reference voltage Vref, and one is still grounded. Meanwhile, the second control signal Valid becomes high because the output of the comparator is Valid, the second transistor M2 is turned on, the drain thereof is discharged to low, and the fourth transistor M4 is turned on, the drain thereof is pulled to high. When the second control signal Valid is high, the comparison signal Clkc of the comparator is pulled down, the comparator is reset, after a certain delay, the second control signal Valid is pulled down because both ends of the comparator are reset to low level, when the second control signal Valid is pulled down, the fifth transistor M5 is turned on, the third output signal Q is pulled up, resulting in the turning-off of the ninth transistor M9 and the tenth transistor M10, and therefore, the first output signal N and the second output signal P point potential in C1 are not affected by the result after the next comparison, that is, the first output signal N and the second output signal P potential in C1 are locked before the next comparison. And because the second control signal Valid is pulled low and Clkc is pulled high again, and the next comparison starts, and because the first control signals D of the first NAND gate NAND1 and the second NAND gate NAND2 in C2 are connected to the third output signal Q of C1, the first control signals D of the first NAND gate NAND1 and the second NAND gate NAND2 in C2 are pulled high, and the result obtained in the second comparison is Valid for the seventh transistor M7 and the eighth transistor M8 in C2.
The outputs SC 1-SC 6 of C1-C6 are sequentially pulled up, the first output signal N and the second output signal P of C1-C6 are sequentially locked, and the function of bit selection and turn-off is time sequence; the first control signals D of C1-C6 are sequentially pulled high, the first NAND gate NAND1 and the second NAND gate NAND2 are sequentially enabled, and the capacitance controlled by the first output signal N and the second output signal P is sequentially inverted. Until C6 is pulled up, the comparison signal Clkc of the comparator is pulled down, the comparison is stopped, the first output signal N and the second output signal P in C1 to C6 are reset again when the next sampling signal comes, and the third output signal Q is reset low, that is, SC1 to SC6 are reset to low level.
Claims (1)
1. A high-speed dynamic parallel logic circuit applied to a SAR ADC, wherein the SAR ADC comprises a comparator, a CDAC and a logic circuit, an input control signal of the logic circuit is a sampling signal and an output signal of the comparator, and an output signal of the logic circuit is used as a reference voltage selection signal of the CDAC, and the high-speed dynamic parallel logic circuit is characterized by comprising a first transistor (M1), a second transistor (M2), a third transistor (M3), a fourth transistor (M4), a fifth transistor (M5), a sixth transistor (M6), a seventh transistor (M7), an eighth transistor (M8), a ninth transistor (M9), a tenth transistor (M10), an eleventh transistor (M11), a twelfth transistor (M12), a first NAND gate (NAND 1) and a second NAND gate (NAND 2), wherein,
the source electrode of the first transistor (M1) is connected with the power supply VDD, the drain electrode of the first transistor (M1) is connected with the drain electrode of the second transistor (M2), the grid electrodes of the fourth transistor (M4) and the sixth transistor (M6), and the grid electrode of the first transistor (M1) is connected with the first control signal D;
the source electrode of the second transistor (M2) is connected with the drain electrode of the third transistor (M3), the drain electrode is connected with the drain electrode of the first transistor (M1), and the grid electrode is connected with the second control signal Valid and the grid electrode of the fifth transistor (M5);
the source electrode of the third transistor (M3) is grounded, the drain electrode is connected with the source electrode of the second transistor (M2), and the grid electrode is connected with the first control signal D;
the source electrode of the fourth transistor (M4) is connected with the power supply VDD, the drain electrode of the fourth transistor is connected with the source electrode of the fifth transistor (M5), and the grid electrode of the fourth transistor (M4) is connected with the grid electrode of the sixth transistor (M6), the drain electrodes of the first transistor (M1) and the second transistor (M2);
the source electrode of the fifth transistor (M5) is connected with the drain electrode of the fourth transistor (M4), the drain electrode of the fifth transistor (M5) is connected with the third output signal Q and is connected with the drain electrode of the sixth transistor (M6), the gates of the ninth transistor (M9) and the tenth transistor (M10), and the gate electrode of the fifth transistor (M5) is connected with the second control signal Valid and the gate electrode of the second transistor (M2);
the source electrode of the sixth transistor (M6) is grounded, the drain electrode is connected with the third output signal Q, the grid electrode is connected with the grid electrode of the fourth transistor (M4), the drain electrodes of the first transistor (M1) and the second transistor (M2);
the source electrode of the seventh transistor (M7) is connected with the power supply VDD, the drain electrode of the seventh transistor (M9) is connected with the source electrode of the ninth transistor (M9), and the grid electrode of the seventh transistor (M7) is connected with the output of the first NAND gate (NAND 1);
the source electrode of the eighth transistor (M8) is connected with the power supply VDD, the drain electrode of the eighth transistor (M10) is connected with the source electrode of the tenth transistor, and the grid electrode of the eighth transistor (M8) is connected with the output of the second NAND gate (NAND 2);
a source electrode of the ninth transistor (M9) is connected with a drain electrode of the seventh transistor (M7), and a drain electrode of the ninth transistor (M9) is connected with a drain electrode of the eleventh transistor (M11) and the first output signal N; the grid electrode of the ninth transistor (M9) is connected with the drains of the fifth transistor (M5) and the sixth transistor (M6) and is connected with the third output signal Q;
the source of the tenth transistor (M10) is connected with the drain of the eighth transistor (M8), and the drain of the tenth transistor (M10) is connected with the drain of the twelfth transistor (M12) and the second output signal P; the grid electrode is connected with the drains of the fifth transistor (M5) and the sixth transistor (M6) and is connected with a third output signal Q;
the source electrode of the eleventh transistor (M11) is grounded, the drain electrode is connected with the drain electrode of the ninth transistor (M9) and the first output signal N, and the grid electrode of the eleventh transistor (M11) is connected with the third control signal Clks;
the source electrode of the twelfth transistor (M12) is grounded, the drain electrode is connected with the drain electrode of the tenth transistor (M10) and the second output signal P, and the grid electrode of the twelfth transistor (M12) is connected with the third control signal Clks;
the input of the first NAND gate (NAND 1) is connected with the first input signal VIN and the first control signal D, and the output is connected with the grid electrode of the seventh transistor (M7);
the input of the second NAND gate (NAND 2) is connected with the second input signal VIP and the first control signal D, and the output is connected with the grid electrode of the eighth transistor (M8);
the first transistor (M1), the second transistor (M2), the third transistor (M3), the fourth transistor (M4), the fifth transistor (M5) and the sixth transistor (M6) form a dynamic D trigger, the input end of the dynamic D trigger is a first control signal D, the clock driving signal is a second control signal Valid, the second control signal Valid is generated by the output end of the comparator through an OR gate, once the output of the comparator is Valid, the second control signal Valid becomes high level, otherwise, the second control signal Valid is low level; the dynamic D flip-flop is used for generating a bit selection switching-off function to provide a comparison result enabling signal for the next-stage parallel logic, when the second control signal Valid jumps from a high level to a low level, the third output signal Q is pulled high, so that the ninth transistor (M9) and the tenth transistor (M10) are not conducted, and the bit selection switching-off function is realized.
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| CN111030697A (en) * | 2019-12-31 | 2020-04-17 | 江苏科大亨芯半导体技术有限公司 | High-speed low-power-consumption successive approximation type analog-to-digital converter |
| US10862496B1 (en) * | 2019-07-30 | 2020-12-08 | Xilinx, Inc. | High-speed successive-approximation-register (SAR) analog-to-digital converter (ADC) control logic circuit |
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| US10862496B1 (en) * | 2019-07-30 | 2020-12-08 | Xilinx, Inc. | High-speed successive-approximation-register (SAR) analog-to-digital converter (ADC) control logic circuit |
| CN111030697A (en) * | 2019-12-31 | 2020-04-17 | 江苏科大亨芯半导体技术有限公司 | High-speed low-power-consumption successive approximation type analog-to-digital converter |
| CN112134565A (en) * | 2020-09-15 | 2020-12-25 | 珠海迈巨微电子有限责任公司 | Low-power-consumption successive approximation type analog-to-digital converter |
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