CN214675121U - Analog-digital converter with multi-mode selection - Google Patents

Abstract

The utility model discloses an analog-to-digital converter of multi-mode selection, which relates to the technical field of integrated circuits and comprises a non-overlapping clock, a bootstrap switch, an operational amplifier type selection module, an internal clock generation unit, a DAC control logic unit, an asynchronous delay logic unit, a DAC capacitor array, a delay logic module, a first delay selector and a second delay selector; the utility model adopts the first delay selector and the second delay selector, the first delay selector and the second delay selector adopt three identical delay times, and nine asynchronous clocks with different delays are formed by selecting a delay time mode, so that the sampling frequency is adjustable; the utility model discloses well adoption operational amplifier type selection module contains two kinds of operational amplifier: the first-stage operational amplifier is added with a second-stage latch and a comparator, and the type of the operational amplifier is selected through an operational amplifier type selector and the operational amplifier type selector; the utility model discloses well capacitor array adopts a transmission door switch, turns off the on-state through the transmission door switch and realizes the digit conversion.

Description

Analog-digital converter with multi-mode selection

Technical Field

The utility model relates to an integrated circuit technical field especially relates to an analog-to-digital converter of multi-mode selection.

Background

The a/D converter is an important bridge connecting an Analog system and a digital signal processing system, and is widely applied to the fields of digital signal processing technology and wireless communication, so that the demand for an ADC (Analog-to-digital converter) based on a CMOS process is increasing, and ADCs converted in multiple modes can be applied to different occasions according to actual scenes, wherein some occasions require ADCs with high precision and high sampling rate, and some occasions require ADCs with high precision and low sampling rate. The sampling frequency of a traditional SAR (Successive Approximation Register) A/D conversion circuit is fixed, the adjustable sampling frequency cannot be realized, the precision (namely the digit of DAC) and an operational amplifier are fixed, the precision conversion cannot be carried out, and the type conversion of the operational amplifier cannot be carried out.

SUMMERY OF THE UTILITY MODEL

The utility model aims to solve the technical problem that the utility model provides an analog-to-digital converter of multi-mode selection to the deficiency of background art, adopts the first time delay selector and the second time delay selector, and the first time delay selector and the second time delay selector all adopt three kinds of the same time delay, and the first time delay selector and the second time delay selector provide 9 kinds of time delay selection, thereby realized that sampling frequency is adjustable; the conversion of the first operational amplifier and the second operational amplifier is realized by adopting the first operational amplifier and the second operational amplifier through an operational amplifier type selection module; the DAC capacitor array comprises transmission gate switches, and bit conversion is realized by the on-off state of the transmission gate switches.

The utility model discloses a solve above-mentioned technical problem and adopt following technical scheme:

a multi-mode selection analog-to-digital converter comprises an operational amplifier type selection module, a delay logic module, a first delay selector, a second delay selector and a Successive Approximation Register (SAR); one end of the delay logic module is connected with the operational amplifier type selection module, and the other end of the delay logic module is connected with one end of the second delay selector; the other end of the second delay selector is respectively connected with a Successive Approximation Register (SAR) and one end of a first delay selector, and the other end of the first delay selector is connected with the output end of the operational amplifier type selection module.

As a further preferred aspect of the analog-to-digital converter of the present invention, the operational amplifier type selection module comprises two kinds of operational amplifiers: a first operational amplifier and a second operational amplifier, and the first operational amplifier and the second operational amplifier have a common input terminal: and common input ends of the Vbias end, the VIN end and the VIP end are all connected with an operational amplifier type selector, wherein the first operational amplifier comprises a first-stage operational amplifier and a second-stage latch, and the second operational amplifier comprises a comparator.

As a further preferred scheme of the analog-to-digital converter of the multi-mode selection of the present invention, the analog-to-digital converter further comprises a bootstrap switch, a non-overlapping clock, an internal clock generation unit, a DAC control logic unit, a first DAC capacitance array, a second DAC capacitance array, and an asynchronous delay logic unit, wherein the CLK input end of the non-overlapping clock is connected to the sampling signal, and the CLK _1N output end and the CLK _2N output end of the non-overlapping clock are respectively connected to the CLK _1N input end and the CLK _2N input end of the bootstrap switch; the Valid output end of the operational amplifier type selection module is connected with the Valid input end of the internal clock generation unit, meanwhile, the Valid output end of the operational amplifier type selection module is also connected with the Valid input end of the asynchronous delay logic unit, and the VOUTN output end and the VOUTP output end of the operational amplifier type selection module are respectively and correspondingly connected with the INN input end and the INP input end of the DAC control logic unit; CAP _ N (P) output ends of the DAC control logic units are connected with the input ends of the corresponding DAC capacitor arrays.

As the utility model relates to a multi-mode selection's analog-to-digital converter's further preferred scheme, first DAC electric capacity array and second DAC electric capacity array all include the transmission gate switch to and with transmission gate switch connection electric capacity array, the C10 of electric capacity array is connected to transmission gate switch one end, and the positive pole input of electric capacity array and operational amplifier type selection module is connected to the other end.

As a further preferred embodiment of the analog-to-digital converter with multi-mode selection of the present invention, the SAMPLE input terminal of the internal clock generating unit is connected to the sampling signal, the output terminals C1 to C10 are respectively connected to the input terminals C1 to C10 of the DAC control logic unit, and meanwhile, the terminals C1 to C10 of the internal clock generating unit are also respectively connected to the terminals C1 to C10 of the asynchronous delay logic unit; the CNi end and the CPi end of the DAC control logic unit are respectively connected with the CNi input end and the CPi input end of the asynchronous delay logic unit, and the external reference voltage Vref is connected with the Vref input end of the DAC control logic unit; the outputs S2-S10 of the asynchronous delay logic unit are connected to the corresponding inputs S2-S10, and the V _ CLC output is connected to the V _ CLC input of the operational amplifier type selection module.

As a further preferred aspect of the analog-to-digital converter with multi-mode selection of the present invention, the first delay selector and the second delay selector all use three identical delays.

The utility model adopts the above technical scheme to compare with prior art, have following technological effect:

1. the utility model adopts the first delay selector and the second delay selector, the first delay selector and the second delay selector adopt three identical delays, and the first delay selector and the second delay selector provide 9 delay selections, thereby realizing adjustable sampling frequency;

2. the utility model discloses an operational amplifier type select module contain two kinds of operational amplifier: the operational amplifier comprises an operational amplifier 1 and an operational amplifier 2, wherein the operational amplifier 1 comprises a first-level operational amplifier and a second-level latch, the operational amplifier 2 comprises a comparator, and the selection of the operational amplifier 1 or 2 is realized through an operational amplifier type selection module;

3. the utility model discloses an operational amplifier type selector, wherein switch circuit can be regarded as a NOR gate logic module, selects the operational amplifier type through switch circuit control.

4. The utility model discloses a DAC capacitor array include the transmission gate switch, turn-off the closed state through the transmission gate switch and realize the digit conversion.

Drawings

FIG. 1 is a diagram of the overall system architecture of the present invention;

fig. 2 is a circuit diagram of the operational amplifier 1 of the present invention;

fig. 3 is a circuit diagram of the operational amplifier 2 of the present invention;

fig. 4 is a circuit diagram of the operational amplifier type selector of the present invention;

FIG. 5 is a circuit diagram of a non-overlapping clock of the present invention;

fig. 6 is a circuit diagram of the bootstrap switch of the present invention;

FIG. 7 is a circuit diagram of the internal clock generating unit of the present invention;

fig. 8 is a circuit diagram of the DAC control logic unit of the present invention;

fig. 9 is a circuit diagram of the asynchronous delay logic unit of the present invention;

FIG. 10 is a circuit diagram of a delay selector;

fig. 11 is a circuit diagram of the delay selector switch.

Detailed Description

Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments may, however, be embodied in many different forms and should not be construed as limited to the examples set forth herein; rather, these example embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art. The drawings are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and thus their repetitive description will be omitted.

Furthermore, the described features, structures, or characteristics may be combined in any suitable manner in one or more example embodiments. In the following description, numerous specific details are provided to give a thorough understanding of example embodiments of the disclosure. One skilled in the relevant art will recognize, however, that the subject matter of the present disclosure can be practiced without one or more of the specific details, or with other methods, components, steps, and so forth. In other instances, well-known structures, methods, implementations, or operations are not shown or described in detail to avoid obscuring aspects of the disclosure.

As shown in fig. 1, an analog-to-digital converter with multi-mode selection includes a delay logic module, a first delay selector and a second delay selector, one end of the delay logic module is connected to an operational amplifier type selection module, the other end is connected to one end of the second delay selector, one end of the first delay selector is connected to the operational amplifier type selection module, and the other end of the first delay selector is connected to the other end of the second delay selector and a Successive Approximation Register (SAR). The circuit also comprises a non-overlapping clock, an internal clock generation unit, a DAC control logic unit and a DAC capacitor array 1 (or 2), wherein the CLK input end of the non-overlapping clock is connected with a sampling signal; as shown in fig. 2 and fig. 3, the Vbias bias of the operational amplifier 1(2) is terminated with a bias voltage, two output ends of the operational amplifier 1 (or 2) are connected to two input ends of an and gate on one hand, and are correspondingly connected to an INN input end and an INP input end of the DAC control logic unit on the other hand, and a Valid output end of the operational amplifier type selection module is connected to a Valid input end of the internal clock generation unit and a Valid input end of the asynchronous delay logic unit respectively; as shown in fig. 6, the CLK input terminal of the non-overlap clock is connected to the sampling signal, the CLK _1N output terminal and the CLK _2N output terminal of the non-overlap clock are respectively connected to the CLK _1N input terminal and the CLK _2N input terminal of the bootstrap switch, the Vin input terminal of the bootstrap switch is connected to the input signal, and the Vout output terminal of the bootstrap switch is respectively connected to the Vin input terminal of the operational amplifier type selection module and the output terminal of the DAC capacitor array 1 (2).

As shown in fig. 7, the SAMPLE input terminal of the internal clock generation unit is connected to the sampling signal, the output terminal of C1 to the output terminal of C10 are respectively connected to the input terminals of C1 to C10 of the DAC control logic unit, and the terminals C1 to C10 of the internal clock generation unit are also respectively connected to the terminals C1 to C10 of the asynchronous delay logic unit; as shown in fig. 8, the CAP _ n (p) output end of the DAC control logic unit is connected to the input end of the corresponding DAC capacitor array 1(2), the CNi end and the CPi end of the DAC control logic unit are respectively connected to the CNi input end and the CPi input end of the asynchronous delay logic unit, the external reference voltage Vref is not only connected to the Vref input end of the DAC control logic unit, but also the Vref input ends of other modules in the circuit are connected to the external reference voltage Vref; as shown in FIG. 9, the outputs S2-S10 of the asynchronous delay logic cell are coupled to the corresponding inputs S2-S10, and the V _ CLC output is coupled to the V _ CLC input of the operational amplifier type selection module.

As shown in fig. 1, the utility model discloses a traditional monotonicity capacitance switch process, the characteristics that monotonicity capacitance switch process has are: 1. the fully differential structure can suppress power supply noise, and the common mode rejection ratio is also good; 2. the input end obtains input voltage (VIP, VIN) after sampling, and the input voltage directly enters the first comparison without consuming energy. Assuming that VIP > VIN, the Valid signal is high, an internal clock signal is triggered, the highest signal bit (MSB) corresponding to the P end is 1, the capacitance of the highest signal bit is connected to the ground, the capacitances of the rest signal bits are kept unchanged, the capacitance of the N end is also kept unchanged, and VIP = VIP-Vref/2 at the moment; over time, the op amp type selection module is reset and the input enters the comparison, which keeps the cycle until the Least Significant Bit (LSB) bit is asserted.

As shown in fig. 1, the basic principle of a multimode selective analog-to-digital converter is as follows: when the sampling clock is high, the upper electrode plate of the capacitor array samples input voltages VIP and VIN through the bootstrap switch, and the lower electrode plate of the capacitor is connected to a reference level. When the sampling clock changes to low level, the sampling is finished and the conversion stage is entered. The input end of the operational amplifier type selection module compares sampling values, and the output result is sent to the SAR logic control unit through the first delay selector to control the level of each capacitor lower plate of the DAC capacitor array on one hand, and is sent to the delay logic module and the second delay selector on the other hand, so that the operational amplifier type selection module enters a reset state. It should be appreciated that the inputs of the first time op amp type selection block are compared directly. Assuming that VIN is larger than VIP, triggering by the first internal clock, grounding a VIN-end capacitance switch, redistributing a DAC capacitance array, reducing the voltage of an input end with large voltage, grounding the capacitance switch, VIN = VIN-Vref/2, keeping VIP unchanged, connecting Vref to the capacitance switch, resetting an operational amplifier type selection module, starting comparison for the second time, and sequentially circulating for 10 times. The structure follows "compare first, then change": and comparing by an operational amplifier type selection module, and redistributing the charges of the capacitor array. The first comparison means that after sampling is finished, the operational amplifier type selection module directly compares two input voltages, changes the connection of the lower polar plate of the highest-order capacitor at one end according to a comparison result, and when the DAC capacitor array is stabilized, the operational amplifier type selection module performs second comparison, the level of the next highest-order capacitor array is changed again, and the operation is circulated for 10 times all the time. The circuit optimization part adopts the basic principle of a first delay selector and a second delay selector: by selecting the type of the first delay selector (such as 300ns/600ns/900 ns) and the type of the second delay selector (such as 300ns/600ns/900 ns), the occupation time of high and low levels of the asynchronous clock can be adjusted, so that the sampling frequency is further influenced, and the adjustable sampling frequency is realized.

As shown in fig. 1, the capacitor array 1 and the capacitor array 2 of the present invention both employ switches, one end of the switch inside the capacitor array 1 is connected to the C10 capacitor, and the other end is connected to the + pole of the operational amplification type selection module; one end of a switch in the capacitor array 2 is connected with the C10 capacitor, the other end of the switch is connected with a negative pole of the operational amplification type selection module, the switch is composed of a transmission gate and an inverter, when A =1, the switch is on, the capacitor array is 10 bits, when A =0, the switch is off, the capacitor array is 9 bits, and bit conversion is achieved through on and off of the transmission gate.

As shown in fig. 2, the operational amplifier 1 of the present invention comprises a pre-stage operational amplifier and a secondary latch, which can prevent the flyback noise and increase the comparison speed; the utility model discloses add M13 in operational amplifier type selection module, can improve voltage resolution and the comparison speed in the back imitation, VIN and VIP pass through preceding stage operational amplifier and enlarge input voltage, further improve voltage resolution. The operational amplifier 1 circuit operating principle: when V _ CLC is high, Valid is low; when V _ CLC is low, VIN and VIP pass through a preceding operational amplifier to amplify two comparison voltages, M3 and M4 terminals compare two input voltages, and due to the fact that cross coupling formed by M5 and M6 has a positive feedback effect, one end of VOUTN and VOUTP is high, the other end of VOUTN and VOUTP is low, Valid is high, and the internal clock signal Ci is triggered. Assuming that Vin > Vip, i.e. the voltage at node 3 rises faster than that at node 4, when the voltage at node 3 increases to turn on the M6 tube, a positive feedback is formed inside the circuit, and finally node 3 rises to a higher level, node 4 discharges to 0, and the whole comparison process is completed. Then, the V _ CLC signal becomes high level again, and the operational amplifier 1 enters a reset phase.

As shown in FIG. 3, the utility model discloses an operational amplifier 2 contains the comparator, the utility model discloses add M9 in operational amplifier type selection module, can improve the comparison speed in voltage resolution ratio and the back imitations. The operational amplifier type selection module circuit working principle is as follows: when V _ CLC is high, Valid is low; when V _ CLC is low, M3 and M4 terminals compare two input voltages, and because the cross coupling formed by M5 and M6 has a positive feedback effect, one end of VOUTN and VOUTP is high, the other end is low, Valid is high, and the internal clock signal Ci is triggered. Assuming that Vin > Vip, i.e. the voltage at node 3 rises faster than that at node 4, when the voltage at node 3 increases to turn on the M6 tube, a positive feedback is formed inside the circuit, and finally node 3 rises to a higher level, node 4 discharges to 0, and the whole comparison process is completed. Then, the V _ CLC signal becomes high again, and the operational amplifier 2 enters a reset phase.

As shown in fig. 4, the present invention adds an operational amplifier type selector to the operational amplifier type selection module, one end of the switch is respectively connected to Vbias, VIN and VIP, each switch circuit can be regarded as a combination of nor logic modules, when a and B are both low level, switch1 is turned on, switch2 is turned off, and the operational amplifier 1 is selected; when a is high and B is low, switch2 is on, switch1 is off, and operational amplifier 2 is selected. The selection of operational amplifiers 1 and 2 is achieved by the level state of A, B.

As shown in fig. 5, the non-overlap clock is added to the sample-and-hold circuit to improve the linearity of the sample-and-hold circuit; the two-phase clock generated by the inverter has a larger overlapping part, so that the MOS tube which is turned off when the sampling switch is turned on is also turned on, the capacitor stored on the charge can be partially disappeared, the grid source voltage of the bootstrap switch is changed, the nonlinear error of the switch is introduced, and the switch linearity of the sampling hold circuit (S/H) is reduced. In the non-overlapped clock, the CLK can generate two reverse non-overlapped clocks CLK _1N, CLK _2N, wherein CLK _1N is the clock in phase with the CLK, and CLK _2N is the non-overlapped reverse clock of CLK _1N, thus effectively avoiding overlapping and improving the linearity of S/H.

Fig. 6 is the bootstrap switch circuit of the present invention, when CLK _1N is low level, the sampling switch M10 is turned off, M1, M3, M4, M8, M9 are turned on, other tubes are turned off, the voltage of node 1 is charged to VDD, the voltage of node 2 is charged to ground, node 3 is charged to VDD, node 4 is discharged to ground, the amount of capacitor charge at this time is VDD × C; when CLK _1N is high, the sampling switch M10 is turned on, M7, M5 and M6 are turned on, the gate voltage of the sampling tube is equal to VDD + Vin, and Vout is equal to Vin.

Fig. 7 shows an internal clock generating unit circuit according to the present invention, the basic working principle of the circuit is: when the SAMPLE signal is high, the data conversion system is in the sampling phase, the internal clocks C1-C10 are all low, and the Valid signal is also low. When the SAMPLE signal is at a low level, the system enters a conversion stage, the operational amplifier type selection module starts to work, when output level values are different, the Valid signal changes to a high level, the D trigger selects rising edge triggering, and the rising edge of the Valid signal triggers the D trigger array, so that the C1 changes to a high level. The V _ CLC signal enables the operational amplifier type selection module to reset, VOUTN and VOUTP are changed into low level, so that Valid is changed from high level to low level, the V _ CLC signal is changed into low level after a period of delay, the operational amplifier type selection module starts to work again, when different levels are output, the Valid signal is changed from low level to high level, a rising edge triggers the D trigger array, C2 is changed into high level, the circuit works in sequence, and finally C10 is also changed into high level. Since the sampling signal is connected to the SET terminal (SET) of the D flip-flop, the circuit internal clocks C1-C10 are all reset to low when the system enters the next sampling phase, i.e., SAMPLE is high again.

As shown in fig. 8, the DAC control logic unit works according to the following principle: a time delay is required before the internal clock signal Ci is input to the and gates, which is to ensure that when inn (inp) is completely stabilized, the clock Ci opens the two-input and gates again to generate the capacitor driving signal (CAPDrive _ ni (pi)), and the capacitor driving signal controls the capacitor CAP _ n (p) of the corresponding capacitor array through the inverter. Assuming that Ci is transmitted to the and gate just after inn (inp) begins to change, inn (inp) changes from high to low, and the level of inn (inp) is higher at the beginning of the change, the voltage of the capacitor driving signal (CAPDrive _ ni (pi)) will rise from low to high, but will eventually stabilize at low, i.e. the voltage of the capacitor driving signal will include a sharp pulse signal, and the pulse sharp will prolong the settling time of the DAC, thereby reducing the switching speed of the whole system.

As shown in fig. 9, the Si signal in the asynchronous delay logic cell circuit is composed of 2 nor gate switches, the C1 signal and the a level generate the node B level through an and gate, and the B level and the sampling signal SAMPLE generate the V _ CLC signal through an or gate. In order to overcome the defect that a synchronous clock control circuit needs an internal clock which is N +1 (or N +2) times as a circuit main clock, the utility model adopts a novel asynchronous delay logic unit, and the asynchronous clock can be generated through the internal logic circuit; the working principle of the asynchronous delay logic unit is as follows: in the sampling stage, the Valid signal is low level, in the conversion stage, during the first comparison, the Valid signal is high, the internal clock sequence C1 goes high, C1 triggers the DAC control logic unit, CAPDrive _ ni (pi) has a signal at one end going high, the capacitor array redistributes, the asynchronous delay logic unit S2 goes high, the asynchronous signal V _ CLC goes low, the operational amplifier type selection module resets, during the second comparison, the Valid signal goes high, when C2 is low, the point a is connected to VDD and GND, the point a can be regarded as low, C2 goes high, S2 goes low, V _ CLC goes low, and sequentially loops for 10 times. The asynchronous delay logic unit starts to work after the capacitor is charged and discharged, and the ADC can work normally as long as the delay time of the delay circuit is ensured to be longer than the charging and discharging time of the corresponding capacitor array.

Fig. 10 shows a first delay selector and a second delay selector circuit, which include 3 delay units, each of which is formed by cascading two inverters, and can delay 300 ns. When the switch3 is closed, the switch4 and the switch5 are disconnected, and the point A and the point B are directly connected without time delay; when the switch4 is closed, the switch3 and the switch5 are disconnected, and a delay unit is connected into the circuit and delays for 300 ns; when the switch5 is closed, the switch3 and the switch4 are disconnected, two delay units connected in series are connected into the circuit, and the delay is 600 ns; when the switch3, the switch4 and the switch5 are all disconnected, three delay units connected in series are connected into the circuit, and the delay is 900 ns.

Fig. 11 is a delay selector switch circuit, where the first stage uses one inverter and three transmission gate switches, and the second stage uses one inverter and two transmission gate switches, when Ctrl1=1 and Ctrl2=1, switch3 is turned on, and both switch4 and switch5 are turned off; when Ctrl1=0 and Ctrl2=1, switch4 is turned on, and both switch3 and switch5 are turned off; when Ctrl1=1 and Ctrl2=0, switch5 is on, and both switch3 and switch4 are off. The control of the delay selection circuit is realized through the control mode.

It will be understood by those skilled in the art that, unless otherwise defined, all terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the prior art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

Above embodiment only is for explaining the utility model discloses a technical thought can not be injectd with this the utility model discloses a protection scope, all according to the utility model provides a technical thought, any change of doing on technical scheme basis all falls into the utility model discloses within the protection scope. The embodiments of the present invention have been described in detail with reference to the accompanying drawings, but the present invention is not limited to the above embodiments, and various changes can be made without departing from the spirit of the present invention within the knowledge of those skilled in the art.

Claims (6)

1. A multi-mode selective analog-to-digital converter, characterized by: the circuit comprises an operational amplifier type selection module, a delay logic module, a first delay selector, a second delay selector and a Successive Approximation Register (SAR); one end of the delay logic module is connected with the operational amplifier type selection module, and the other end of the delay logic module is connected with one end of the second delay selector; the other end of the second delay selector is respectively connected with a Successive Approximation Register (SAR) and one end of a first delay selector, and the other end of the first delay selector is connected with the output end of the operational amplifier type selection module.

2. A multimode selective analog-to-digital converter as in claim 1, characterized in that: the operational amplifier type selection module comprises two operational amplifiers: a first operational amplifier and a second operational amplifier, and the first operational amplifier and the second operational amplifier have a common input terminal: and common input ends of the Vbias end, the VIN end and the VIP end are all connected with an operational amplifier type selector, wherein the first operational amplifier comprises a first-stage operational amplifier and a second-stage latch, and the second operational amplifier comprises a comparator.

3. A multimode selective analog-to-digital converter as in claim 1, characterized in that: the circuit also comprises a bootstrap switch, a non-overlapped clock, an internal clock generation unit, a DAC control logic unit, a first DAC capacitor array, a second DAC capacitor array and an asynchronous delay logic unit, wherein the CLK input end of the non-overlapped clock is connected with a sampling signal, and the CLK _1N output end and the CLK _2N output end of the non-overlapped clock are respectively connected with the CLK _1N input end and the CLK _2N input end of the bootstrap switch; the Valid output end of the operational amplifier type selection module is connected with the Valid input end of the internal clock generation unit, meanwhile, the Valid output end of the operational amplifier type selection module is also connected with the Valid input end of the asynchronous delay logic unit, and the VOUTN output end and the VOUTP output end of the operational amplifier type selection module are respectively and correspondingly connected with the INN input end and the INP input end of the DAC control logic unit; CAP _ N (P) output ends of the DAC control logic units are connected with the input ends of the corresponding DAC capacitor arrays.

4. A multimode selective analog-to-digital converter as in claim 3, characterized in that: the first DAC capacitor array and the second DAC capacitor array both comprise transmission gate switches, the capacitor arrays are connected with the transmission gate switches, one ends of the transmission gate switches are connected with C10 of the capacitor arrays, and the other ends of the transmission gate switches are connected with the capacitor arrays and the anode input end of the operational amplifier type selection module.

5. A multimode selective analog-to-digital converter as in claim 4, characterized in that: the SAMPLE input end of the internal clock generation unit is connected with a sampling signal, the output end of C1 to the output end of C10 are correspondingly connected with the input ends of C1 to C10 of the DAC control logic unit respectively, and meanwhile, the ends C1 to C10 of the internal clock generation unit are correspondingly connected with the ends C1 to C10 of the asynchronous delay logic unit respectively; the CNi end and the CPi end of the DAC control logic unit are respectively connected with the CNi input end and the CPi input end of the asynchronous delay logic unit, and the external reference voltage Vref is connected with the Vref input end of the DAC control logic unit; the outputs S2-S10 of the asynchronous delay logic unit are connected to the corresponding inputs S2-S10, and the V _ CLC output is connected to the V _ CLC input of the operational amplifier type selection module.

6. A multimode selective analog-to-digital converter as in claim 1, characterized in that: the first delay selector and the second delay selector both adopt three identical delays.

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