CN112448721A

CN112448721A - Low-power consumption comparator with low delay distortion characteristic of self-biasing circuit

Info

Publication number: CN112448721A
Application number: CN201910805369.2A
Authority: CN
Inventors: 徐江涛; 史晓琳; 聂凯明; 高静
Original assignee: Tianjin University Marine Technology Research Institute
Current assignee: Tianjin University Marine Technology Research Institute
Priority date: 2019-08-29
Filing date: 2019-08-29
Publication date: 2021-03-05
Anticipated expiration: 2039-08-29
Also published as: CN112448721B

Abstract

A low-power consumption comparator with a self-bias circuit and low delay distortion characteristic comprises 10 MOSFET transistors M1-M10, two capacitors CP and CN, and six switches SW 1-SW 6; the transistors M1-M4 are input stages of the comparator, the transistors M5 and M6 are current limiters of the input stages of the comparator, and the transistors M7-M10 are bias stages of the comparator. The gates of transistors M5 and M6 are connected to M7 and M10 in the bias stage, so that the current flowing through M5, M6 is a certain value. The gates of the transistors M8, M9 are connected to the gates of the transistors M5, M6, M7 and M10, thereby forming a current mirror structure that can effectively limit the current through the input stage. The comparator can effectively realize high conversion precision, is suitable for asynchronous ADC, can ensure the precision of data used for recording digital signals and time stamps used for generating the digital signals in the ADC, and enlarges the use occasions of the ADC.

Description

Low-power consumption comparator with low delay distortion characteristic of self-biasing circuit

Technical Field

The invention belongs to the field of analog integrated circuits, and particularly relates to a low-power-consumption comparator with a self-bias circuit and a low-delay distortion characteristic.

Background

An ADC converts an analog input, such as a voltage or current, to a digital output, which may be a digital signal. In a typical linear ADC, the lowest and highest values of the digital code it generates may be determined by the maximum and minimum values of the input analog signal. The input analog signal is limited by the high and low operating voltages of the ADC. The intermediate analog input signal is linearly mapped and quantized by the ADC into a digital signal. In a conventional ADC, an analog input signal is captured by a Digital-to-analog converter (DAC).

The output of the DAC is coupled to a clock comparator, wherein the clock comparator compares at a particular time according to a clock signal. The clock comparator is polled at a particular time within the clock cycle to determine whether the input signal is greater than or less than a predetermined signal. The comparison process continues according to the result of the clock comparator.

In a conventional ADC, an analog input signal is sampled into a digital-to-analog converter (DAC). The output of the DAC is coupled to a clock comparator, wherein the clock comparator compares at a particular time according to a clock signal. The clock comparator is polled at a particular time within the clock cycle to determine whether the input signal is greater than or less than a predetermined signal. The comparison process continues according to the result of the clock comparator.

In an asynchronous ADC, the analog input signal is not sampled as in a conventional ADC, where the input signal is sampled at a particular time. In an asynchronous ADC, the analog input is compared to a reference signal, which may be stationary or continuous. The stationary reference comprises a dc reference signal and the continuous reference comprises an ac reference signal. The comparator in an asynchronous ADC must operate in a continuous mode, which means that it produces an output on an input signal that is equal to the reference signal, without the need for a clock to determine when sampling occurs. To achieve an accurate analog-to-digital conversion version, the two tuples of the number and the time stamp generated by the analog-to-digital converter must be accurate. Any delay of the comparator will result in an error in the analog to digital conversion.

Fig. 1 is a schematic diagram of a conventional low power comparator. The operating voltage of the comparator is GND to VDD. The differential inputs Vinp and Vinn are respectively a positive input end and a negative input end of the comparator, and the differential outputs Voutp and Voutn are respectively a positive output end and a negative output end of the comparator. When the positive input voltage is greater than the negative input voltage, the comparator flips, i.e., the positive output voltage Voutp approaches VDD, and the negative output voltage Voutn may approach GND.

The comparator consists of four transistors M1-M4, sources of M1 and M3 of the transistors are connected to VDD, and sources of M2 and M4 of the transistors are connected to GND. Such conventional comparators have several disadvantages: the comparator does not implement a full differential because it does not have any common node or virtual ground. Also, the leakage current through the comparator is a strong function of the difference between VDD and GND and the magnitude of the voltage transitions at the inputs Vinp and Vinn. In addition, the comparator is sensitive to common mode voltage variations between the voltages at the inputs. Due to these disadvantages, the delay distortion of the comparator is high and the asynchronous ADC is not suitable. Therefore, the patent proposes a low power consumption comparator with a low delay distortion characteristic of a self-bias circuit, thereby effectively realizing high conversion precision.

Disclosure of Invention

Aiming at the problems in the prior art, the invention provides a low-power-consumption comparator with a self-bias circuit and a low delay distortion characteristic, which does not need to provide bias voltage externally, and has a common-mode node and a virtual ground, so that the delay distortion of the comparator is favorably reduced, and the high conversion precision is effectively realized.

A low-power consumption comparator with a self-bias circuit and low-delay distortion characteristic is shown in figure 2 and comprises 10 MOSFET transistors M1-M10, two capacitors CP and CN and six switches SW 1-SW 6, wherein M1, M3, M5, M7 and M8 are P-type MOSFETs, and M2, M4, M6, M9 and M10 are N-type MOSFETs. The specific connection relationship is as follows: the source of M5 and the source of M7 are both connected with a power supply VDD, the grid of M5 is connected with the grid of M7, and the drain of M5 is connected with the sources of M1 and M3; the drain of M3 is connected with the drain of M4 and serves as the positive output Voutp of the comparator, and the gate of M3 is connected with the gate of M4; the source electrode of M4 and the drain electrode of M2 are both connected with the drain electrode of M6; the drain of the M1 is connected with the drain of the M2 and serves as a negative output Voutn of the comparator, and the gate of the M1 is connected with the gate of the M2; the source of M6 and the source of M10 are both connected with GND; the gate of M8 is connected with the gate of M9 and with the gates of M5, M6, M7 and M10; the drain electrode of the M8 is connected with the drain electrode of the M9; the switch SW1 is bridged between the drain and the gate of M3; the switch SW2 is bridged between the drain and the gate of M1; a comparator positive input voltage Vinp is connected to the left plate of the capacitor CP through a switch SW3, and a comparator common mode voltage VCM is connected to the left plate of the capacitor CP through a switch SW 4; the right plate of the capacitor CP is connected to the gate of M1; the comparator negative input voltage Vinn is connected to the right plate of the capacitor CN through a switch SW5, and the comparator common mode voltage VCM is connected to the left plate of the capacitor CN through a switch SW 6; the right plate of capacitor CN is connected to the gate of M3.

A low-power consumption comparator with a self-bias circuit and low delay distortion characteristic specifically works according to the following principle: the transistors M1-M4 are input stages of the comparator, the transistors M5 and M6 are current limiters of the input stages of the comparator, and the transistors M7-M10 are bias stages of the comparator. The gates of transistors M5 and M6 are connected to M7 and M10 in the bias stage so that the current through M5, M6 is a certain value, which is related to the width-to-length ratio of M7-M10. The gates of the transistors M8, M9 are connected to the gates of the transistors M5, M6, M7 and M10, thereby forming a current mirror structure that can effectively limit the current through the input stage. ϕ 1 and ϕ 2 are two non-overlapping clocks. When ϕ 1 is high, SW1, SW2, SW4, SW6 are closed and the common mode voltage VCM is picked up on the left plate of capacitor CP and the right plate of capacitor CN, respectively. The common mode voltage of the differential inverter is sampled to the right plate of capacitor CP and the left plate of capacitor CN through closed SW1 and SW2, respectively. In this process, any offset due to mismatch across the input stage is eliminated, thereby achieving self-biasing of the comparator. When ϕ 2 is high, switches SW3 and SW5 are in a closed state and the other switches are in an open state, which serves to implement the comparator function. When voltages Vinp and Vinn are equal to common-mode voltage VCM, the output voltage is equal to common-mode voltage VCM. When the input voltages Vinp and Vinn are not equal to the common-mode voltage VCM, the output voltage fluctuates centered on the common-mode voltage VCM.

A low power consumption comparator with a low delay distortion characteristic of a self-bias circuit to effectively realize high conversion accuracy. The accuracy of the doublet generated by the ADC, namely the data for recording the digital signal and the timestamp for generating the digital signal, is ensured, and the use occasion of the ADC is further expanded.

Drawings

FIG. 1 is a schematic diagram of a conventional low power comparator circuit;

fig. 2 is a low power consumption comparator with low delay distortion characteristic of the self-bias circuit according to the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, a detailed description of the embodiments of the present invention will be given below with reference to examples. In this example, M1, M3, M5, M7, M8 are PMOS transistors, M2, M4, M6, M9, M10 are NMOS transistors. The specific relationship of the width-length ratio of each transistor in the comparator is as follows: M5/M7= M6/M10=2 × M1/M8=2 × M3/M8=2 × M2/M9=2 × M4/M9. The gate length of each MOS tube is 180 nm; m5, M7 and M8 grid width is 1 um; m1, M3 gate width is 500 nm; m6, M9 and M10 gate widths of 700 nm; m2 and M4 gate width is 350 nm. Capacitors CP and CN each have a capacitance of 200 fF. The periods of the two non-overlapping clocks ϕ 1 and ϕ 2 are 200ns, and the duty ratio is 50%. The common-mode voltage VCM is equal to the arithmetic mean of Vinp and Vinn. The current flowing through the branch formed by the transistors M1 and M2 is half of the current flowing through the transistors M5 and M6, and the other half flows through the branch formed by the transistors M3 and M4. When Vinp is greater than Vinn, transistor M2 gradually turns on more than transistor M1, thereby causing the output voltage Voutn to decrease. Similarly, transistor M3 turns on more gradually than transistor M4, thereby making the output voltage Voutp higher. The total average current of the comparator is 1uA, and the average power is 3.3 uW.

Claims

1. A low power consumption comparator with a low delay distortion characteristic of a self-bias circuit, characterized by: the power supply comprises 10 MOSFET transistors M1-M10, two capacitors CP and CN and six switches SW 1-SW 6, wherein M1, M3, M5, M7 and M8 are P-type MOSFETs, and M2, M4, M6, M9 and M10 are N-type MOSFETs; the source of M5 and the source of M7 are both connected with a power supply VDD, the grid of M5 is connected with the grid of M7, and the drain of M5 is connected with the sources of M1 and M3; the drain of M3 is connected with the drain of M4 and serves as the positive output Voutp of the comparator, and the gate of M3 is connected with the gate of M4; the source electrode of M4 and the drain electrode of M2 are both connected with the drain electrode of M6; the drain of the M1 is connected with the drain of the M2 and serves as a negative output Voutn of the comparator, and the gate of the M1 is connected with the gate of the M2; the source of M6 and the source of M10 are both connected with GND; the gate of M8 is connected with the gate of M9 and with the gates of M5, M6, M7 and M10; the drain electrode of the M8 is connected with the drain electrode of the M9; the switch SW1 is bridged between the drain and the gate of M3; the switch SW2 is bridged between the drain and the gate of M1; a comparator positive input voltage Vinp is connected to the left plate of the capacitor CP through a switch SW3, and a comparator common mode voltage VCM is connected to the left plate of the capacitor CP through a switch SW 4; the right plate of the capacitor CP is connected to the gate of M1; the comparator negative input voltage Vinn is connected to the right plate of the capacitor CN through a switch SW5, and the comparator common mode voltage VCM is connected to the left plate of the capacitor CN through a switch SW 6; the right plate of capacitor CN is connected to the gate of M3.

2. A low power consumption comparator with a low delay distortion characteristic of a self-bias circuit as claimed in claim 1, wherein: the specific working principle is as follows: transistors M1-M4 are input stages of the comparator, two transistors M5 and M6 are current limiters of the input stages of the comparator, and M7-M10 are bias stages of the comparator; the gates of the transistors M5 and M6 are connected to M7 and M10 in the bias stage, so that the current flowing through M5 and M6 is a certain value, and the current is related to the width-to-length ratio of M7-M10; the gates of the transistors M8 and M9 are connected to the gates of the transistors M5, M6, M7 and M10, so that a current mirror structure is formed, and the current passing through the input stage can be effectively limited; ϕ 1 and ϕ 2 are two non-overlapping clocks; when ϕ 1 is high, SW1, SW2, SW4 and SW6 are closed, and the common mode voltage VCM is respectively collected to the left plate of the capacitor CP and the right plate of the capacitor CN; the common mode voltage of the differential inverter is sampled to the right plate of capacitor CP and the left plate of capacitor CN through closed SW1 and SW2, respectively; in the process, any offset caused by mismatch at two sides of the input stage is eliminated, so that the self-bias of the comparator is realized; when ϕ 2 is high, switches SW3 and SW5 are in a closed state, and the other switches are in an open state, and at this time, function as a comparator is realized; when voltages Vinp and Vinn are equal to the common-mode voltage VCM, the output voltage is equal to the common-mode voltage VCM; when the input voltages Vinp and Vinn are not equal to the common-mode voltage VCM, the output voltage fluctuates centered on the common-mode voltage VCM.