CN116032217A - Oscillator structure and analog-to-digital conversion system comprising same - Google Patents
Oscillator structure and analog-to-digital conversion system comprising same Download PDFInfo
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- CN116032217A CN116032217A CN202211664152.2A CN202211664152A CN116032217A CN 116032217 A CN116032217 A CN 116032217A CN 202211664152 A CN202211664152 A CN 202211664152A CN 116032217 A CN116032217 A CN 116032217A
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Abstract
The application relates to the field of integrated circuits and discloses an oscillator structure and an analog-to-digital conversion system comprising the oscillator structure, wherein the oscillator structure comprises: the first input end of the comparator is connected with one end of the first capacitor and the first power end and is connected with the ground end through a switch; the reference voltage generation circuit comprises a first resistor, wherein one end of the first resistor is connected with the second power supply end and provides reference voltage; the voltage feedback loop comprises an operational amplifier, a second resistor and a second capacitor, wherein the first input end of the operational amplifier receives the reference voltage, the output end of the operational amplifier is connected with the second input end of the comparator, one end of the second resistor is connected with the second input end of the operational amplifier, the other end of the second resistor is connected with the first input end of the comparator, one end of the second capacitor is connected with the second input end of the operational amplifier, and the other end of the second capacitor is connected with the second input end of the comparator. The method and the device can eliminate delay and offset of the comparator and realize high precision with smaller power consumption.
Description
Technical Field
The present invention relates generally to the field of integrated circuits, and more particularly, to an oscillator structure and an analog-to-digital conversion system including the same.
Background
High-precision low-power-consumption oscillators are widely integrated in chips such as Micro Controller Units (MCU), analog-to-digital converters (ADC), digital-to-analog converters (DAC), battery Management Systems (BMS), medical front ends and the like. The on-chip integrated oscillator improves the integration level, simplifies the off-chip circuit, and reduces the overall cost and design complexity of the application system. High precision, low power consumption oscillators are required for many applications such as timers, power detection systems, etc. The oscillator requires higher accuracy to achieve an accurate ADC sampling rate or accurate timing. While many battery powered systems require lower power consumption to extend service life.
RC oscillators are widely used to implement oscillators below tens of MHz. The delay and offset of the comparator in conventional RC oscillator structures limit the accuracy of the output clock. To reduce the delay, the comparator requires a large power consumption.
Therefore, achieving a high-precision low-power-consumption oscillator is a problem that needs to be solved in the art.
Disclosure of Invention
An object of the embodiments of the present invention is to provide an oscillator structure and an analog-to-digital conversion system including the same, which can eliminate the influence of delay and offset of a comparator and realize high accuracy with less power consumption.
In one aspect, the present application discloses an oscillator structure comprising:
the first input end of the comparator is connected with one end of the first capacitor and the first power end and is connected with the ground end through a switch, and the other end of the first capacitor is connected with the ground end;
the reference voltage generation circuit comprises a first resistor, wherein one end of the first resistor is connected with a second power supply end and provides reference voltage, and the other end of the first resistor is connected with the ground end; and
the voltage feedback loop comprises an operational amplifier, a second resistor and a second capacitor, wherein a first input end of the operational amplifier receives the reference voltage, an output end of the operational amplifier is connected with a second input end of the comparator, one end of the second resistor is connected with the second input end of the operational amplifier, the other end of the second resistor is connected with the first input end of the comparator, one end of the second capacitor is connected with the second input end of the operational amplifier, and the other end of the second capacitor is connected with the second input end of the comparator.
In a preferred embodiment, the oscillator structure further includes a third resistor, the reference voltage generating circuit further includes a fourth resistor, one end of the third resistor is connected to a voltage source, the other end of the third resistor is connected to one end of the first capacitor and the first input end of the comparator, one end of the fourth resistor is connected to the voltage source, and the other end of the fourth resistor is connected to one end of the second resistor and the first input end of the operational amplifier.
In a preferred embodiment, the oscillator structure further includes a first current source, and the reference voltage generating circuit further includes a second current source, the first current source being connected to one end of the first capacitor and the first input terminal of the comparator, and the second current source being connected to one end of the first resistor and the first input terminal of the operational amplifier.
In a preferred embodiment, the method further comprises: when the voltage of the output end of the comparator jumps from high level to low level, a fast signal is provided so that the power of the comparator is increased.
In a preferred embodiment, the comparator comprises: first to eleventh transistors, wherein:
the sources of the first to fourth transistors are connected with a voltage source, the gates of the first and second transistors are connected with the drain of the second transistor and the drain of the fifth transistor, the gates of the third and fourth transistors are connected with the drain of the third transistor and the drain of the sixth transistor, and the gates of the sixth and fifth transistors are respectively the first and second input ends of the comparator;
the drain electrode of the first transistor, the drain electrode and the grid electrode of the seventh transistor and the grid electrode of the eighth transistor are connected, and the drain electrodes of the fourth transistor and the eighth transistor are connected and serve as the output end of the comparator; and
the sources of the fifth and sixth transistors are connected with the drains of the ninth and tenth transistors, the gates of the ninth and tenth transistors are connected with a bias voltage, the source of the tenth transistor is connected with the drain of the eleventh transistor, the gate of the eleventh transistor is connected with the fast signal, and the sources of the seventh, eighth, ninth and eleventh transistors are connected with a ground terminal.
In a preferred embodiment, when the voltage at the output terminal of the comparator transitions from a high level to a low level, the fast signal transitions to a high level, so that the eleventh transistor is turned on, and the ninth and tenth transistors supply tail currents, thereby increasing the power of the comparator.
In a preferred embodiment, the fast signal is a transient pulse signal.
In a preferred embodiment, the switch is controlled in dependence on the output of the comparator.
In a preferred embodiment, the method further comprises: and the trigger is connected with the output end of the comparator.
In another aspect the application discloses an analog to digital conversion system comprising an oscillator structure according to the previous description.
Compared with the prior art, the oscillator structure and the analog-to-digital conversion system comprising the oscillator structure have at least the following differences and effects:
1, a voltage feedback loop is added, and the delay from low level to high level of the comparator can be eliminated, so that the power consumption of the comparator is small.
2, the comparator fast mode is added, and the influence of the delay from high level to low level on the clock precision is obviously reduced.
And 3, the power consumption of the voltage feedback loop is smaller. The overall power consumption of the oscillator is significantly reduced compared to conventional arrangements.
In the present application, a number of technical features are described in the specification, and are distributed in each technical solution, which makes the specification too lengthy if all possible combinations of technical features (i.e. technical solutions) of the present application are to be listed. In order to avoid this problem, the technical features disclosed in the above summary of the present application, the technical features disclosed in the following embodiments and examples, and the technical features disclosed in the drawings may be freely combined with each other to constitute various new technical solutions (these technical solutions are all regarded as being already described in the present specification) unless such a combination of technical features is technically impossible. For example, in one example, feature a+b+c is disclosed, in another example, feature a+b+d+e is disclosed, and features C and D are equivalent technical means that perform the same function, technically only by alternative use, and may not be adopted simultaneously, feature E may be technically combined with feature C, and then the solution of a+b+c+d should not be considered as already described because of technical impossibility, and the solution of a+b+c+e should be considered as already described.
Drawings
Fig. 1 is a schematic structural diagram of an oscillator structure in one embodiment of the present application.
Fig. 2 is a schematic diagram of a comparator in an embodiment of the present application.
Fig. 3 is a schematic structural diagram of an oscillator structure according to another embodiment of the present application.
Detailed Description
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present application. However, it will be understood by those skilled in the art that the claimed invention may be practiced without these specific details and with various changes and modifications from the embodiments that follow.
For the purpose of making the objects, technical solutions and advantages of the present application more apparent, embodiments of the present application will be described in further detail below with reference to the accompanying drawings.
An embodiment of the present application discloses an oscillator structure, the oscillator structure includes: a comparator, a reference voltage generation circuit, a voltage feedback loop. The first input end of the comparator is connected with one end of the first capacitor and the first power end and is connected with the ground end through the switch, and the other end of the first capacitor is connected with the ground end. The reference voltage generating circuit comprises a first resistor, one end of the first resistor is connected with the second power end and provides reference voltage, and the other end of the first resistor is connected with the ground end. The voltage feedback loop comprises an operational amplifier, a second resistor and a second capacitor, wherein the first input end of the operational amplifier receives the reference voltage, the output end of the operational amplifier is connected with the second input end of the comparator, one end of the second resistor is connected with the second input end of the operational amplifier, the other end of the second resistor is connected with the first input end of the comparator, one end of the second capacitor is connected with the second input end of the operational amplifier, and the other end of the second capacitor is connected with the second input end of the comparator. The oscillator structure can eliminate the influence of delay and offset of the comparator, and can realize high precision with smaller power consumption.
Fig. 1 shows a schematic diagram of an oscillator structure in one embodiment, the oscillator structure comprising: an RC circuit, a comparator 101, a reference voltage generation circuit 102, a voltage feedback loop 103. The RC circuit comprises a first capacitor C1 and a third resistor R3. The voltage feedback loop 103 includes an operational amplifier 104, a second resistor R2, and a second capacitor C2. The reference voltage generation circuit 102 includes a first resistor R1 and a fourth resistor R4. Wherein a first input terminal (e.g., a positive input terminal) of the comparator 101 is connected to one end of the first capacitor C1 and one end of the third resistor R3, the other end of the third resistor R3 is connected to the voltage source VDD, and the first input terminal of the comparator 101 is connected to the ground terminal through the switch S, and the other end of the first capacitor C1 is connected to the ground terminal. One end of the first resistor R1 is connected to one end of the fourth resistor R4 and provides a reference voltage α×vdd, the other end of the first resistor R1 is connected to the ground, and the other end of the fourth resistor R4 is connected to the voltage source VDD. It is understood that the reference voltage α×vdd depends on the proportional relationship between the first resistor R1 and the fourth resistor R4.
The first input end (for example, a positive input end) of the operational amplifier 104 receives the reference voltage α×vdd, the output end of the operational amplifier 104 is connected to the second input end (for example, a negative input end) of the comparator 101, one end of the second resistor R2 is connected to the second input end (for example, a negative input end) of the operational amplifier 104, the other end of the second resistor R2 is connected to the first input end of the comparator 101, one end of the second capacitor C2 is connected to the second input end of the operational amplifier 104, and the other end of the second capacitor C2 is connected to the second input end of the comparator 101.
In one embodiment, the switch S is controlled to be turned on and off according to the output of the comparator 101. For example, when the output terminal of the comparator 101 is at a high level, the switch S is closed, so that the voltage at one end of the first capacitor C1 is pulled down to a low level. When the output terminal of the comparator 101 is at a high level, the switch S is turned off, so that the one-terminal voltage of the first capacitor C1 is charged to a high level.
The negative input of a comparator (e.g., comparator 101) in a conventional oscillator configuration is a fixed reference voltage (e.g., VDD). Therefore, the inverting point of the ramp voltage at the positive input of the comparator 101 is affected by the offset and delay of the comparator, reducing the frequency accuracy of the oscillator. The present solution adds a voltage feedback loop 102 on the basis of a conventional RC oscillator. In this scheme, the negative input of comparator 101 is connected to the output Vc of feedback loop 103. Vc is controlled by the average value of the ramp voltage, and when the average value of the ramp voltage is larger than alpha, VDD, vc becomes lower, and the amplitude of the ramp voltage becomes lower; conversely, when the average value of the ramp voltage is smaller than α×vdd, vc becomes high and the ramp voltage amplitude becomes high. Eventually making the average value of the ramp voltage equal to α×vdd. For comparator imbalance, the comparator inversion point=vc+vos (assuming Vos is positive), the ramp voltage inversion point becomes high, so the ramp voltage average becomes high, the feedback loop makes Vc low, and eventually the magnitude of the ramp voltage does not change, and the oscillator frequency does not change. For low- > high delay when the comparator transitions low to high, if the delay becomes large, the ramp voltage inversion point becomes high, the average value becomes large, the feedback loop 103 makes Vc low, and finally the ramp voltage amplitude is unchanged, and the oscillator frequency is unchanged. Oscillator frequency errors due to low- > high delay of the comparator low-to-high transitions and comparator offset can be eliminated.
In one embodiment, the oscillator structure further comprises providing a fast signal such that the power of the comparator increases when the output voltage of the comparator 101 transitions from a high level to a low level.
Specifically, referring to fig. 2, the comparator includes: the first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, the eighth transistor M8, the ninth transistor M9, the tenth transistor M10, and the eleventh transistor M11.
Wherein the sources of the first transistor M1, the second transistor M2, the third transistor M3 and the fourth transistor M4 are connected with the voltage source VDD, the gates of the first transistor M1 and the second transistor M2 are connected with the drain of the second transistor M2 and the drain of the fifth transistor M5, the gates of the third transistor M3 and the fourth transistor M4 are connected with the drain of the third transistor M3 and the drain of the sixth transistor M6, the gates of the fifth transistor M5 and the sixth transistor M6 are respectively the first input end and the second input end of the comparator 101, respectively, for receiving the differential input signal V INN 、V INP . The drain of the first transistor M1, the drain and gate of the seventh transistor M7, and the gate of the eighth transistor M8 are connected, the drains of the second transistor M2 and the eighth transistor M8 are connected and serve as the output terminal of the comparator 101 for outputting the voltage V OUT . The sources of the fifth transistor M5 and the sixth transistor M6 are connected with the drains of the ninth transistor M9 and the tenth transistor M10, and the gates of the ninth transistor M9 and the tenth transistor M10 are connected with the bias voltage V IB The source of the tenth transistor M10 is connected to the drain of the eleventh transistor M11, the gate of the eleventh transistor M11 is connected to the fast signal, and the sources of the seventh transistor M7, the eighth transistor M8, the ninth transistor M9, and the eleventh transistor M11 are all connected to ground.
The high- > low delay of the high-level transition of the comparator 101 to the low-level affects the accuracy of the clock output, so the comparator 101 of this embodiment designs the fast mode. When the output voltage of the comparator 101 is low, the fast signal is low, and the tail current is supplied from the ninth transistor M9. Then, when the output terminal voltage of the comparator 101 transitions from a high level to a low level, the fast signal transitions to a high level, so that the eleventh transistor M11 is turned on, and the tenth transistor M10 supplies a tail current, so that the tail current of the comparator 101 increases, thereby increasing the power of the comparator 101. At this time, the delay of the comparator 101 becomes small, so the high- > low delay is significantly reduced.
In one embodiment, the fast signal is a transient pulse signal, that is, the fast signal is high for a short period of time. Since fast mode is enabled only for a period in which the output of the comparator 101 is high (about the delay of the comparator high- > low), the duty cycle is negligible throughout the clock cycle, so the overall power consumption is not increased.
It should be noted that the present embodiment adds transistors M10 and M11 based on the conventional comparator structure. When fast is 0, the comparator tail current is provided by M9, which is small to save power consumption. When a smaller delay is required (i.e. a High- > Low converter in the oscillator scheme), fast becomes High, the switch tube M11 is turned on, and the M10 provides a larger current, so that the delay of the comparator becomes obviously smaller. In this scheme, fast is high for a short time, so the average power consumption of the comparator is low.
In one embodiment, the oscillator structure further comprises a flip-flop 105, the flip-flop 105 being connected to the output of the comparator 101. The flip-flop 101 may hold the output signal of the comparator 101. The flip-flop 105 is triggered on the rising edge of the comparator output and the output toggles so that the clock duty cycle of the flip-flop output is 50%.
Fig. 3 shows a schematic diagram of an oscillator structure in another embodiment, the oscillator structure comprising: a first current source I1, a first capacitor C1, a comparator 301, a reference voltage generating circuit 302, and a voltage feedback loop 303. The reference voltage generation circuit 302 includes a first resistor R1 and a second current source I2. The voltage feedback loop 303 includes an operational amplifier 304, a second resistor R2, and a second capacitor C2. One end of the first resistor R1 is connected to the second current source I2 and the first input end (e.g., positive input end) of the operational amplifier 304 and provides the reference voltage I2 x R1, and the other end of the first resistor R1 is connected to the ground. A first input (e.g., a positive input) of the comparator 301 is connected to one end of the first capacitor C1 and the first current source I1, and is connected to the ground through the switch S, and the other end of the first capacitor C1 is connected to the ground. The first input terminal of the operational amplifier 304 receives the reference voltage I2×r1, the output terminal of the operational amplifier 304 is connected to the second input terminal (e.g., negative input terminal) of the comparator 301, one terminal of the second resistor R2 is connected to the second input terminal (e.g., negative input terminal) of the operational amplifier 304, the other terminal of the second resistor R2 is connected to the first input terminal of the comparator 301, one terminal of the second capacitor C2 is connected to the second input terminal of the operational amplifier 304, and the other terminal of the second capacitor C2 is connected to the second input terminal of the comparator 301. The current values of the current sources I1 and I2 may be the same or different, for example, may be proportional. The current sources I1 and I2 generally require to be generated from the same source in a proportional relationship such that the effects like temperature coefficients can be counteracted.
The negative input of the comparator 301 is connected to the output Vc of the feedback loop 303, where Vc is controlled by the average value of the ramp voltage, so that the low- > high delay of the low-level transition of the comparator to the high-level and the oscillator frequency error caused by the offset of the comparator can be eliminated. Furthermore, the high- > low delay of the high-to-low transition of comparator 301 can be significantly reduced due to the addition of fast mode.
In another aspect the application discloses an analog to digital conversion system comprising an oscillator structure according to the previous description. The ADC comprises a Multiplexer (MUX), an analog-to-digital converter (ADC), a reference voltage generator, an amplifier (PGA), a digital filter and interface module, a temperature sensor and an oscillator structure, wherein the multiplexer, the amplifier, the analog-to-digital converter, the digital, the oscillator filter and the interface are sequentially connected, the reference voltage generator is connected with the analog-to-digital converter, the oscillator is connected with the analog-to-digital converter, and the temperature sensor is connected with the digital filter and the interface module.
It should be noted that in the present patent application, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element. In the present patent application, if it is mentioned that an action is performed according to an element, it means that the action is performed at least according to the element, and two cases are included: the act is performed solely on the basis of the element and is performed on the basis of the element and other elements. Multiple, etc. expressions include 2, 2 times, 2, and 2 or more, 2 or more times, 2 or more.
This specification includes combinations of the various embodiments described herein. Separate references to embodiments (e.g., "one embodiment" or "some embodiments" or "preferred embodiments") do not necessarily refer to the same embodiment; however, unless indicated as mutually exclusive or as would be apparent to one of skill in the art, the embodiments are not mutually exclusive. It should be noted that the term "or" is used in this specification in a non-exclusive sense unless the context clearly indicates otherwise or requires otherwise.
All documents mentioned in the present specification are considered to be included in the disclosure of the present application as a whole, so that they may be regarded as a basis for modification if necessary. Furthermore, it should be understood that the foregoing description is only of the preferred embodiments of the present invention and is not intended to limit the scope of the present invention. Any modification, equivalent replacement, improvement, or the like, which is within the spirit and principles of one or more embodiments of the present disclosure, is intended to be included within the scope of one or more embodiments of the present disclosure.
Claims (10)
1. An oscillator structure, comprising:
the first input end of the comparator is connected with one end of the first capacitor and the first power end and is connected with the ground end through a switch, and the other end of the first capacitor is connected with the ground end;
the reference voltage generation circuit comprises a first resistor, wherein one end of the first resistor is connected with a second power supply end and provides reference voltage, and the other end of the first resistor is connected with the ground end; and
the voltage feedback loop comprises an operational amplifier, a second resistor and a second capacitor, wherein a first input end of the operational amplifier receives the reference voltage, an output end of the operational amplifier is connected with a second input end of the comparator, one end of the second resistor is connected with the second input end of the operational amplifier, the other end of the second resistor is connected with the first input end of the comparator, one end of the second capacitor is connected with the second input end of the operational amplifier, and the other end of the second capacitor is connected with the second input end of the comparator.
2. The oscillator structure according to claim 1, further comprising a third resistor, wherein the reference voltage generating circuit further comprises a fourth resistor, one end of the third resistor is connected to a voltage source, the other end of the third resistor is connected to one end of the first capacitor and the first input terminal of the comparator, one end of the fourth resistor is connected to the voltage source, and the other end of the fourth resistor is connected to one end of the second resistor and the first input terminal of the operational amplifier.
3. The oscillator structure according to claim 1, further comprising a first current source, the reference voltage generation circuit further comprising a second current source, the first current source connecting one end of the first capacitor and a first input of the comparator, the second current source connecting one end of the first resistor and a first input of the operational amplifier.
4. The oscillator structure according to claim 1, characterized by further comprising: when the voltage of the output end of the comparator jumps from high level to low level, a fast signal is provided so that the power of the comparator is increased.
5. The oscillator structure according to claim 4, wherein the comparator comprises: first to eleventh transistors, wherein:
the sources of the first to fourth transistors are connected with a voltage source, the gates of the first and second transistors are connected with the drain of the second transistor and the drain of the fifth transistor, the gates of the third and fourth transistors are connected with the drain of the third transistor and the drain of the sixth transistor, and the gates of the sixth and fifth transistors are respectively the first and second input ends of the comparator;
the drain electrode of the first transistor, the drain electrode and the grid electrode of the seventh transistor and the grid electrode of the eighth transistor are connected, and the drain electrodes of the fourth transistor and the eighth transistor are connected and serve as the output end of the comparator; and
the sources of the fifth and sixth transistors are connected with the drains of the ninth and tenth transistors, the gates of the ninth and tenth transistors are connected with a bias voltage, the source of the tenth transistor is connected with the drain of the eleventh transistor, the gate of the eleventh transistor is connected with the fast signal, and the sources of the seventh, eighth, ninth and eleventh transistors are connected with a ground terminal.
6. The oscillator structure according to claim 5, wherein the fast signal transitions to a high level when an output voltage of the comparator transitions from a high level to a low level, so that the eleventh transistor is turned on, and tail currents are supplied from the ninth and tenth transistors, thereby increasing power of the comparator.
7. The oscillator structure according to claim 5, wherein the fast signal is a transient pulse signal.
8. The oscillator structure according to claim 1, characterized in that the switch is controlled according to an output of the comparator.
9. The oscillator structure according to claim 1, characterized by further comprising: and the trigger is connected with the output end of the comparator.
10. Analog-to-digital conversion system, characterized in that it comprises an oscillator structure according to any of claims 1-9.
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| CN117595879A (en) * | 2023-11-28 | 2024-02-23 | 江苏神州半导体科技有限公司 | Analog-to-digital conversion unit, digital-to-analog conversion unit and signal transmission circuit |
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| CN117595879A (en) * | 2023-11-28 | 2024-02-23 | 江苏神州半导体科技有限公司 | Analog-to-digital conversion unit, digital-to-analog conversion unit and signal transmission circuit |
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