CN113922822A - Analog-to-digital conversion device and battery management system - Google Patents
Analog-to-digital conversion device and battery management system Download PDFInfo
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- CN113922822A CN113922822A CN202111203563.7A CN202111203563A CN113922822A CN 113922822 A CN113922822 A CN 113922822A CN 202111203563 A CN202111203563 A CN 202111203563A CN 113922822 A CN113922822 A CN 113922822A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/124—Sampling or signal conditioning arrangements specially adapted for A/D converters
- H03M1/1245—Details of sampling arrangements or methods
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
- G01R19/25—Arrangements for measuring currents or voltages or for indicating presence or sign thereof using digital measurement techniques
- G01R19/2506—Arrangements for conditioning or analysing measured signals, e.g. for indicating peak values ; Details concerning sampling, digitizing or waveform capturing
- G01R19/2509—Details concerning sampling, digitizing or waveform capturing
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/36—Arrangements for testing, measuring or monitoring the electrical condition of accumulators or electric batteries, e.g. capacity or state of charge [SoC]
- G01R31/3644—Constructional arrangements
- G01R31/3648—Constructional arrangements comprising digital calculation means, e.g. for performing an algorithm
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/36—Arrangements for testing, measuring or monitoring the electrical condition of accumulators or electric batteries, e.g. capacity or state of charge [SoC]
- G01R31/385—Arrangements for measuring battery or accumulator variables
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/36—Arrangements for testing, measuring or monitoring the electrical condition of accumulators or electric batteries, e.g. capacity or state of charge [SoC]
- G01R31/396—Acquisition or processing of data for testing or for monitoring individual cells or groups of cells within a battery
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/34—Analogue value compared with reference values
- H03M1/36—Analogue value compared with reference values simultaneously only, i.e. parallel type
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Abstract
The present disclosure provides an analog-to-digital conversion apparatus including: the first integration unit is used for receiving an analog input signal and carrying out modulation conversion on the analog input signal to generate a first integration signal; the second integration unit receives the first integration signal and performs modulation conversion on the first integration signal to generate a second integration signal; the quantization unit is used for comparing the second integral signal with the reference signal and generating a digital code stream with analog input signal information based on the second integral signal and the reference signal; and the low-pass filtering unit is used for shaping and filtering out-of-band noise in the digital code stream output by the quantization unit. The present disclosure also provides a battery management system.
Description
Technical Field
The present disclosure relates to an analog-to-digital conversion apparatus and a battery management system.
Background
In the battery management system, analog-to-digital conversion is required to perform analog-to-digital change on the battery voltage or the detection signal so as to obtain a digital signal for digital processing.
In a typical analog-to-digital conversion apparatus, the output of the analog-to-digital conversion apparatus may receive some interference, and thus the output of the analog-to-digital conversion apparatus may not be stable. Although the interference can be eliminated by a filter such as a low-pass filter in the related art, the effect of the filtering method using only a low-pass filter is not particularly preferable in the related art, and a conversion error or the like may not be eliminated.
In the present disclosure, a novel analog-to-digital converter with low noise and low power consumption can be realized by improving the analog-to-digital conversion device itself and the filter part.
Disclosure of Invention
In order to solve one of the above technical problems, the present disclosure provides an analog-to-digital conversion apparatus and a battery management system.
According to an aspect of the present disclosure, an analog-to-digital conversion apparatus includes:
a first integration unit for receiving an analog input signal and performing modulation conversion on the analog input signal to generate a first integrated signal;
a second integration unit that receives the first integration signal and performs modulation conversion on the first integration signal to generate a second integration signal;
a quantization unit for comparing a second integrated signal and a reference signal and generating a digital code stream with analog input signal information based on the second integrated signal and the reference signal;
the low-pass filtering unit is used for shaping and filtering out-of-band noise in the digital code stream output by the quantization unit; and
and the random jitter filtering unit is used for filtering the shaped and filtered signals of the low-pass filtering unit so as to eliminate random jitter data existing in the shaped and filtered signals and generate digital output signals corresponding to the analog input signals.
According to at least one embodiment of the present disclosure, the random jitter filtering unit is configured to process a plurality of pieces of history data in the shaped filtered signal and generate a digital output signal corresponding to the analog input signal based on the plurality of pieces of history data, wherein the random jitter filtering unit removes random jitter data in the plurality of pieces of history data and generates the digital output signal based on the history data not containing random jitter, or the random jitter filtering unit reduces the influence of random jitter in the plurality of pieces of history data to generate the digital output signal.
According to at least one embodiment of the present disclosure, the random jitter filtering unit is configured to eliminate random jitter in data of m significant bits of the N significant bits in the shaped filtered signal, where N is greater than or equal to 2 and m is greater than or equal to 1 and less than or equal to N.
According to at least one embodiment of the present disclosure, the random jitter filtering unit is configured to eliminate random jitter in the data of each of the N significant bits in the shaped filtered signal.
According to at least one embodiment of the present disclosure, in the first integrating unit, one end of a first switch is connected to a first analog input signal terminal, the other end of the first switch is connected to one end of a first sampling capacitor, the other end of the first sampling capacitor is connected to the positive input terminal of the first operational amplifier via a second switch, one end of a third switch is connected to the first analog signal input terminal, the other end of the third switch is connected to one end of a second sampling capacitor, the other end of the second sampling capacitor is connected to the negative input terminal of the first operational amplifier via a fourth switch, one end of a fifth switch is connected to the second analog input signal terminal, the other end of the fifth switch is connected to one end of the second sampling capacitor, the other end of the second sampling capacitor is connected to the negative input terminal of the first operational amplifier via a fourth switch, the other end of a seventh switch is connected to the second analog input signal terminal, the other end of the seventh switch is connected to one end of the first sampling capacitor, the other end of the first switch is connected to the positive reference voltage terminal through a seventh switch and is connected to the negative reference voltage terminal through an eighth switch, the other end of the fifth switch is connected to the positive reference voltage terminal through a ninth switch and is connected to the negative reference voltage terminal through a tenth switch, a connection node of the first sampling capacitor and the second switch is connected to the regulated voltage through an eleventh switch, a connection node of the second sampling capacitor and the fourth switch is connected to the regulated voltage through a twelfth switch, a negative output terminal of the first operational amplifier is connected to a positive input terminal thereof through a first integrating capacitor, and a positive output terminal of the first operational amplifier is connected to a negative input terminal thereof through a second integrating capacitor.
According to at least one embodiment of the present disclosure, in the second integration unit, one end of a thirteenth switch is connected to the positive output terminal of the first operational amplifier, the other end of the thirteenth switch is connected to one end of a third sampling capacitor, the other end of the third sampling capacitor is connected to the positive input terminal of the second operational amplifier via a fourteenth switch, the other end of the thirteenth switch is connected to the external voltage via a fifteenth switch, and the other end of the third sampling capacitor is connected to the regulated voltage via a sixteenth switch. One end of the seventeenth switch is connected with the negative output end of the first operational amplifier, the other end of the seventeenth switch is connected with one end of the fourth sampling capacitor, the other end of the fourth sampling capacitor is connected with the negative input end of the second operational amplifier through the eighteenth switch, the other end of the seventeenth switch is connected with external voltage through the nineteenth switch, the other end of the fourth sampling capacitor is connected with regulated voltage through the twentieth switch, the negative output end of the second operational amplifier is connected with the positive input end of the second operational amplifier through the third integrating capacitor, and the positive output end of the second operational amplifier is connected with the negative input end of the second operational amplifier through the fourth integrating capacitor.
According to at least one embodiment of the present disclosure, the first operational amplifier has a structure of:
the source electrode of the first PMOS transistor is connected with the system voltage, the grid electrode of the first PMOS transistor is connected with the control voltage to control the on and off of the first PMOS transistor, the drain electrode of the first PMOS transistor is connected with the source electrode of the second PMOS transistor and the source electrode of the third PMOS transistor, the grid electrode of the second PMOS transistor and the grid electrode of the third PMOS transistor are respectively connected with the positive input end and the negative input end, the drain electrode of the second PMOS transistor and the drain electrode of the third PMOS transistor are respectively connected with the negative input end and the positive input end of the first amplifier, and the negative input terminal and the positive input terminal of the first amplifier are grounded through the first NMOS transistor and the second NMOS transistor respectively, and the grid electrodes of the first NMOS transistor and the second NMOS transistor are connected, the negative output end and the positive output end of the first amplifier are respectively connected to the grid electrodes of the third NMOS transistor and the fourth NMOS transistor, and the source electrodes of the third NMOS transistor and the fourth NMOS transistor are respectively connected with the positive input end and the negative input end of the first amplifier. The drain electrodes of the third NMOS transistor and the fourth NMOS transistor are used as output ends of the operational amplifier, the source electrodes of the fourth PMOS transistor and the fifth PMOS transistor are connected with system voltage, the grid electrodes of the fourth PMOS transistor and the fifth PMOS transistor are connected, the drain electrodes of the fourth PMOS transistor and the fifth PMOS transistor are respectively connected with the negative input end and the positive input end of the second amplifier and respectively connected with the source electrodes of the sixth PMOS transistor and the seventh PMOS transistor, and the grid electrodes of the sixth PMOS transistor and the seventh PMOS transistor are respectively connected with the positive output end and the negative output end of the second amplifier and respectively connected with the drain electrodes of the third NMOS transistor and the fourth NMOS transistor.
According to at least one embodiment of the present disclosure, the second operational amplifier has a structure of:
the source electrode of the first PMOS transistor is connected with the system voltage, the grid electrode of the first PMOS transistor is connected with the control voltage to control the on and off of the first PMOS transistor, the drain electrode of the first PMOS transistor is connected with the source electrode of the second PMOS transistor and the source electrode of the third PMOS transistor, the grid electrode of the second PMOS transistor and the grid electrode of the third PMOS transistor are respectively connected with the positive input end and the negative input end, the drain electrode of the second PMOS transistor and the drain electrode of the third PMOS transistor are respectively connected with the negative input end and the positive input end of the first amplifier, and the negative input terminal and the positive input terminal of the first amplifier are grounded through the first NMOS transistor and the second NMOS transistor respectively, and the grid electrodes of the first NMOS transistor and the second NMOS transistor are connected, the negative output end and the positive output end of the first amplifier are respectively connected to the grid electrodes of the third NMOS transistor and the fourth NMOS transistor, and the source electrodes of the third NMOS transistor and the fourth NMOS transistor are respectively connected with the positive input end and the negative input end of the first amplifier. The drain electrodes of the third NMOS transistor and the fourth NMOS transistor are used as output ends of the operational amplifier, the source electrodes of the fourth PMOS transistor and the fifth PMOS transistor are connected with system voltage, the grid electrodes of the fourth PMOS transistor and the fifth PMOS transistor are connected, the drain electrodes of the fourth PMOS transistor and the fifth PMOS transistor are respectively connected with the negative input end and the positive input end of the second amplifier and respectively connected with the source electrodes of the sixth PMOS transistor and the seventh PMOS transistor, and the grid electrodes of the sixth PMOS transistor and the seventh PMOS transistor are respectively connected with the positive output end and the negative output end of the second amplifier and respectively connected with the drain electrodes of the third NMOS transistor and the fourth NMOS transistor.
According to at least one embodiment of the present disclosure, the quantization unit includes a pre-amplification circuit and a latch, wherein the pre-amplification circuit amplifies an output signal of the second integration unit by a predetermined gain, and the latch latches the signal amplified by the predetermined gain.
According to at least one embodiment of the present disclosure, the digital signal processing device further includes a chopper circuit, the chopper circuit is used for eliminating an offset voltage of the operational amplifier and is connected between the operational amplifier and the integrating capacitor, and the chopper circuit performs twice modulation to modulate the offset voltage to a position of a clock phase frequency.
According to at least one embodiment of the present disclosure, the low-pass filtering unit includes two cascaded stages of digital filters, each of the data filters includes an adder and a register, each new data is added to the previous data by the adder when being input to each data filter, and the added result is held by the register, and then waiting for the next data input, the addition and the holding are periodically performed.
According to at least one embodiment of the present disclosure, the random jitter filtering unit performs filtering processing on each bit of data in N valid bits of the analog-to-digital conversion apparatus, where each bit of data is respectively connected to one random jitter filtering unit.
According to at least one embodiment of the present disclosure, the random jitter filtering unit simultaneously performs filtering processing on m bits of data in N significant bits of the analog-to-digital conversion apparatus, and the m bits of data are connected to one random jitter filtering unit.
According to at least one embodiment of the present disclosure, the random jitter filtering unit receives i pieces of history data, and determines an output signal thereof according to the number of repetitions and/or the variation trend of the input data, where i is greater than or equal to 2.
According to another aspect of the present disclosure, a battery management system includes:
an analog-to-digital conversion apparatus as described above;
the battery voltage acquisition unit is used for acquiring the voltage of the battery/battery pack and providing the acquired voltage signal to the analog-to-digital conversion device;
and the control logic unit is used for receiving the digital signal converted by the analog-to-digital conversion device and generating a driving signal of a charge and discharge switch so as to control the charge and discharge of the battery.
According to at least one embodiment of the present disclosure, the charging and discharging system further includes a charging and discharging current detection resistor, the charging and discharging measurement signal generated by the charging and discharging current detection resistor is provided to the analog-to-digital conversion device and analog-to-digital converted by the analog-to-digital conversion device, and the converted signal is the control logic unit, so that the control logic unit controls the charging and discharging switch according to the charging and discharging measurement signal.
Drawings
The accompanying drawings, which are included to provide a further understanding of the disclosure and are incorporated in and constitute a part of this specification, illustrate exemplary embodiments of the disclosure and together with the description serve to explain the principles of the disclosure.
Fig. 1 shows a schematic diagram of an analog-to-digital conversion apparatus according to an embodiment of the present disclosure.
Fig. 2 shows a circuit diagram of a first stage integration unit according to an embodiment of the present disclosure. Fig. 3 shows a circuit diagram of a second stage integration unit according to an embodiment of the present disclosure.
Fig. 4 shows a circuit diagram of an operational amplifier according to one embodiment of the present disclosure.
Fig. 5 shows a circuit diagram of a quantization unit according to an embodiment of the present disclosure.
Fig. 6 shows a circuit diagram of a clock generation unit according to an embodiment of the present disclosure.
Fig. 7 shows a circuit diagram of a chopper circuit according to one embodiment of the present disclosure.
Fig. 8 shows a circuit diagram of a low-pass filtering unit according to an embodiment of the present disclosure.
Fig. 9 shows a schematic diagram of a battery management system according to one embodiment of the present disclosure.
Detailed Description
The present disclosure will be described in further detail with reference to the drawings and embodiments. It is to be understood that the specific embodiments described herein are for purposes of illustration only and are not to be construed as limitations of the present disclosure. It should be further noted that, for the convenience of description, only the portions relevant to the present disclosure are shown in the drawings.
It should be noted that the embodiments and features of the embodiments in the present disclosure may be combined with each other without conflict. Technical solutions of the present disclosure will be described in detail below with reference to the accompanying drawings in conjunction with embodiments.
Unless otherwise indicated, the illustrated exemplary embodiments/examples are to be understood as providing exemplary features of various details of some ways in which the technical concepts of the present disclosure may be practiced. Accordingly, unless otherwise indicated, features of the various embodiments may be additionally combined, separated, interchanged, and/or rearranged without departing from the technical concept of the present disclosure.
The use of cross-hatching and/or shading in the drawings is generally used to clarify the boundaries between adjacent components. As such, unless otherwise noted, the presence or absence of cross-hatching or shading does not convey or indicate any preference or requirement for a particular material, material property, size, proportion, commonality between the illustrated components and/or any other characteristic, attribute, property, etc., of a component. Further, in the drawings, the size and relative sizes of components may be exaggerated for clarity and/or descriptive purposes. While example embodiments may be practiced differently, the specific process sequence may be performed in a different order than that described. For example, two processes described consecutively may be performed substantially simultaneously or in reverse order to that described. In addition, like reference numerals denote like parts.
When an element is referred to as being "on" or "on," "connected to" or "coupled to" another element, it can be directly on, connected or coupled to the other element or intervening elements may be present. However, when an element is referred to as being "directly on," "directly connected to" or "directly coupled to" another element, there are no intervening elements present. For purposes of this disclosure, the term "connected" may refer to physically, electrically, etc., and may or may not have intermediate components.
For descriptive purposes, the present disclosure may use spatially relative terms such as "below … …," below … …, "" below … …, "" below, "" above … …, "" above, "" … …, "" higher, "and" side (e.g., as in "side wall") to describe one component's relationship to another (other) component as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use, operation, and/or manufacture in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary term "below … …" can encompass both an orientation of "above" and "below". Further, the devices may be otherwise positioned (e.g., rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments and is not intended to be limiting. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. Furthermore, when the terms "comprises" and/or "comprising" and variations thereof are used in this specification, the presence of stated features, integers, steps, operations, elements, components and/or groups thereof are stated but does not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and/or groups thereof. It is also noted that, as used herein, the terms "substantially," "about," and other similar terms are used as approximate terms and not as degree terms, and as such, are used to interpret inherent deviations in measured values, calculated values, and/or provided values that would be recognized by one of ordinary skill in the art.
According to one embodiment of the present disclosure, an analog-to-digital conversion apparatus is provided.
Fig. 1 shows a schematic block diagram of an analog-to-digital conversion apparatus according to an embodiment of the present disclosure. As shown in fig. 1, the analog-to-digital conversion circuit 10 may include an analog modulation section 100, a low-pass filtering unit 200, and a random jitter filtering unit 300.
The analog modulation part 100 may include a first integration unit 110, a second integration unit 120, and a quantization unit 130.
The first integration unit 110 is configured to receive an analog input signal and perform modulation conversion on the analog input signal to generate a first integrated signal.
The second integration unit 120 receives the first integrated signal and performs modulation conversion on the first integrated signal to generate a second integrated signal.
The quantization unit 130 is configured to compare the second integrated signal with the reference signal, and generate a digital code stream with analog input signal information based on the second integrated signal and the reference signal.
The low-pass filtering unit 200 may be configured to shape and filter out-of-band noise in the digital code stream output by the quantization unit 130.
The random jitter filtering unit 300 performs a filtering process on the shaped filtered signal of the low pass filtering unit 200 to remove random jitter data present in the shaped filtered signal and generate a digital output signal corresponding to the analog input signal.
The first integration unit 110 may take the form of a switched capacitor integrator, which according to a preferred example of the present disclosure has the advantage of high time constant accuracy, good temperature characteristics and easy clocking according to the novel switched capacitor integrator, as shown in fig. 2.
As shown in fig. 2, the first integration unit 110 may be composed of a switch, a capacitor, and an operational amplifier.
Wherein one end of the first switch S1-1 is connected to the first analog input signal terminal Vip, the other end is connected to one end of the first sampling capacitor C1, the other end of the first sampling capacitor C1 is connected to the positive input terminal of the first operational amplifier OP1 via the second switch S6-1, one end of the third switch S2-1 is connected to the first analog signal input terminal, the other end is connected to one end of the second sampling capacitor C2, the other end of the second sampling capacitor C2 is connected to the negative input terminal of the first operational amplifier OP1 via the fourth switch S6-2, one end of the fifth switch S1-2 is connected to the second analog input signal terminal Vin, the other end is connected to one end of the second sampling capacitor C2, the other end of the second sampling capacitor C2 is connected to the negative input terminal of the first operational amplifier OP1 via the fourth switch S6-2, the other end of the seventh switch S2-2 is connected to the second analog input signal terminal Vin, and the other end is connected to one end of the first sampling capacitor C1.
The other end of the first switch S11 is connected to the positive reference voltage terminal Vr + via a seventh switch S3-1 and to the negative reference voltage terminal Vr-via an eighth switch S4-1.
The other end of the fifth switch S1-2 is connected to the positive reference voltage terminal Vr + via a ninth switch S3-2 and to the negative reference voltage terminal Vr-via a tenth switch S4-2.
The connection node of the first sampling capacitor C1 and the second switch S6-1 is connected to the regulated voltage Vcmi via an eleventh switch, and the connection node of the second sampling capacitor C2 and the fourth switch S6-2 is connected to the regulated voltage Vcmi via a twelfth switch (the regulated voltage may be determined according to actual conditions).
In addition, the negative output terminal of the first operational amplifier OP1 is connected to the positive input terminal via the first integrating capacitor C3, and the positive output terminal of the first operational amplifier OP1 is connected to the negative input terminal via the second integrating capacitor C4.
With the first integration unit 110, in the first phase of the switch control signal, the integration capacitor in the first integration unit 110 samples the analog input signal through the on and off control of the switch, and in the second phase of the switch control signal, the signal of the integration capacitor in the first integration unit 110 is transmitted to the integration capacitor through the on and off control of the switch, thus periodically operating.
Preferably, the first sampling capacitor and the second sampling capacitor are symmetrical and have equal capacitance values, and the first integrating capacitor and the second integrating capacitor are symmetrical and have equal capacitance values. With this structure, a smaller sampling capacitance can be adopted, and stability is better. This is because the structure shown in fig. 2 is not sensitive to parasitic elements, and therefore better adaptability to physical parasitic elements and non-ideal factors is achieved, and correspondingly smaller capacitance is used.
Fig. 3 shows a specific circuit diagram of the second integrating unit 120 according to one embodiment of the present disclosure. Wherein the novel switched capacitor integrator has the advantages of high time constant accuracy, good temperature characteristics, and easy clock control.
One end of a thirteenth switch W1-1 is connected to the positive output terminal V1+ of the first operational amplifier OP1, the other end is connected to one end of a third sampling capacitor C5, the other end of the third sampling capacitor C5 is connected to the positive input terminal of the second operational amplifier OP2 via a fourteenth switch W3-1, the other end of the thirteenth switch W1-1 is connected to the external voltage Vcm via a fifteenth switch W2-1, and the other end of the third sampling capacitor C5 is connected to the regulated voltage Vcmi via a sixteenth switch W4-1. One end of a seventeenth switch W1-2 is connected to the negative output terminal V1 of the first operational amplifier OP1, the other end is connected to one end of a fourth sampling capacitor C6, the other end of the fourth sampling capacitor C6 is connected to the negative input terminal of the second operational amplifier OP2 via an eighteenth switch W3-2, the other end of the seventeenth switch W1-2 is connected to the external voltage Vcm via a nineteenth switch W2-2, and the other end of the fourth sampling capacitor C6 is connected to the adjustment voltage Vcmi via a twentieth switch W4-2.
In addition, the negative output terminal V2-of the second operational amplifier OP2 is connected to the positive input terminal via the third integrating capacitor C7, and the positive output terminal V2+ of the second operational amplifier OP2 is connected to the negative input terminal via the fourth integrating capacitor C8.
In order to achieve accurate measurement requirements, there is also provided in the present disclosure, according to a preferred embodiment of the present disclosure, a gain-enhanced operational amplifier structure, wherein the operational amplifier structure can be used as the first operational amplifier structure and the second operational amplifier structure described above.
Fig. 4 shows a schematic diagram of an operational amplifier structure according to the present disclosure.
The structure of the operational amplifier is as follows:
the source of the first PMOS transistor M0 is connected to the system voltage, the gate of the first PMOS transistor M0 is connected to the control voltage to control the on and off of the first PMOS transistor M0, the drain of the first PMOS transistor M3526 is connected to the source of the second PMOS transistor M1 and the source of the third PMOS transistor M2, the gate of the second PMOS transistor M1 and the gate of the third PMOS transistor M2 are connected to the positive input terminal and the negative input terminal, the drain of the second PMOS transistor M1 and the drain of the third PMOS transistor M2 are connected to the negative input terminal and the positive input terminal of the first amplifier An, respectively, the negative input terminal and the positive input terminal of the first amplifier An are grounded through the first NMOS transistor M4 and the second NMOS transistor M3, and the gates of the first NMOS transistor M4 and the second NMOS transistor M3 are connected.
The negative output terminal and the positive output terminal of the first amplifier An are respectively connected to the gates of the third NMOS transistor M5 and the fourth NMOS transistor M6, and the sources of the third NMOS transistor M5 and the fourth NMOS transistor M6 are respectively connected to the positive input terminal and the negative input terminal of the first amplifier An. The drains of the third NMOS transistor M5 and the fourth NMOS transistor M6 serve as the output terminals of the operational amplifier.
The sources of the fourth PMOS transistor M9 and the fifth PMOS transistor M10 are connected to the system voltage, the gates of the fourth PMOS transistor M9 and the fifth PMOS transistor M10 are connected, the drains of the fourth PMOS transistor M9 and the fifth PMOS transistor M10 are connected to the negative input terminal and the positive input terminal of the second amplifier Ap respectively and to the sources of the sixth PMOS transistor M7 and the seventh PMOS transistor M8 respectively, and the gates of the sixth PMOS transistor M7 and the seventh PMOS transistor M8 are connected to the positive output terminal and the negative output terminal of the second amplifier Ap respectively and to the drains of the third NMOS transistor M5 and the fourth NMOS transistor M6 respectively.
A circuit diagram of a quantization unit according to the present disclosure is provided in fig. 5, in which a pre-amplification circuit and a latch may be included, wherein the pre-amplification circuit amplifies an input signal (an output signal of the second integration unit) to a predetermined degree (a predetermined gain), and the latch latches the amplified signal. And the output terminals Q and QB are the output terminals of the quantizer in the circuit configuration shown in fig. 5.
The control of the switches in the first integration unit as shown in fig. 2 and the second integration unit as shown in fig. 3 may be controlled using clock signals generated by a clock generation circuit as shown in fig. 6.
The clock generation circuit described in fig. 6 can generate three two-phase non-overlapping clocks (clk1, clk 2; clk1 ', clk 2'; clk1 ', clk 2'), so that the correctness of the timing of the analog-to-digital conversion device can be ensured. By means of these overlap signals, the switches shown in fig. 2 and 3 can be controlled, for example. This allows the circuit to operate alternately under different control signals.
Further, according to a preferred embodiment of the present disclosure, a chopper circuit may be provided in the analog modulation section 100. Fig. 7 shows a circuit diagram of the chopper circuit.
Wherein the chopper circuit may be provided between the operational amplifier and the integrating capacitor as shown in fig. 2. The offset voltage of the operational amplifier can be eliminated by selecting or turning off the chopper circuit. By the chopper circuit, lower offset voltage can be realized. Specifically, the chopper circuit may modulate the offset voltage to a high frequency and then filter out. And the original signal still keeps the original state and is not influenced.
The chopper circuit is mainly composed of two switches and is controlled by a certain time sequence. In the first phase, INP is connected to OUTP and INN is connected to OUTN. And in the second phase, INP is connected to OUTN, and INN is connected to OUTP. This way, two modulations are achieved, the offset voltage being modulated to the location of the clock phase frequency. The original signal also undergoes modulation, but the second modulation modulates it back to the original position without being affected.
The low-pass filtering unit 200 is used for shaping and filtering out-of-band noise in the digital code stream output by the quantization unit.
Fig. 8 presents a schematic diagram of a low-pass filtering unit 200 according to an embodiment of the present disclosure.
As shown in fig. 8, the low pass filtering unit 200 may include two cascaded stages of digital filters, a first stage digital filter 210 and a second stage digital filter 220. The digital filter employed may be a FIR low-pass digital filter.
Wherein the first stage digital filter 210 and the second stage digital filter 220 may have the same structure.
First stage digital filter 210 may include only first stage adder 211 and first stage register 212 and no multiplication unit is needed in first stage digital filter 210.
The first stage adder 211 receives the output Q of the quantizer 130, and the first stage adder 211 is connected to the first stage register 212, and the first stage adder 211 is also connected to the output of the first stage register 212. After receiving one output data of the quantizer 130 through the first stage digital filter 210, the one output data is added to the previous output data (obtained from the output of the first stage register 212) through the first stage adder 211, and the added data is transferred from the first stage adder 211 to the first stage register 212, stored by the first stage register 212, and then waits for the next input data. When new data is received again from the quantizer 130, the new data is added to the data stored in the register by the first-stage adder 211, the added data is output to the first-stage register 212, and the first-stage register 212 stores the new data, so that the periodic operation is performed, and the accumulation and storage processes are completed.
The second stage adder 221 receives the output of the first stage register 212, and the second stage adder 221 is connected to the second stage register 222, and the second stage adder 221 is also connected to the output of the second stage register 222. After receiving one output data of the first stage register 212 through the second stage digital filter 220, the one output data is added to the previous output data (obtained from the output of the second stage register 222) by the second stage adder 221, and the added data is transferred from the second stage adder 221 to the second stage register 222, stored by the second stage register 222, and then waits for the next input data. When a new data is received again from the first stage register 212, the new data is added to the data stored in the register by the second stage adder 221, the added data is output to the second stage register 222, and the second stage register 222 stores the new data, so that the periodic operation is performed, thereby completing the process of accumulation and storage.
Further, the output of the second stage adder 221 may be taken as the output of the low pass filter unit 200.
In addition, a down-sampling module and a gain module may be added at the back end of the low pass filter 200.
In the digital filter of the low-pass filter, a multiplication unit is not needed, and the filter only consists of an adder and a register, so that the digital filter has the advantages of small hardware resource, high execution efficiency and small group delay.
It is also shown in fig. 8 that the low pass filtering unit 200 may further include a third-stage digital filter 230 and a fourth-stage digital filter 240. In this case, the output of the adder 241 of the fourth-stage digital filter 240 may be used as the output of the low-pass filtering unit 200.
The third stage adder 231 receives the output of the second stage register 222, and the third stage adder 231 is connected to the third stage register 232, and the third stage adder 231 is also connected to the output of the third stage register 232. After receiving one output data of the second stage filter 220 through the third stage digital filter 230, the one output data is added to the previous output data (obtained from the output of the third stage register 232) through the third stage adder 231, and the added data is transferred from the third stage adder 231 to the third stage register 232, stored by the third stage register 232, and then waits for the next input data. When a new data is received again from the second stage digital filter 220, the new data is added to the data stored in the register by the third stage adder 231, the added data is output to the third stage register 232, and the third stage register 232 stores the new data, so that the periodic operation is performed, thereby completing the process of accumulation and storage.
The fourth-stage adder 241 receives the output of the third-stage register 232, and the fourth-stage adder 241 is connected to the fourth-stage register 242, and the fourth-stage adder 241 is also connected to the output of the fourth-stage register 242. After receiving one output data of the third stage register 232, the fourth stage digital filter 240 adds the one output data to the previous output data (obtained from the output of the fourth stage register 242) by the fourth stage adder 241, and the added data is transferred from the fourth stage adder 241 to the fourth stage register 242, stored in the fourth stage register 242, and waits for the next input data. When a new data is received from the third-stage register 232 again, the new data is added to the data stored in the register by the fourth-stage adder 241, the added data is output to the fourth-stage register 242, and the fourth-stage register 242 stores the data, so that the periodic work is performed, thereby completing the process of accumulation and storage.
The random jitter filtering unit 300 will be described below.
The random jitter filtering unit 300 may be turned onThe shaped filtered signal of the low-pass filtering unit is processed by a noise coefficient matrix, wherein the noise coefficient matrix can be expressed as n (a) ═ a1、a2、……、ai) Wherein i is an integer of 2 or more.
The noise coefficient matrix is determined by the system noise characteristics of the analog-to-digital conversion device and is changed according to the system noise characteristics.
The random jitter filtering unit may perform filtering processing on each bit of data in the N significant bits of the analog-to-digital conversion apparatus, where each bit of data is connected to one random jitter filtering unit.
The random jitter filtering unit can also perform filtering processing on m bits of data in N effective bits of the analog-to-digital conversion device at the same time, and the m bits of data are connected with one random jitter filtering unit. For example, N is 12 bits, and m is set to 3 bits, so that one random jitter filter unit can be connected to each 3 bits of the 12 bits, and thus 4 random jitter filter units can be connected.
The processing of one-bit (e.g., least significant bit, LSM) data is explained below. Wherein, the historical data of the bit data is n, wherein n is more than or equal to 2.
Acquiring n pieces of history data of least significant bits: d1、D2、……、Dn. And determining output data D by combining the n pieces of history data with the noise coefficient matrixoutFor example, this can be represented by the following formula:
(a1×D1+a2×D2+……+an×Dn)/G＝Dout。
wherein the data of the coefficient G can be selected to be suitable values according to the actual requirements of the analog-to-digital conversion device.
In this way, even if the data is disturbed by a certain amount, the data is still stable and unchanged from the external view.
According to the present disclosure, there is also provided a battery management system, wherein the battery management system may be used to manage a battery or a battery pack, and the battery management system may be in the form of a chip. It should be noted that in the present disclosure, the charge and discharge control switch may be integrated inside the chip or may be disposed outside the chip. In the drawings of the present disclosure, a description is made in a form in which a charge and discharge control switch is provided inside a chip. In addition, an external charger or an external load may be connected to both positive and negative terminals of the battery or the battery pack to perform a charging operation or a discharging operation on the battery or the battery pack.
As shown in fig. 9, the battery management system may include a VDD generator, a voltage acquisition unit, a logic control unit, a driving unit, a charging/discharging control circuit, and the above-mentioned analog-to-digital conversion device.
The VDD generator generates a VDD voltage according to the highest voltage of the battery pack for use inside the chip.
The voltage acquisition unit is used for acquiring the voltage of the battery or the battery pack, when the battery pack is in the form of the battery pack, the voltage acquisition unit acquires the voltage of each battery, the voltage acquisition unit provides the acquired battery voltage to the control logic unit, and the control logic unit controls the charge and discharge control switch through the driving unit.
In addition, the device also comprises a detection resistor R for detecting the charging current and the discharging current.
Signals detected by the voltage acquisition unit and the detection resistor can be provided to the analog-to-digital conversion device disclosed by the disclosure so as to perform analog-to-digital conversion according to the signals, and then the signals converted by the analog-to-digital conversion device are provided to the control logic unit.
In the description herein, reference to the description of the terms "one embodiment/mode," "some embodiments/modes," "example," "specific example," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment/mode or example is included in at least one embodiment/mode or example of the application. In this specification, the schematic representations of the terms used above are not necessarily intended to be the same embodiment/mode or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments/modes or examples. Furthermore, the various embodiments/aspects or examples and features of the various embodiments/aspects or examples described in this specification can be combined and combined by one skilled in the art without conflicting therewith.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In the description of the present application, "plurality" means at least two, e.g., two, three, etc., unless specifically limited otherwise.
It will be understood by those skilled in the art that the foregoing embodiments are merely for clarity of illustration of the disclosure and are not intended to limit the scope of the disclosure. Other variations or modifications may occur to those skilled in the art, based on the foregoing disclosure, and are still within the scope of the present disclosure.
Claims (10)
1. An analog-to-digital conversion apparatus, comprising:
a first integration unit for receiving an analog input signal and performing modulation conversion on the analog input signal to generate a first integrated signal;
a second integration unit that receives the first integration signal and performs modulation conversion on the first integration signal to generate a second integration signal;
a quantization unit for comparing a second integrated signal and a reference signal and generating a digital code stream with analog input signal information based on the second integrated signal and the reference signal;
the low-pass filtering unit is used for shaping and filtering out-of-band noise in the digital code stream output by the quantization unit; and
and the random jitter filtering unit is used for filtering the shaped and filtered signals of the low-pass filtering unit so as to eliminate random jitter data existing in the shaped and filtered signals and generate digital output signals corresponding to the analog input signals.
2. The analog-to-digital conversion apparatus according to claim 1, wherein the random jitter filtering unit is configured to process a plurality of history data in the shaped filtered signal and generate the digital output signal corresponding to the analog input signal based on the plurality of history data, wherein the random jitter filtering unit removes random jitter data in the plurality of history data and generates the digital output signal based on history data not containing random jitter, or wherein the random jitter filtering unit reduces influence of random jitter data in the plurality of history data to generate the digital output signal.
3. The analog-to-digital conversion apparatus of claim 2, wherein the random jitter filtering unit is configured to eliminate random jitter in data of m significant bits of the N significant bits in the shaped filtered signal, where N ≧ 2 and 1 ≦ m ≦ N,
optionally, the random jitter filtering unit is configured to eliminate random jitter in the data of each of the N valid bits in the shaped filtered signal.
4. The analog-to-digital conversion device according to any one of claims 1 to 3, wherein in the first integrating unit, one end of a first switch is connected to a first analog input signal terminal, the other end is connected to one end of a first sampling capacitor, the other end of the first sampling capacitor is connected to the positive input terminal of the first operational amplifier via a second switch, one end of a third switch is connected to the first analog signal input terminal, the other end is connected to one end of a second sampling capacitor, the other end of the second sampling capacitor is connected to the negative input terminal of the first operational amplifier via a fourth switch, one end of a fifth switch is connected to the second analog input signal terminal, the other end is connected to one end of the second sampling capacitor, the other end of the second sampling capacitor is connected to the negative input terminal of the first operational amplifier via a fourth switch, the other end of a seventh switch is connected to the second analog input signal terminal, the other end is connected to one end of the first sampling capacitor, the other end of the first switch is connected to the positive reference voltage terminal through a seventh switch and is connected to the negative reference voltage terminal through an eighth switch, the other end of the fifth switch is connected to the positive reference voltage terminal through a ninth switch and is connected to the negative reference voltage terminal through a tenth switch, a connection node of the first sampling capacitor and the second switch is connected to the regulated voltage through an eleventh switch, a connection node of the second sampling capacitor and the fourth switch is connected to the regulated voltage through a twelfth switch, a negative output terminal of the first operational amplifier is connected to a positive input terminal thereof through a first integrating capacitor, and a positive output terminal of the first operational amplifier is connected to a negative input terminal thereof through a second integrating capacitor.
5. The analog-to-digital conversion device according to claim 4, wherein in the second integration unit, one end of a thirteenth switch is connected to the positive output terminal of the first operational amplifier, the other end is connected to one end of a third sampling capacitor, the other end of the third sampling capacitor is connected to the positive input terminal of the second operational amplifier via a fourteenth switch, the other end of the thirteenth switch is connected to the external voltage via a fifteenth switch, and the other end of the third sampling capacitor is connected to the regulated voltage via a sixteenth switch. One end of the seventeenth switch is connected with the negative output end of the first operational amplifier, the other end of the seventeenth switch is connected with one end of the fourth sampling capacitor, the other end of the fourth sampling capacitor is connected with the negative input end of the second operational amplifier through the eighteenth switch, the other end of the seventeenth switch is connected with external voltage through the nineteenth switch, the other end of the fourth sampling capacitor is connected with regulated voltage through the twentieth switch, the negative output end of the second operational amplifier is connected with the positive input end of the second operational amplifier through the third integrating capacitor, and the positive output end of the second operational amplifier is connected with the negative input end of the second operational amplifier through the fourth integrating capacitor.
6. The analog-to-digital conversion device of claim 4, wherein the first operational amplifier is configured to:
the source electrode of the first PMOS transistor is connected with the system voltage, the grid electrode of the first PMOS transistor is connected with the control voltage to control the on and off of the first PMOS transistor, the drain electrode of the first PMOS transistor is connected with the source electrode of the second PMOS transistor and the source electrode of the third PMOS transistor, the grid electrode of the second PMOS transistor and the grid electrode of the third PMOS transistor are respectively connected with the positive input end and the negative input end, the drain electrode of the second PMOS transistor and the drain electrode of the third PMOS transistor are respectively connected with the negative input end and the positive input end of the first amplifier, and the negative input terminal and the positive input terminal of the first amplifier are grounded through the first NMOS transistor and the second NMOS transistor respectively, and the grid electrodes of the first NMOS transistor and the second NMOS transistor are connected, the negative output end and the positive output end of the first amplifier are respectively connected to the grid electrodes of the third NMOS transistor and the fourth NMOS transistor, and the source electrodes of the third NMOS transistor and the fourth NMOS transistor are respectively connected with the positive input end and the negative input end of the first amplifier. The drain electrodes of the third NMOS transistor and the fourth NMOS transistor are used as output ends of the operational amplifier, the source electrodes of the fourth PMOS transistor and the fifth PMOS transistor are connected with system voltage, the grid electrodes of the fourth PMOS transistor and the fifth PMOS transistor are connected, the drain electrodes of the fourth PMOS transistor and the fifth PMOS transistor are respectively connected with the negative input end and the positive input end of the second amplifier and respectively connected with the source electrodes of the sixth PMOS transistor and the seventh PMOS transistor, and the grid electrodes of the sixth PMOS transistor and the seventh PMOS transistor are respectively connected with the positive output end and the negative output end of the second amplifier and respectively connected with the drain electrodes of the third NMOS transistor and the fourth NMOS transistor.
7. The analog-to-digital conversion device of claim 5, wherein the second operational amplifier is configured to:
the source electrode of the first PMOS transistor is connected with the system voltage, the grid electrode of the first PMOS transistor is connected with the control voltage to control the on and off of the first PMOS transistor, the drain electrode of the first PMOS transistor is connected with the source electrode of the second PMOS transistor and the source electrode of the third PMOS transistor, the grid electrode of the second PMOS transistor and the grid electrode of the third PMOS transistor are respectively connected with the positive input end and the negative input end, the drain electrode of the second PMOS transistor and the drain electrode of the third PMOS transistor are respectively connected with the negative input end and the positive input end of the first amplifier, and the negative input terminal and the positive input terminal of the first amplifier are grounded through the first NMOS transistor and the second NMOS transistor respectively, and the grid electrodes of the first NMOS transistor and the second NMOS transistor are connected, the negative output end and the positive output end of the first amplifier are respectively connected to the grid electrodes of the third NMOS transistor and the fourth NMOS transistor, and the source electrodes of the third NMOS transistor and the fourth NMOS transistor are respectively connected with the positive input end and the negative input end of the first amplifier. The drain electrodes of the third NMOS transistor and the fourth NMOS transistor are used as output ends of the operational amplifier, the source electrodes of the fourth PMOS transistor and the fifth PMOS transistor are connected with system voltage, the grid electrodes of the fourth PMOS transistor and the fifth PMOS transistor are connected, the drain electrodes of the fourth PMOS transistor and the fifth PMOS transistor are respectively connected with the negative input end and the positive input end of the second amplifier and respectively connected with the source electrodes of the sixth PMOS transistor and the seventh PMOS transistor, and the grid electrodes of the sixth PMOS transistor and the seventh PMOS transistor are respectively connected with the positive output end and the negative output end of the second amplifier and respectively connected with the drain electrodes of the third NMOS transistor and the fourth NMOS transistor.
8. The analog-to-digital conversion apparatus according to claim 5 or 6, wherein the quantization unit includes a pre-amplification circuit and a latch, wherein the pre-amplification circuit amplifies an output signal of the second integration unit by a predetermined gain, and the latch latches the amplified signal by the predetermined gain;
optionally, the digital signal processing circuit further comprises a chopper circuit, wherein the chopper circuit is used for eliminating an offset voltage of the operational amplifier and is connected between the operational amplifier and the integrating capacitor, and the chopper circuit performs twice modulation to modulate the offset voltage to a position of a clock phase frequency;
alternatively, the low-pass filtering unit includes two cascaded stages of digital filters, each of the data filters includes an adder and a register, each new data is added to the previous data by the adder when being input to each data filter, and the added result is saved by the register, and then is periodically added and saved while waiting for the next data input;
optionally, the random jitter filtering unit performs filtering processing on each bit of data in N valid bits of the analog-to-digital conversion device, where each bit of data is connected to one random jitter filtering unit;
optionally, the random jitter filtering unit performs filtering processing on m bits of data in N valid bits of the analog-to-digital conversion device at the same time, where the m bits of data are connected to one random jitter filtering unit;
optionally, the random jitter filtering unit receives n pieces of history data, and determines removal or reduction of influence of the random jitter data from the n pieces of history data according to system noise of the analog-to-digital conversion device to determine an output signal thereof, where n is greater than or equal to 2.
9. A battery management system, comprising:
an analog-to-digital conversion arrangement as claimed in any one of claims 1 to 8;
the battery voltage acquisition unit is used for acquiring the voltage of the battery/battery pack and providing the acquired voltage signal to the analog-to-digital conversion device;
and the control logic unit is used for receiving the digital signal converted by the analog-to-digital conversion device and generating a driving signal of a charge and discharge switch so as to control the charge and discharge of the battery.
10. The battery management system of claim 9, further comprising a charge and discharge current detection resistor, wherein the charge and discharge measurement signal generated by the charge and discharge current detection resistor is provided to the analog-to-digital conversion device and analog-to-digital converted by the analog-to-digital conversion device, and the converted signal is provided to the control logic unit, such that the control logic unit controls the charge and discharge switch according to the charge and discharge measurement signal.
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| WO2022217515A1 (en) * | 2021-04-14 | 2022-10-20 | 珠海迈巨微电子有限责任公司 | Analog-to-digital converter |
| CN113078717B (en) * | 2021-05-06 | 2022-05-13 | 北京时代民芯科技有限公司 | Voltage dump circuit applied to voltage sampling of multiple batteries |
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2020
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| CN115296672A (en) * | 2022-08-05 | 2022-11-04 | 珠海城市职业技术学院 | Sigma delta modulator based on unipolar transistor |
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