CN111555727A - High-gain low-noise switched capacitor adjustable gain amplifier - Google Patents
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Abstract
The invention provides a high-gain low-noise switched capacitor adjustable gain amplifier, which comprises an external signal source, a square wave generator, a switched capacitor integrator and a feedback circuit with a signal amplification function, wherein the external signal source and the square wave generator are connected into the switched capacitor integrator, the switched capacitor integrator outputs through the feedback circuit, the switched capacitor integrator comprises 7 COMS switching tubes which are started by forward pulses, a sampling capacitor, an adjustable feedback capacitor and an integrating capacitor, and the feedback circuit comprises an operational amplifier. The invention reduces the frequency of the integrated feedback capacitor in time to be equivalent to the capacitance value of the feedback capacitor, thereby reducing the noise of PGA while realizing high gain, simultaneously reducing power consumption and cost, improving the detection precision and efficiency of the circuit, being suitable for various sensor interfaces, signal conditioning chips and signal links, and having great market development prospect in automobile electronics, white household appliances, industrial automation and internet of things.
Description
Technical Field
The invention relates to the field of integrated circuit design, in particular to a high-gain low-noise switched capacitor adjustable gain amplifier.
Background
A switched capacitor variable gain amplifier (PGA) is often used in a sensor signal detection, analog-to-digital signal conversion (ADC) and digital-to-analog (DAC) conversion circuit. However, in the conventional PGA circuit with a switched capacitor, when a higher gain is achieved, the ratio of the input capacitor to the feedback capacitor of the switched capacitor amplifier is often increased, or a two-stage PGA circuit is cascaded. The former realizes high gain and simultaneously has much noise amplification of the switch capacitor, and the latter has defects in power consumption and chip area occupation consideration.
As shown in fig. 1, for example, a single-ended output switch capacitor PGA is used, a control clock signal of a CMOS switch is an equal-duration two-phase square wave with non-overlapping characteristics, a pulse square wave of a first phase is a sampling time, a pulse square wave of a second phase is an amplification or integration time, and charges of a sampling capacitor and an adjustable feedback capacitor are integrated by an operational amplifier through a feedback path. In the figure 120, a non-overlapping pulse generator generates the gate control signals for the switching tubes, and φ 1 and φ 2 are sampling and integration periods, respectively.
This achieves sampling and amplification of the signal within the time of one cycle. According to the working principle of the switch capacitor, the amplification factor of the PGA at phi 2 is the ratio of the input capacitor to the feedback capacitor:
Gain＝Vout(n)/Vin(n)＝C104/C108
where n is the number of pulse cycles.
The noise originated from the switched capacitor is a key index affecting the accuracy of the output signal, and the high amplification factor PGA should be designed to reduce the noise as much as possible. The switched capacitor noise entering the inverting input of the op-amp in fig. 1 is expressed in charge as:
where K is a constant and T is an absolute temperature value.
If translated to the input switched capacitor 104, the equivalent noise voltage at the input is expressed as:
the noise voltage at the output is:
in equation (3), the Gain is a value set by the amplification of the PGA signal, and generally Gain > >1, it can be seen that the reduction of the equivalent output noise of the PGA must increase the capacitance of the tunable capacitor 108 when Gain is a set value. But increasing the capacitance of the capacitor 108 is severely limited,
1. increasing the capacitance value of 108, and correspondingly increasing the capacitance value of 104 in order to keep the Gain unchanged; meanwhile, in order to maintain a certain system bandwidth, noise is filtered, and the reduction of the closed-loop feedback coefficient of the operational amplifier 111 is prevented from influencing the integration precision, the capacitance value of the integrating capacitor 102 must be increased. The result is a significant increase in the area required for the chip and an increase in cost.
2. If the capacitance values of 108 and 104 are increased simultaneously, the power consumption is also increased, because the charging and discharging current required by the operational amplifier 111 to complete integration is increased obviously and the chip power consumption is increased.
In practical application, most of the PGAs are in fully differential structures, and the principle is unchanged. The above formula for switched capacitor noise is the same as the problem encountered.
Disclosure of Invention
The invention solves the technical problem of providing a high-gain low-noise switched capacitor adjustable gain amplifier, which reduces the integrated frequency of a feedback capacitor in time to be equivalent to reducing the capacitance value of the feedback capacitor, reduces the noise of a switched capacitor circuit under the condition of realizing high gain, does not increase the layout area of the circuit, reduces the power consumption and the cost, improves the detection precision and the efficiency of a signal detection circuit, is suitable for various sensor interfaces, signal conditioning chips and signal links, and has great market development prospect in automotive electronics, white household appliances, industrial automation and the Internet of things.
The technical solution for realizing the purpose of the invention is as follows:
a high-gain low-noise switched-capacitor adjustable gain amplifier, comprising: the frequency division control circuit comprises an external signal source, a square wave generator with a frequency division function, a switched capacitor integrator and a feedback circuit with a signal amplification function, wherein the external signal source is connected to the switched capacitor integrator; the switched capacitor integrator comprises 7 COMS switch tubes started by forward pulses, a sampling capacitor, an adjustable feedback capacitor and an integrating capacitor, a feedback circuit comprises an operational amplifier, the COMS switch tubes started by the forward pulses are all connected with a square wave generator and comprise a first COMS switch tube, a second COMS switch tube, a third COMS switch tube, a fourth COMS switch tube, a fifth COMS switch tube, a sixth COMS switch tube and a seventh COMS switch tube; one end of the second COMS switch tube is connected with an external signal source to obtain an input signal, the other end of the second COMS switch tube is connected with one end of the sampling capacitor and one end of the third COMS switch tube in a common mode, and the other end of the third COMS switch tube is grounded; the other end of the sampling capacitor is connected with one end of the first COMS switch tube, one end of the fourth COMS switch tube and one end of the adjustable feedback capacitor in a common mode, and the other end of the fourth COMS switch tube is grounded; the other end of the first COMS switch tube is connected with the inverting input end of the operational amplifier; two ends of the integrating capacitor are respectively connected with the reverse input end and the output end of the operational amplifier, and the forward input end of the operational amplifier is grounded; the other end of the adjustable feedback capacitor is connected with one end of a fifth COMS switch tube, one end of a seventh COMS switch tube and one end of a sixth COMS switch tube, the other end of the fifth COMS switch tube and the other end of the seventh COMS switch tube are both grounded, the other end of the sixth COMS switch tube is connected with the output end of an operational amplifier, and the output end of the operational amplifier is used for outputting a signal for a total output end; the square wave generator comprises an oscillator circuit, a phase non-overlapping circuit and a frequency divider which are sequentially connected and used for generating an isochronous-length biphase non-overlapping clock signal, wherein the square wave of the first phase is sampling time, and the square wave of the second phase is integration time.
Further, in the high-gain low-noise switched capacitor adjustable gain amplifier of the present invention, the square wave generator outputs a clock signal to the sampling capacitor, and the sampling capacitor is controlled to sample and integrate the input signal in two time periods of one clock cycle, where the sampling time period is an integration time period.
Further, in the high-gain low-noise switched capacitor adjustable gain amplifier of the present invention, the square wave generator outputs a clock signal to the adjustable feedback capacitor, and controls the adjustable feedback capacitor to sample and integrate the input signal in two time periods of a clock cycle, where the sampling time period is a sampling time period after N times of frequency division, that is: and in every N cycles, 1 cycle is an effective sampling period, the rest N-1 cycles are null samples, N is a frequency division coefficient and is controlled by a frequency divider, and the integration period of the N is consistent with the integration period of the control sampling capacitor.
Furthermore, in the high-gain low-noise switched capacitor adjustable gain amplifier of the invention, the charge quantity sampled by the feedback capacitor (108) in each N periods is as follows: (Q)108)AVE＝Vout·C108/N。
The application of the high-gain low-noise switched capacitor adjustable gain amplifier in a switched capacitor adjustable gain circuit for signal detection, analog-to-digital conversion, sensor signal amplification and conditioning.
A sampling and integration time control method of a switched capacitor adjustable gain amplifier respectively controls a sampling time period and an integration time period of an adjustable feedback capacitor of the switched capacitor adjustable gain amplifier:
1) controlling the clock signal of the integration time period of the adjustable feedback capacitor to be consistent with the clock signal of the integration time period of the sampling capacitor;
2) the clock signal for controlling the sampling time period of the adjustable feedback capacitor is a clock signal subjected to N times of frequency division, namely the effective sampling time period of the adjustable feedback capacitor in each N cycles is 1 cycle, the sampling of other N-1 cycles is null sampling, namely the voltage of the sampling is 0, wherein N is a frequency division coefficient.
Compared with the prior art, the invention adopting the technical scheme has the following technical effects:
the high-gain low-noise switched capacitor adjustable gain amplifier does not reduce the true capacitance value of the adjustable feedback capacitor to increase noise while increasing the amplification factor, does not increase the capacitance value of the adjustable feedback capacitor, and increases the chip area and the charge-discharge current of the operational amplifier due to the synchronous increase of the capacitance value of the integrating capacitor 102, thereby realizing the high amplification factor without increasing the occupied wafer area and power consumption.
Drawings
Fig. 1 is a circuit diagram of a conventional single-ended output switched capacitor PGA.
Fig. 2 is a circuit diagram of the high-gain low-noise switched capacitor adjustable gain amplifier of the present invention.
Fig. 3 is a schematic diagram of a control clock when the frequency division multiple of the high-gain low-noise switched capacitor adjustable gain amplifier of the invention is 4.
Fig. 4 is a schematic diagram of a fully differential architecture of a high-gain low-noise switched capacitor variable gain amplifier of the present invention.
Reference signs mean: 101: signal source, 103, 105, 106, 107, 109, 110, 209: forward pulse-on CMOS switch tube, 102: integration capacitance, 104: sampling capacitance, 108: adjustable feedback capacitor, 111 is an operational amplifier, 301: differential mode input signal, 302: common mode input signal, 303-312: CMOS switch tube, 320, 321: input capacitance pair, 322, 323: feedback capacitance pair, 324, 325: integrating capacitance pair, 331: and (4) fully-differential output operational amplifier.
Detailed Description
Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the accompanying drawings are illustrative only for the purpose of explaining the present invention, and are not to be construed as limiting the present invention.
A high-gain low-noise switched capacitor adjustable gain amplifier, as shown in fig. 2, comprising: the frequency division circuit comprises an external signal source, a square wave generator with the frequency division function, a switched capacitor integrator and a feedback circuit with the signal amplification function, wherein the external signal source is connected into the switched capacitor integrator, the square wave generator is used for generating a frequency division control clock signal to the switched capacitor integrator, and the switched capacitor integrator is output through the feedback circuit.
The switched capacitor integrator comprises 7 COMS switching tubes started by forward pulses, a sampling capacitor 104, an adjustable feedback capacitor 108 and an integrating capacitor 102, a feedback circuit comprises an operational amplifier 111, and the COMS switching tubes started by the forward pulses are all connected with a square wave generator and comprise a first COMS switching tube 103, a second COMS switching tube 105, a third COMS switching tube 106, a fourth COMS switching tube 107, a fifth COMS switching tube 109, a sixth COMS switching tube 110 and a seventh COMS switching tube 209; .
One end of the second cmos switch tube 105 is connected to an external signal source to obtain an input signal, the other end of the second cmos switch tube 105 is connected to one end of the sampling capacitor 104 and one end of the third cmos switch tube 106, and the other end of the third cmos switch tube 106 is grounded; the other end of the sampling capacitor 104 is connected with one end of the first cmos switch tube 103, one end of the fourth cmos switch tube 107 and one end of the adjustable feedback capacitor 108 in common, and the other end of the fourth cmos switch tube 107 is grounded; the other end of the first cmos switch tube 103 is connected to the inverting input terminal of the operational amplifier 111; two ends of the integrating capacitor 102 are respectively connected with the reverse input end and the output end of the operational amplifier 111, and the forward input end of the operational amplifier 111 is grounded; the other end of the adjustable feedback capacitor 108 is connected to one end of the fifth cmos switch tube 109, one end of the seventh cmos switch tube 209, and one end of the sixth cmos switch tube 110, the other end of the fifth cmos switch tube 109 and the other end of the seventh cmos switch tube 209 are both grounded, the other end of the sixth cmos switch tube 110 is connected to the output end of the operational amplifier 111, and the output end of the operational amplifier is a total output end output signal.
The square wave generator comprises an oscillator circuit, a phase non-overlapping circuit and a frequency divider which are sequentially connected and used for generating an isochronous-length biphase non-overlapping clock signal, wherein the square wave of the first phase is sampling time, and the square wave of the second phase is integration time.
Example 1
A high-gain low-noise switched capacitor adjustable gain amplifier, as shown in fig. 2, comprising: the frequency division circuit comprises an external signal source, a square wave generator with the frequency division function, a switched capacitor integrator and a feedback circuit with the signal amplification function, wherein the external signal source is connected into the switched capacitor integrator, the square wave generator is used for generating a frequency division control clock signal to the switched capacitor integrator, and the switched capacitor integrator is output through the feedback circuit.
The switched capacitor integrator comprises 7 COMS switching tubes started by forward pulses, a sampling capacitor 104, an adjustable feedback capacitor 108 and an integrating capacitor 102, a feedback circuit comprises an operational amplifier 111, and the COMS switching tubes started by the forward pulses are all connected with a square wave generator and comprise a first COMS switching tube 103, a second COMS switching tube 105, a third COMS switching tube 106, a fourth COMS switching tube 107, a fifth COMS switching tube 109, a sixth COMS switching tube 110 and a seventh COMS switching tube 209; .
One end of the second cmos switch tube 105 is connected to an external signal source to obtain an input signal, the other end of the second cmos switch tube 105 is connected to one end of the sampling capacitor 104 and one end of the third cmos switch tube 106, and the other end of the third cmos switch tube 106 is grounded; the other end of the sampling capacitor 104 is connected with one end of the first cmos switch tube 103, one end of the fourth cmos switch tube 107 and one end of the adjustable feedback capacitor 108 in common, and the other end of the fourth cmos switch tube 107 is grounded; the other end of the first cmos switch tube 103 is connected to the inverting input terminal of the operational amplifier 111; two ends of the integrating capacitor 102 are respectively connected with the reverse input end and the output end of the operational amplifier 111, and the forward input end of the operational amplifier 111 is grounded; the other end of the adjustable feedback capacitor 108 is connected to one end of the fifth cmos switch tube 109, one end of the seventh cmos switch tube 209, and one end of the sixth cmos switch tube 110, the other end of the fifth cmos switch tube 109 and the other end of the seventh cmos switch tube 209 are both grounded, the other end of the sixth cmos switch tube 110 is connected to the output end of the operational amplifier 111, and the output end of the operational amplifier is a total output end output signal.
The square wave generator comprises an oscillator circuit, a phase non-overlapping circuit and a frequency divider which are sequentially connected and used for generating an isochronous-length biphase non-overlapping clock signal, wherein the square wave of the first phase is sampling time, and the square wave of the second phase is integration time. The square wave generator outputs a clock signal to the sampling capacitor 104, and controls the sampling capacitor 104 to sample and integrate the input signal in two time periods of one clock cycle, where the sampling time period is an integration time period. The square wave generator outputs a clock signal to the adjustable feedback capacitor 108, and controls the adjustable feedback capacitor 108 to input the clock signal in two time periods of one clock cycleThe number is sampled and integrated, and the sampling time period is N times of the sampling time period after frequency division, namely: and in every N cycles, 1 cycle is an effective sampling period, the rest N-1 cycles are null samples, N is a frequency division coefficient and is controlled by a frequency divider, and the integration period of the N is consistent with the integration period of the control sampling capacitor 104. The amount of charge sampled by feedback capacitor 108 on average every N cycles is: (Q)108)AVE＝Vout·C108/N。
The application of the high-gain low-noise switched capacitor adjustable gain amplifier in a switched capacitor adjustable gain circuit for signal detection, analog-to-digital conversion, sensor signal amplification and conditioning is provided.
A sampling and integration time control method of a switched capacitor adjustable gain amplifier respectively controls the sampling time period and the integration time period of an adjustable feedback capacitor 108 of the switched capacitor adjustable gain amplifier:
1) the clock signal for controlling the integration time period of the adjustable feedback capacitor 108 is consistent with the clock signal for controlling the integration time period of the sampling capacitor 104;
2) the clock signal for controlling the sampling time period of the adjustable feedback capacitor 108 is a clock signal subjected to frequency division by N times, that is, the effective sampling time period of the adjustable feedback capacitor 108 in each N cycles is 1 cycle, the samples in other N-1 cycles are null samples, the null samples are voltage samples of 0, where N is a frequency division coefficient.
As shown in fig. 3, 220 and 221 are control signals generated by a square wave generator for controlling the CMOS switch tubes, where Φ 1 and Φ 2 are a sampling period and an integration period, respectively, 222 and 223 are control signals of the sixth CMOS switch tube 110 and the seventh CMOS switch tube 209 after being processed by the frequency divider, respectively, where the frequency division factor N is 4, and 224 is an output voltage waveform of Vout when the frequency division multiple N is 4.
1) In the sampling period φ 1 of the first cycle, the second COMS switch 105, the fourth COMS switch 107 and the sixth COMS switch 110 are closed, and the other switches are open. The sampling capacitor 104 and the adjustable feedback capacitor 108 are charged to vin.C by Vin and Vout, respectively104And Vout. C108。
2) In the integration period phi 2 of the first cycle, the third cmos switch tube 106, the first cmos switch tube 103 and the fifth cmos switch tube 109 are closed, and the other switch tubes are opened. The charges in the sampling capacitor 104 and the adjustable feedback capacitor 108 are driven into the integrating capacitor 102, and the variation of the output voltage is:
ΔVout＝(Vin·C104-Vout·C108)/C102
3) in the subsequent consecutive 3 cycles (i.e. the second cycle to the fourth cycle), as shown in 222 and 223 in fig. 3, the sixth cmos switch tube 110 is kept open all the time, and the seventh cmos switch tube 209 is closed in the sampling time period, so that the sampling of the adjustable feedback capacitor 108 is zero or "null sampling". After 4 cycles, the variation of the output voltage is:
ΔVout＝(Vin·4·C104-Vout·C108)/C102(4)
it can be seen from equation (4) that when the division factor is 4, the equivalent of the adjustable feedback capacitor 108 is one fourth of the sampling capacitor 104, and the equivalent of the amplification factor is 4 when viewed from the average value of the output voltage, as shown in 224 of fig. 3.
From the perspective of each switched capacitor (sampling capacitor 104 and adjustable feedback capacitor 108), in the time period of each clock cycle, both plates of the capacitor are connected with switches to act, and the capacitance value of the capacitor is not changed before and after improvement. The switched capacitor noise defined by equations (1) - (3) thus still applies, i.e. a 4-fold amplification is achieved without increasing the output noise from the switched capacitor integrator.
The allocation multiple is not limited to 4 in the application, and can be designed into other suitable integers. It should be noted that as the division factor increases, the equivalent integration time constant increases and the bandwidth decreases.
Example 2
As shown in fig. 4, the switched capacitor variable gain amplifier is a fully differential structure, and its principle is the same as that of single-ended output PGA circuit, but it has more practical value due to its symmetrical structure.
The switched capacitor adjustable gain amplifier with the fully differential structure comprises an external signal source, a square wave generator with a frequency division function, a switched capacitor integrator and a fully differential output operational amplifier 331, wherein the external signal source is connected to the switched capacitor integrator;
the external signal source comprises a differential mode input signal source 301 and a common mode input signal source 302, the differential mode input signal source 301 and the common mode input signal source 302 are sequentially connected, the other end of the common mode input signal source 302 is grounded, the switched capacitor integrator comprises 7 pairs of COMS switching tube pairs which are started by forward pulses, input capacitor pairs 320 and 321, feedback capacitor pairs 322 and 323 and integrating capacitor pairs 324 and 325, the COMS switching tube pairs which are started by the forward pulses are all connected with a square wave generator, and the COMS switching tube pairs are 303 and 304, 305 and 306, 307 and 308, 309 and 310, 311 and 312, 313 and 314, 315 and 316 respectively;
one end of the COMS switch tube 303 is connected with the differential mode input signal source 301 to obtain an input signal, the other end of the COMS switch tube 303 is connected with one end of the input capacitor 320 and one end of the COMS switch tube 305 in a common mode, and the other end of the COMS switch tube 305 is grounded; the other end of the input capacitor 320 is connected with one end of the COMS switch tube 309, one end of the COMS switch tube 307 and one end of the feedback capacitor 322 in common, and the other end of the COMS switch tube 307 is grounded; the other end of the cmos switch tube 309 and one end of the integrating capacitor 324 are both connected to the inverting input terminal of the fully differential output operational amplifier 331; the other end of the integrating capacitor 324 is connected with the positive output end of the fully differential output operational amplifier 331; the other end of the feedback capacitor 322 is connected to one end of the cmos switch tube 311, one end of the cmos switch tube 313, and one end of the cmos switch tube 315, the other end of the cmos switch tube 311 and the other end of the cmos switch tube 313 are both grounded, the other end of the cmos switch tube 315 is connected to the forward output end of the fully differential output operational amplifier 331, and the forward output end of the fully differential output operational amplifier 331 is the total forward output end output signal.
One end of the COMS switch tube 304 is connected to the common mode input signal source 302 to obtain an input signal, the other end of the COMS switch tube 304 is connected to one end of the input capacitor 321 and one end of the COMS switch tube 306 in common, and the other end of the COMS switch tube 306 is grounded; the other end of the input capacitor 321 is connected with one end of the COMS switch tube 310, one end of the COMS switch tube 308 and one end of the feedback capacitor 323 in common, and the other end of the COMS switch tube 308 is grounded; the other end of the cmos switch tube 310 and one end of the integrating capacitor 325 are both connected to the positive input end of the fully differential output operational amplifier 331; the other end of the integrating capacitor 325 is connected with the inverting output end of the fully differential output operational amplifier 331; the other end of the feedback capacitor 323 is connected to one end of the cmos switch tube 312, one end of the cmos switch tube 314, and one end of the cmos switch tube 316, the other end of the cmos switch tube 312 and the other end of the cmos switch tube 314 are both grounded, the other end of the cmos switch tube 316 is connected to the inverting output terminal of the fully differential output operational amplifier 331, and the inverting output terminal of the fully differential output operational amplifier 331 outputs a signal for the total inverting output terminal.
The switching control signals of the CMOS switch tubes 303, 304, 307 and 308 are 220 in fig. 3, the switching control signals of the CMOS switch tubes 305, 306, 309, 310, 311 and 312 are 221 in fig. 3, the switching control signals of the CMOS switch tubes 315 and 316 are 222 in fig. 3, and the switching control signals of the CMOS switch tubes 313 and 314 are 223 in fig. 3.
The switched capacitor PGA in the above two embodiments does not increase the amplification factor and also does not increase the output noise from the switched capacitor, and does not increase the chip area and power consumption. Compared with the conventional PGA circuit, the signal-to-noise ratio of the output signal is remarkably improved, and the PGA circuit is suitable for a sensor with the characteristic of low-frequency weak signals or a signal sampling system of other physical signal sources. The improved circuit has the characteristics of wide application range and flexibility, can be applied to a signal acquisition system of a sensor, and can also be applied to a high-precision ADC (analog to digital converter), a DAC (digital to analog converter) and other signal processing circuits of switched capacitors.
The foregoing is directed to embodiments of the present invention and, more particularly, to a method and apparatus for controlling a power converter in a power converter, including a power converter, a power.
Claims (6)
1. A high-gain low-noise switched capacitor adjustable gain amplifier, comprising: the frequency division control circuit comprises an external signal source, a square wave generator with a frequency division function, a switched capacitor integrator and a feedback circuit with a signal amplification function, wherein the external signal source is connected to the switched capacitor integrator;
the switched capacitor integrator comprises 7 COMS switch tubes started by forward pulses, a sampling capacitor (104), an adjustable feedback capacitor (108) and an integrating capacitor (102), a feedback circuit comprises an operational amplifier (111), the COMS switch tubes started by the forward pulses are all connected with a square wave generator and comprise a first COMS switch tube (103), a second COMS switch tube (105), a third COMS switch tube (106), a fourth COMS switch tube (107), a fifth COMS switch tube (109), a sixth COMS switch tube (110) and a seventh COMS switch tube (209);
one end of the second COMS switch tube (105) is connected with an external signal source to obtain an input signal, the other end of the second COMS switch tube (105) is connected with one end of the sampling capacitor (104) and one end of the third COMS switch tube (106) in common, and the other end of the third COMS switch tube (106) is grounded; the other end of the sampling capacitor (104) is connected with one end of a first COMS switch tube (103), one end of a fourth COMS switch tube (107) and one end of an adjustable feedback capacitor (108) in common, and the other end of the fourth COMS switch tube (107) is grounded; the other end of the first COMS switch tube (103) is connected with the inverting input end of the operational amplifier (111); two ends of the integrating capacitor (102) are respectively connected with the reverse input end and the output end of the operational amplifier (111), and the forward input end of the operational amplifier (111) is grounded; the other end of the adjustable feedback capacitor (108) is connected with one end of a fifth COMS switch tube (109), one end of a seventh COMS switch tube (209) and one end of a sixth COMS switch tube (110) in a common mode, the other end of the fifth COMS switch tube (109) and the other end of the seventh COMS switch tube (209) are grounded, the other end of the sixth COMS switch tube (110) is connected with the output end of an operational amplifier (111), and the output end of the operational amplifier is used for outputting a signal for a total output end;
the square wave generator comprises an oscillator circuit, a phase non-overlapping circuit and a frequency divider which are sequentially connected and used for generating an isochronous-length biphase non-overlapping clock signal, wherein the square wave of the first phase is sampling time, and the square wave of the second phase is integration time.
2. A high-gain low-noise switched capacitor adjustable gain amplifier according to claim 1, wherein the square wave generator outputs a clock signal to the sampling capacitor (104), and the sampling capacitor (104) is controlled to sample and integrate the input signal in two time segments of one clock cycle, where the sampling time segment is the integration time segment.
3. A high-gain low-noise switched capacitor adjustable gain amplifier according to claim 1, wherein the square wave generator outputs a clock signal to the adjustable feedback capacitor (108), and the adjustable feedback capacitor (108) is controlled to sample and integrate the input signal in two time segments of one clock cycle, where the sampling time segment is N times the sampling time segment after frequency division, that is: and in every N cycles, 1 cycle is an effective sampling period, the rest N-1 cycles are null samples, N is a frequency division coefficient and is controlled by a frequency divider, and the integration period of the N is consistent with the integration period of the control sampling capacitor (104).
4. A high gain low noise switched capacitor adjustable gain amplifier according to claim 3, wherein the amount of charge sampled by the feedback capacitor (108) on average every N cycles is: (Q)108)AVE＝Vout·C108/N。
5. Use of a high gain, low noise switched capacitor variable gain amplifier according to any of claims 1-4 in switched capacitor variable gain circuits for signal detection, analog to digital conversion, sensor signal amplification and conditioning.
6. A sampling and integration time control method for a switched capacitor adjustable gain amplifier is characterized in that a sampling time period and an integration time period of an adjustable feedback capacitor (108) of the switched capacitor adjustable gain amplifier are respectively controlled:
1) controlling the clock signal of the integration time period of the adjustable feedback capacitor (108) to be consistent with the clock signal of the integration time period of the sampling capacitor (104);
2) the clock signal for controlling the sampling time period of the adjustable feedback capacitor (108) is a clock signal subjected to N times of frequency division, namely the effective sampling time period of the adjustable feedback capacitor (108) in each N periods is 1 period, the samples in other N-1 periods are null samples, the null samples are sampled, namely the voltage of the samples is 0, and N is a frequency division coefficient.
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| CN112688687A (en) * | 2020-12-09 | 2021-04-20 | 南方电网数字电网研究院有限公司 | Method and device for acquiring physical information to be tested, computer equipment and storage medium |
| CN113381729A (en) * | 2021-06-25 | 2021-09-10 | 上海料聚微电子有限公司 | Switched capacitor integrator and control method for improving transient performance thereof |
| CN113872605A (en) * | 2021-09-30 | 2021-12-31 | 江苏润石科技有限公司 | Method and circuit for reducing power consumption of Sigma-Delta integrator |
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| CN113381729A (en) * | 2021-06-25 | 2021-09-10 | 上海料聚微电子有限公司 | Switched capacitor integrator and control method for improving transient performance thereof |
| CN113872605A (en) * | 2021-09-30 | 2021-12-31 | 江苏润石科技有限公司 | Method and circuit for reducing power consumption of Sigma-Delta integrator |
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