JPH0993086A - Switched capacitor circuit and signal processing circuit using the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To increase an equivalent resistance value regardlessly of the switching frequency and capacitance of switched capacitor. SOLUTION: Five capacitors C1 to C5 , for which one terminal is connected to the ground, are parallelly arranged and between a signal input terminal 2 and a ground terminal 3, the other terminals of capacitors C1 to C5 are successively connected by transistors Tr1 to Tr6 . The mutually adjacent transistors Tr1 to Tr6 are alternately turned on/off at frequency f. Thus, a five-fold equivalent resistance value R=5/fC as large as that of equivalent resistance circuit composed of a switched capacitor equipped with one capacitor can be provided.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a switched capacitor circuit and a signal processing circuit using the same, and more particularly to an increase in resistance value of the switched capacitor circuit.

[0002]

2. Description of the Related Art Conventionally, a switched capacitor has been known as an equivalent resistance in a semiconductor integrated circuit and is widely used for a filter or the like. FIG. 8 shows the basic configuration. A changeover switch 43 is provided between each of the terminals 41 and 42 and the other end of the capacitor 40 having the capacitance C whose one end is connected to the ground. The changeover switches 43 are alternately connected to the terminal 41 side and the terminal 42 side at the frequency f. For example, when a power source of voltage V ₀ is connected to the terminal 41 and a ground is connected to the terminal 42, the electric charge of CV ₀ moves to the terminal 42 in 1 / f. Both terminals 41,
Considering the average transfer of electric charge between 42, the magnitude of the current between both terminals is fCV ₀ , and the resistance R between both terminals is given by the following equation.

R = 1 / f · C (1) The actual current flows intermittently by switching, but when viewed on a macro time scale compared to the switching frequency f, the circuit of FIG. Acts as an equivalent resistance circuit.

This equivalent resistance circuit has the advantage that the resistance value R can be controlled by changing the frequency f.

[0005]

Heretofore, there has conventionally been no demand to increase the resistance value of this switched capacitor. However, when the application of the switched capacitor is expanded, there may be a demand for increasing the resistance value R of the switched capacitor depending on the application.
In order to increase the resistance value R of the switched capacitor, it is necessary to reduce the switching frequency f or the capacitance C. However, it is technically difficult to accurately realize a capacitor of about 0.5 pF or less on an integrated circuit, and there is a limit to the method of decreasing the capacitance C and increasing the resistance value R. When the switched capacitor circuit is used for signal processing, the switching frequency f needs to be sufficiently higher than the signal frequency due to aliasing. Therefore, the switching frequency f cannot be lowered indefinitely.

As described above, in the conventional switched capacitor circuit, the resistance value R has a practical upper limit.

An object of the present invention is to provide a switched capacitor circuit capable of sufficiently increasing the resistance value R while keeping the switching frequency f and the capacitance C at practical values, and a signal processing circuit using the same. To do.

[0008]

A switched capacitor circuit according to the present invention is a switched capacitor circuit in which one end of a capacitor, one end of which is connected to a constant voltage source, is alternately connected to a first terminal or a second terminal by a changeover switch. By providing a plurality of switch capacitors, and connecting the second terminal of one switched capacitor to the first terminal of the adjacent switched capacitor, the plurality of switched capacitors are sequentially connected and the polarity of the switch switching between the two adjacent switched capacitors. On the contrary, the capacitors of two adjacent switched capacitors are intermittently connected to each other and act as an equivalent resistance between the first terminal and the second terminal of the last switched capacitor.

The plurality of switched capacitors sequentially transfer the charges to the adjacent switched capacitors, but the amount of charges transferred in a state where the capacitors of the adjacent switched capacitors are short-circuited is the same until both voltages become the same. . Therefore, the amount of charge accumulated in the switched capacitor gradually decreases. Since the amount of current in the switched capacitor circuit is determined by the amount of charge in the final switched capacitor, that is, the amount of charge flowing in the constant voltage source (eg, ground), the resistance value is increased by providing a plurality of switched capacitors. be able to.

Therefore, according to the present invention, the equivalent resistance value R is increased without reducing the switching frequency f and the capacitance C. Therefore, in the semiconductor integrated circuit,
High resistance can be obtained.

In the signal processing circuit of the present invention, a signal is input to a non-inverting input terminal and a signal is output from an output terminal to which the inverting input terminal is connected, and one end is a non-inverting input terminal of the buffer amplifier. An equivalent resistance circuit connected to one end and the other end connected to a constant voltage source, wherein the equivalent resistance circuit is the switched capacitor circuit described above.

The signal is converted into a voltage signal by the switched capacitor circuit. Then, this voltage signal is amplified by the buffer amplifier into a signal having sufficient current capability. Here, since the switched capacitor circuit is a circuit using the above-described plurality of switched capacitors, the resistance thereof can be increased. Therefore, even a weak current signal can be supplied to the buffer amplifier as a sufficient voltage.

In the signal processing circuit of the present invention, the first and second buffer amplifiers having the inverting input terminal and the output terminal connected to each other, and the one end to the non-inverting input terminal of the first and second buffer amplifiers, respectively. The first and second equivalent resistance circuits connected to each other and the other end connected to the constant voltage source, and the outputs of the first and second buffer amplifiers are input to the two input terminals, and the outputs of both buffer amplifiers are connected. A differential amplifier that outputs a signal regarding the difference, wherein the first and second equivalent resistance circuits are the switched capacitor circuit according to claim 1 having substantially the same configuration, and the first and second equivalent resistance circuits are the same. And a signal is input to only one of the second buffer amplifier and an output signal is obtained at the output of the differential amplifier.

Since the input signal is input to only one of the first and second buffer amplifiers, the signal is output from this buffer amplifier. Since no signal is input to the other buffer amplifier, no signal is output, but switching noise, offset voltage, etc. in the switched capacitor circuit are output from the other buffer amplifier. Since the outputs of the two buffer amplifiers are subtracted from each other, switching noise and offset voltage are removed, and only the signal component is obtained at the output of the differential amplifier.

As described above, according to the present circuit, it is possible to effectively eliminate the problem in the signal processing caused by using the switched capacitor circuit.

[0016]

Embodiments of the present invention will be described below with reference to the drawings.

[First Embodiment] FIG. 1 is a block diagram of a switched capacitor circuit according to an embodiment of the present invention. Between the signal input terminal 2 and the ground terminal 3, five capacitors C ₁
Each of C ₅ to C ₅ has six MOS transistors Tr sequentially
_{1 to} Tr ₆ are connected. Capacitors C _{1 to} C
The other end of ₅ is grounded. Transistors Tr ₁ and Tr
₃ , clock φ ₂ is supplied to the gate electrodes of Tr ₅ ,
The clock φ ₁ is supplied to the gate electrodes of the transistors Tr ₂ , Tr ₄ , Tr ₆ . As shown in FIG. 2, the clocks φ ₁ and φ ₂ both have a frequency f and opposite phases. Therefore, the transistor switches Tr ₁ , Tr ₃ , Tr connected to one end of each of the capacitors C ₁ -C _5
5 and Tr _2, Tr _4, Tr ₆ are opened and closed alternately, the transistor Tr ₁ to Tr ₆ acts as a changeover switch in the prior art. When the clock φ ₁ is “H”, the transistors Tr ₂ , Tr ₄ and Tr ₆ are turned on,
When the capacitors C ₁ and C ₂ , the capacitors C ₃ and C ₄ , the capacitor C ₅ and the signal input terminal 2 are connected and the clock φ ₂ is “H”, the transistors Tr ₁ , Tr ₃ and Tr ₅ are turned on and grounded. Terminal 3, capacitor C ₁ , capacitor C ₂
And C ₃ and capacitors C ₄ and C ₅ are connected. 5
The two capacitors C _{1 to} C ₅ all have the same capacitance C. The capacitance C is as small as possible (about 1 pF) within a range that can be easily formed.

Next, the principle operation of this switched capacitor circuit will be described. In the initial state where no electric charge is stored in the capacitors C _{1 to} C ₅ , the signal input terminal 2 is connected to the power source to supply the voltage V. Then, clocks φ ₁ and φ ₂ are applied to the gate electrodes of the respective transistors Tr _{1 to} Tr ₆ , but when Tr _{1 first} becomes conductive (ON) (at this time, Tr ₃ and Tr ₅ are also ON, Tr ₂ , T
r ₄ and Tr ₆ are off. ) C ₁ is charged and CV
An amount of charge Q represented by is accumulated here. Where Q
= CV Next, when Tr ₂ becomes conductive (ON) (at this time, Tr ₄ , Tr ₆ are also ON, Tr ₁ , Tr ₃ ,
Tr ₅ is off. ), C ₁ is connected to C ₂ and C ₁
Part of the electric charge Q accumulated in C moves to C ₂ . This amount of movement is determined so that the voltage difference between both ends of C ₁ and C ₂ becomes equal. Since C ₁ and C ₂ have the same capacity C, this movement amount is Q / 2. After that, Tr ₁ , T
_{Three of} r ₃ and Tr ₅ and three of Tr ₂ , Tr ₄ , and Tr ₆ are alternately turned on, and the turned-on transistor Tr ₁
As described above, the charge moves between the two capacitors connected by ~ Tr ₆ so that the charges accumulated in the two capacitors are averaged. The initial state is set to time t = 0, and thereafter, the times are counted as t = 1, 2, ...
Table 1 shows the transition of the charges accumulated in the capacitors C _{1 to} C ₅ at t = 0 to 12 and the equilibrium state after a sufficient time has passed. In Table 1, the numbers shown in the columns C _{1 to} C ₅ are the ratios of the charges accumulated in each capacitor to the charges Q, and n is a sufficiently large natural number.

[0019]

[Table 1] Switched capacitor circuit with one conventional capacitor,
A switched capacitor circuit having five capacitors according to this embodiment will be compared. When the same voltage V is applied to both ends of the switched capacitor circuit, the amount of charge flowing per clock cycle is Q in the former case,
In the latter steady state, it is Q / 5. That is,
The current that flows in this embodiment is ⅕ of the conventional one,
The equivalent resistance value R is 5 times that of the former. That is, the resistance value in this embodiment is as follows.

R = 5 / fC (2) If the number of switched capacitors is N, the resistance value R is R = N / fC (3).

As described above, according to this embodiment, the resistance value can be increased by increasing the number of connected switched capacitors. Therefore, it is possible to obtain a large resistance which has never been obtained.

Furthermore, the resistance value R can be changed by adjusting the switching frequency f. Therefore, the effect that the absolute value of the resistance value can be set to an arbitrary value in the semiconductor integrated circuit is also obtained. That is, it is difficult to determine the absolute value of the resistance value of the diffused resistance or the like in the semiconductor integrated circuit, but in this circuit, the absolute value can be set to a desired one by adjusting the switching frequency.

[Embodiment 2] FIG. 3 is an embodiment of the present invention and is a block diagram of a signal processing circuit for converting a current signal from a photodiode into a voltage signal. The switched capacitor circuit 10 is the switched capacitor circuit shown in FIG. 1 and is the same as that described in the first embodiment.
One terminal 42 of the switched capacitor circuit 10 is grounded, and the other terminal 41 is connected to the non-inverting input terminal of the buffer amplifier 11 to which the output terminal and the inverting input terminal are connected. The photodiode 14 which is a signal generation source is connected to the non-inverting input terminal. This photodiode 14 is usually externally attached to an integrated circuit,
They may be formed in the same integrated circuit so that only this area is exposed to light.

The operation of this signal processing circuit will be described. The current signal i (t) generated by the photodiode 14 flows to the ground as the current i (t) in the switched capacitor circuit 10 to which the clocks φ ₁ and φ ₂ are applied. At this time, this causes a potential difference in the switched capacitor circuit 10 according to the equivalent resistance value R, and the voltage signal v is applied to the non-inverting input terminal of the buffer amplifier 11 on the upstream side thereof.
(t) = R · i (t) occurs. Here, the buffer amplifier 1
1 has a high impedance with respect to the non-inverting input terminal, and outputs a voltage signal having a sufficient current capacity corresponding to v (t) at the output without affecting the voltage signal v (t). That is, a slight current signal generated in the photodiode 14 can be converted into a signal having sufficient current capability.

As described in the first embodiment, the switched capacitor circuit 10 can obtain a sufficiently large resistance value while keeping the capacitance C and the switching frequency f practical.

[Third Embodiment] FIG. 4 is a block diagram of a signal processing circuit according to an embodiment of the present invention, which converts a charge signal from a photodiode into a voltage signal. The switched capacitor circuits 20 and 21 have the same configuration as that shown in FIG. This switched capacitor circuit 20, 21
Has one end grounded and the other end having buffer amplifiers 22, 2
3 are respectively connected to the non-inverting input terminals. The photodiode 25 is connected to the non-inverting input terminal of the buffer amplifier 22.
Is connected. The outputs of the buffer amplifiers 22 and 23 are two inputs of the comparator 26.

The operation of this signal processing circuit will be described. The output signal of the buffer amplifier 22 to which the photodiode 25 is connected is the same as that in the second embodiment. This output signal is
It includes switching noise and offset voltage in the switched capacitor circuit 20. Therefore, a system including a switched capacitor circuit 21 and a buffer amplifier 23 having the same configuration as the system including the switched capacitor circuit 20 and the buffer amplifier 22 except that the photodiode is not connected is provided, and the difference between the outputs of both systems is output from the comparator 26. Take it out. Switching noise generated in both systems,
Since the offset voltages are basically equal to each other, these switching noise and offset voltage can be canceled and removed from the output signal obtained at the signal terminal 28. The resistance in the circuit is for keeping the processing stable.

[0028]

Example 1 In the circuit of the embodiment shown in FIG. 4, the capacitance of the capacitors of the switched capacitor circuits 20 and 21 is set to 1 pF, the switching frequency is set to about 30 kHz, and the resistance value is set to about 100 kΩ. I actually processed. The result is shown in FIG. In this way, it is understood that suitable light-voltage conversion characteristics can be obtained.

[0029]

[Embodiment 2] FIG. 6 shows a structure of an experimental example in which a circuit similar to that of the embodiment 2 in FIG. 3 is composed of discrete components. In this example, the capacitors C _{1 to} C ₅ are 100 pF,
The signal from the AC signal source is passed through a 1 μF capacitor,
Input to the buffer amplifier 11. In an actual semiconductor integrated circuit, a capacitor C ₁ -C ₅ was employed of about 1 pF.

The buffer amplifier 11 when the frequency of the signal source is changed with the switching frequency set to 31.4 kHz
FIG. 6 shows the output state of the. Here, S in FIG.
The points of 1, S2 and S3 show the output characteristics when grounded. The gain is the ratio of the input signal level to the output signal level, and the phase is the phase difference between the input signal and the output signal.

From FIG. 7, it is understood that the resistance value is increased and the signal attenuation is decreased by increasing the number of switched capacitors. In this figure,
The transistor Tr is represented by a switch in accordance with usual notation.

[Brief description of drawings]

FIG. 1 is a circuit configuration diagram of a first embodiment.

FIG. 2 is a waveform diagram showing a switching clock.

FIG. 3 is a circuit configuration diagram of a second embodiment.

FIG. 4 is a circuit configuration diagram of a third embodiment.

5 is a light-voltage conversion characteristic diagram of Example 1. FIG.

FIG. 6 is a circuit configuration diagram of a second embodiment.

FIG. 7 is a processing characteristic diagram of the second embodiment.

FIG. 8 is a circuit configuration diagram of a conventional equivalent resistance circuit.

[Explanation of symbols]

C ₁ -C ₅ capacitors, Tr ₁ to Tr ₆ transistors, 2 signal input terminal, 3 a ground terminal, 10,20,2
1 switched capacitor circuit 11,22,23 buffer amplifier, 12 input terminals, 14,25 photodiode, 26 comparator.

Claims (3)

[Claims] 1. A first terminal or a second terminal of a capacitor, one end of which is connected to a constant voltage source
By providing a plurality of switched capacitors that are alternately connected to the terminals, and connecting the second terminal of one switched capacitor to the first terminal of the adjacent switched capacitor,
A plurality of switched capacitors are sequentially connected, the polarity of the switching of the two adjacent switched capacitors is opposite, and the capacitors of the two adjacent switched capacitors are intermittently connected to each other, and the first terminal of the first switched capacitor is connected. And a second terminal of the last switched capacitor, which acts as an equivalent resistance. 2. A signal processing circuit using the switched capacitor circuit according to claim 1, wherein a signal is input to a non-inverting input terminal and a signal is output from an output terminal to which the inverting input terminal is connected. And one end is connected to the non-inverting input end of the buffer amplifier,
An equivalent resistance circuit, the other end of which is connected to a constant voltage source, and the equivalent resistance circuit is the switched capacitor circuit according to claim 1. 3. The switched capacitor circuit according to claim 1, wherein the first and second buffer amplifiers have an inverting input terminal and an output terminal connected to each other, and one end of the first and second buffer amplifiers. The first and second equivalent resistance circuits connected to the non-inverting input terminal and the other end connected to the constant voltage source, and the outputs of the first and second buffer amplifiers are input to the two input terminals, and A differential amplifier that outputs a signal regarding the difference between the outputs of the buffer amplifiers, and the first and second equivalent resistance circuits are the switched capacitor circuit according to claim 1 having substantially the same configuration. At the same time, the signal processing circuit is characterized in that a signal is input only to one of the first and second buffer amplifiers to obtain an output signal at the output of the differential amplifier.