JPH03185915A - Switched capacitor type hysteresis comparator circuit - Google Patents

Abstract

PURPOSE:To comparate two inputs with a prescribed hysteresis width by using a capacitor for forming a feedback circuit so as to eliminate the need for a smoothing filter. CONSTITUTION:Let the voltages applied to input terminals IN1, IN2 be denoted by V1, V2 respectively and the output voltage of an inverter 2 by V0 (and output voltages of H, L levels by VOH, VOL respectively), then since one voltage across the capacitors C1, C2 is V1, an inverted input terminal voltage V<+> of an operational amplifier 1 is expressed in equation I. When the comparator output changes from VOH to VOL or from VOL to VOH respectively, equations II, III are yielded from the equation I. When the inequalities II, III are replaced into equations, the hysteresis width VTH of the comparator is obtained as equation IV. The hysteresis width is expressed by the equation replacing two resistive constants deciding the hysteresis width of an analog hysteresis comparator circuit subject to resistance voltage division into the capacitances C2, C1.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a hysteresis comparator circuit, and particularly to a switched capacitor type hysteresis comparator circuit implemented on a semiconductor integrated circuit.

[Conventional technology]

Conventionally, a circuit using a plurality of operational amplifiers is well known as a hysteresis comparator circuit in an analog circuit.

FIG. 3 is a circuit diagram of an analog hysteresis comparator showing an example of such a conventional device.

As shown in Figure 3, the conventional circuit consists of three operational amplifiers 5
7 and resistors RO to R2 are used to obtain a comparative output for the input signal. That is, the input terminal INI
When the first input signal is supplied to the resistor RO, it is amplified by the anti-phase amplifier consisting of the resistor RO and the operational amplifier 5, and this output and the second input signal supplied to the input terminal IN2 are connected to the resistor RO.
and an operational amplifier 6. This adder output is compared with analog ground in a negative phase comparator section consisting of resistors R1, R2 and operational amplifier 7.
The comparison result is output in analog form to the output terminal OUT.

FIG. 4 is a circuit diagram of a switched capacitor type hysteresis comparator showing another conventional example.

As shown in FIG. 4, this circuit is an example in which the analog circuit shown in FIG. 3 described above is used as a switched capacitor type hysteresis comparator. SW1 to SW4 are switches driven by clocks φ1 and φ2 that do not overlap with each other, CI is a capacitor, R1 and R2 are resistors, 1 is an operational amplifier, and 4 is a sample hold circuit consisting of an even number of inverters 2 and flip-flops 3. It is.

[Problem to be solved by the invention]

In the conventional analog circuit hysteresis comparator circuit described above, especially in a comparator circuit that converts a signal into 1.0 data via a switched capacitor filter on a semiconductor integrated circuit, a clock component is added to the output of the switched capacitor filter. A smoothing filter is required to remove this. This smoothing filter generally has an RC active filter configuration, but in order to realize this, the resistance and capacitor are large, and the chip area is large.In particular, if it is a two-person type, two series of smoothing filters are required. Therefore, an even larger chip area is required. Further, the RC active filter also has the disadvantage that the order becomes high when considering variations in each element. Furthermore, in order to configure a two-man-operated hysteresis comparator as shown in FIG. 3 using an analog circuit, three operational amplifiers are required, which has the drawback of increasing the circuit pattern and increasing current consumption.

On the other hand, the circuit shown in Figure 4 is a switched capacitor type hysteresis comparator circuit,
Although the above-mentioned drawbacks have been overcome, when the chip size is further reduced, there is a drawback that the resistance area forming the return path becomes larger.

[Means to solve the problem]

The switched capacitor type hysteresis comparator circuit of the present invention has one end connected to the first and second input terminals, and the other end connected in common. and a first and second switch driven by a second clock; a first capacitor having one electrode connected to the commonly connected other ends of the first and second switches; an operational amplifier whose negative phase input terminal is connected to the other electrode of the first capacitor and whose positive phase input terminal is connected to the analog ground; a third switch driven by a clock; a sample-and-hold circuit having a plurality of series-connected inverters and flip-flops connected to the output end of the operational amplifier, and whose output end is connected to the output terminal; a fourth switch whose one end is connected to the output end of the circuit and driven by the second clock; and a second capacitor connected between the other end of the fourth switch and the negative phase input terminal of the operational amplifier. and between the other end of the fourth switch and the second input terminal, or between the other end of the fourth switch, the first switch, and the first carrier.

a fifth switch connected to the connection voltage of the capacitor and driven by the first clock; the second capacitor is connected to the fifth switch through the fifth switch at the time of the first clock; It is configured to be connected to one input terminal.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram of a switched capacitor type hysteresis comparator showing a first embodiment of the present invention.

As shown in FIG. 1, in this embodiment, the switch SW
A circuit consisting of I to SW3, capacitor CI, and operational amplifier 1 is a comparator section.

A clock φ that drives these switches 5WI-8W3
1 and clock φ2 are provided with a slit so that they do not overlap each other, and the circuit malfunctions due to this slit. Therefore, a sample and hold circuit 4 consisting of an even number of inverters 2 and a flip-flop circuit 3 is added to the output of the comparator section to hold the input value at the time of clock φ1. Further, the switch SW4.5 and the capacitor C2 form a feedback path from the sample and hold circuit 4. Therefore, if the output of this sample-and-hold circuit 4 is set as the output terminal OUT, and if the capacitor C2 and switch SW4゜5 in Fig. 1 are removed, a comparator circuit with opposite phase will be formed between the input terminal INI and the output terminal OUT. become.

Next, the operation of such a comparator circuit will be explained.

First, the voltage applied to the input unit INI in FIG. 1 is Vl, the voltage applied to the input terminal IN2 is V2%, and the output voltage of the inverter 2 is V. (High level output voltage V.H
: Low level output voltage■. L), the clock φ2
The charges Q1 and C2 charged in capacitors C1 and C2 respectively at the time are Q1=01(V2 VA.)
・・・・・・(1)Q2=02 (Vo
VAG) ...(2).

On the other hand, at clock φ1, capacitor C1 and capacitor C3 are connected in parallel, so the charge Q is Q=Q++Q2
=C+ (V2 VAO) +02 (VOVAG)・
...(3) becomes. Moreover, the voltage (■) between the electrodes of the capacitors c1 and C2 can be expressed as follows.

Here, since the voltage of one electrode of capacitors C1 and C2 is vl, the negative phase input terminal voltage of operational amplifier 1 -
is, V-=V, -V (5>) Therefore, from equation (5), 9- (6) is obtained.

On the other hand, since such a circuit is a comparator, v---v
When Ao>o, V o = VOL...
...(7) When V--VA, <O, V o =
V on ......(8).

Here, ■. . →■. If the output changes to 1, (6)
From the formula, ......(9) Here, V2<V. , Therefore, V 1'> V 2...
...(10) Next, VOL→■. If the output changes to 8, from equation (6), ......(11) Here, V2>V. 1, therefore, ■1″<V2 (1
2) Here, if the inequality signs in equations (9) and (11) are replaced with equality, the hysteresis width of the comparator ■T□
is found.

C6 (13) This hysteresis width is determined by setting R1 to 0 for the resistance constants R1 and R2 that determine the hysteresis width of the conventional analog hysteresis comparator circuit that divides the voltage by resistors as shown in Figure 3.
2. It is expressed by a formula in which R2 is replaced with 01.

FIG. 2 is a circuit diagram of a switched capacitor type hysteresis comparator showing a second embodiment of the present invention.

As shown in FIG. 2, this embodiment has the same basic configuration as the first embodiment described above, except that the number of inverters is an odd number, and the fifth switch SW5 is replaced with the first switch SW5. This is because it is placed at the connection point between the switch SWI and the first capacitor C1.

Also in this case, the second capacitor C2 is connected to the first input terminal IN1 during the period of the first clock φ1.

〔Effect of the invention〕

As explained above, the switched capacitor type hysteresis comparator circuit of the present invention uses a capacitor to form a feedback path, so that compared to analog hysteresis comparator circuits, the switched capacitor type hysteresis comparator circuit of the present invention can be used as a switched capacitor on a semiconductor integrated circuit. When comparing capacitor filter output signals, a smoothing filter is not required,
Moreover, it has the effect of being able to compare the power of two people with a certain hysteresis width. Furthermore, compared to conventional switched capacitor type hysteresis comparator circuits, the present invention does not require a resistor, so it has the effect of reducing the chip area.

[Brief explanation of drawings]

Fig. 1 is a circuit diagram of a switched capacitor type hysteresis comparator showing a first embodiment of the present invention, Fig. 2 is a similar circuit diagram showing a second embodiment of the invention, and Fig. 3 is a conventional example. FIG. 4 is a circuit diagram of a switched capacitor type hysteresis comparator showing another conventional example. l...Operational amplifier, 2...Even stage inverter, 3...Flip-flop, 4...
・・Sample hold circuit, INI, IN2・・・・
・Input terminal, OUT...Output terminal, C,, C2
...Capacitor, SW1~SW5...
Switch, φ1. φ2...Clock.

Claims (1)

[Claims] first and second switches each having one end connected to the first and second input terminals, the other end connected in common, and driven by first and second clocks that do not overlap with each other; a first capacitor having one electrode connected to the commonly connected other ends of the first and second switches; and a negative phase input end connected to the other electrode of the first capacitor and connected to analog ground. an operational amplifier to which a positive phase input terminal is connected; a third switch connected between the output terminal of the operational amplifier and the negative phase input terminal and driven by the second clock; and a third switch connected to the output terminal of the operational amplifier. a sample-and-hold circuit having a multi-stage series-connected inverter and a flip-flop and having an output terminal connected to an output terminal; one end of the sample-and-hold circuit is connected to the output terminal of the sample-and-hold circuit and is driven by the second clock; a fourth switch, a first capacitor connected between the other end of the fourth switch and the negative phase input terminal of the operational amplifier, and a first capacitor connected between the other end of the fourth switch and the first input terminal; a fifth switch connected between the other end of the fourth switch and a connection point between the first switch and the first capacitor and driven by the first clock; A switched capacitor type hysteresis comparator circuit, wherein the switched capacitor type hysteresis comparator circuit is connected to the first input terminal via the fifth switch at the time of the first clock.