JP2570199B2 - Switched capacitor circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a switched capacitor circuit, and more particularly to a switched capacitor circuit having excellent noise characteristics.

[0002]

2. Description of the Related Art As an example of a conventional switched capacitor circuit, referring to FIG.
The configuration of the analog conversion circuit will be described.

[0003] As shown in FIG. 4, 1-bit input digital-analog converter circuit includes a switch SW1 to SW4, a capacitor C ₁ -C _3, is composed of a operational amplifier, and operates as a low pass filter .

Next, the operation of the switched capacitor circuit will be described with reference to FIG.

[0005] In FIG. 4, the switch SW1~SW4 repeats on and off by a predetermined clock signal of a frequency (sampling frequency) (not shown), the capacitive element C ₁ -C ₃
Switch the contact to which the terminal is connected.

More specifically, the switches SW1 to SW4 of the switched capacitor circuit are, for example, two-phase clock signals φ
₁ and φ ₂ (not shown), the opening and closing of which are controlled. For example, when the clock signal φ ₁ is on, the input capacitance element C ₁
One side of the terminal connected to the input signal V _i of, as the clock signal phi ₂ is the terminal of said one side of the input capacitor element C ₁ in the on state is connected to the internal ground, the switch SW1 is switched control Is done.

At the timing when the switches SW1 to SW4 are in the state shown in FIG. 4A, the total amount q (n-1) of the electric charge stored in the inverting input terminal of the operational amplifier is given by the following equation (1). .

Q (n-1) =-V _o (n-1) C ₃ (1)

[0009] In the above formula _{(1), V o (n} -1) , the output voltage of the operational amplifier at the timing switch SW1~SW4 is in the state shown in FIG. 4 (A) (n-1 ), C 3 is ,
It represents the capacitance of the capacitor C ₃ to the output terminal and connected between the inverting input terminal of the operational amplifier.

[0010] That is, at the timing (n-1), as shown in FIG. 4 (A), one side of terminals of the input capacitor element C ₁ is connected to the input signal V _i by a switch SW1,
The other side of the terminal of the input capacitance element C ₁ is connected to the internal ground by the switch SW2, also, both terminals of the capacitor C ₂ is opened by the switch SW3, SW4. The inverting input terminal of the operational amplifier is connected to the output terminal via a capacitor C ₃ to form a feedback path. The non-inverting input terminal of the operational amplifier is always connected to the internal ground potential.

At the next timing (n-1 / 2), the total amount of charges stored in the inverting input terminal of the operational amplifier is given by the following equation (2). At this timing, the connection of the switches SW1 to SW4 changes to the state shown in FIG. The timing (n-1 / 2) is the same as the timing (n
-1) and an intermediate position between the timing (n).

[0012]

(Equation 1)

In the above equation (2), V _i (n-1) is the input signal voltage V _o (n-1 / 2) at the timing (n-1).
The output voltage, C ₂ of the operational amplifier at the timing (n-1/2), as shown in FIG. 4 (B), connected in parallel with the output terminal of the operational amplifier and the capacitance element C ₃ between the inverting input terminal it represents the capacitance of the capacitor C ₂ to be.

At timing (n-1 / 2), FIG.
(B), the one side of the terminal of the input capacitance element C ₁ is connected to the internal ground by the switch SW1, the other side of the terminal of the input capacitance element C ₁ to the inverting input terminal of the operational amplifier by the switch SW2 connected, the capacitor C ₂ is connected in parallel to form the capacitor C ₃ through the switch SW3, SW4. The inverting input terminal of the operational amplifier is connected to the output terminal via capacitive elements C ₂ and C ₃ forming a feedback path.

Referring to FIG. 4B, the timing (n-
In (1/2), the charge −V _i (n−1) C ₁ charged in the input capacitive element C ₁ by the input signal voltage V _i (n−1) is input to the inverting input terminal of the operational amplifier, and The electric charges charged in _two capacitors C ₂ and C ₃ connected in parallel between the output terminal of the amplifier (the output voltage is V _o (n-1 / 2)) and the inverting input terminal (the potential is the internal ground potential) The added charges are accumulated.

Further, at the next timing (n), there is no change in the output voltage of the operational amplifier. That is, the following equation (3) holds.

V _o (n) = V _o (n-1 / 2) (3)

Therefore, the above equation (3) is substituted into the above equation (2), and the following equation is obtained.
Obtain (4).

[0019]

(Equation 2)

On the other hand, since the following equation (5) is satisfied from the law of conservation of charge, the following equation (6) is obtained from the above equations (1) and (4).

Q (n-1) = q (n-1 / 2) (5)

[0022]

(Equation 3)

Here, with respect to the above equation (6), the following equation (7) is obtained by Z-transforming both sides.

[0024]

(Equation 4)

That is, the transfer function of the circuit shown in FIG.
When expressed in terms of display, the following equation (8) is obtained.

[0026]

(Equation 5)

Next, consider the frequency characteristics of the switched capacitor circuit of FIG. The frequency characteristic of the transfer function H (Z) given on the Z plane (see the above equation (8)) is expressed by the following equation:
It is obtained by setting to (9).

Z = exp (j2πf / fs) (9)

Here, j ² = −1, f is the signal frequency, and fs is the sampling frequency.

Then, in the case of direct current, Z = 1 (ie,
The signal frequency f = 0) may be set. In this case, the above equation (8)
More, the output voltage V _o is expressed by the following equation (10), and the output signal that level is determined by the ratio of the C ₁ and C _2.

V _o = − (C ₁ / C ₂ ) V _i (10)

It is also easily calculated that the output voltage decreases as the frequency increases, and it is confirmed that the circuit shown in FIG. 4 is a low-pass filter.

Here, as shown in FIG.
When 1 is switched to the input signal V _i side, the input capacitive element C _1, with the switching side, the charge of q = -C ₁ V _i is charged. Then, when the switch is made in the opposite direction (that is, on the internal ground side), this charge is discharged.

[0034] Therefore, the power supply supplies the internal ground voltage to a switched capacitor circuit, the 1 / fs (= sampling period) of time will flow charge of -C ₁ V _i, per unit time, -fsC average current of ₁ V _i flows. Here, fs is a sampling frequency.

Since this current contains high frequency noise, the noise characteristic of the internal ground voltage is degraded, and the noise characteristic of the switched capacitor circuit is degraded.

[0036]

As described above, in the conventional switched-capacitor circuit, current flows out and in from a power supply that supplies an internal ground voltage due to charging and discharging of a capacitive element. Therefore, there is a problem that the noise characteristic of the internal ground voltage is deteriorated because of the noise.

Accordingly, an object of the present invention is to solve the above-mentioned problems and to provide a switched capacitor circuit having excellent noise characteristics.

[0038]

According to the present invention, there is provided a switched capacitor circuit including at least a switch, a capacitor, and an operational amplifier.
Means for flowing in and out of the power supply at the same timing with the same amount of current having the opposite polarity as that of a current flowing out and flowing from a power supply for providing an internal ground potential to the switched capacitor circuit. Providing a capacitor circuit;

Further, the present invention relates to a switched capacitor circuit (hereinafter, referred to as a "first switched capacitor circuit") including at least a switch, a capacitance element, and an operational amplifier. (Referred to as “second switched capacitor circuit”), and providing a signal obtained by inverting an input signal of the first switched capacitor circuit as an input signal of the second switched capacitor circuit. A featured switched capacitor circuit is provided.

In the present invention, preferably, the capacitance value of the input capacitance element of the second switched capacitor circuit is equal to the capacitance value of the input capacitance element of the first switched capacitor circuit. I do.

Further, as another preferred embodiment, the present invention provides a switched capacitor circuit ("first switched capacitor") including at least a switch, a capacitance element, and an operational amplifier and commonly inputting one input signal. A plurality of switched capacitor circuits (referred to as “second switched capacitor circuits”), and the input signal of the first switched capacitor circuits is inverted. Providing a signal as an input signal to the second switched capacitor circuit;
Wherein the capacitance value of the input capacitance element of the switched capacitor circuit is equal to the sum of the capacitance values of the input capacitance elements of the plurality of first switched capacitor circuits. .

[0042]

According to the present invention, at the time of switching, the current flowing from the power supply supplying the internal ground voltage to the switched capacitor circuit is canceled with the same current value and the same timing in reverse polarity so as to cancel the current. Since the current flows from the power supply that supplies the internal ground voltage to the provided switched capacitor circuit, the sum of the currents becomes zero, and the good noise characteristics can be maintained without being affected by the charging / discharging current due to switching. it can.

[0043]

Next, the present invention will be described with reference to the drawings.

[0044]

Embodiment 1 FIG. 1 is a diagram showing the configuration of a first embodiment of the switched capacitor circuit of the present invention.

Referring to FIG. 1, in this embodiment, in addition to a switched capacitor circuit 1 composed of a switch, a capacitance element, and an operational amplifier, a switch, a capacitance element, and an operational amplifier Another switched
A capacitor circuit 2 is provided, and a signal obtained by inverting an input signal to the switched capacitor circuit 1 is input to the switched capacitor circuit 2. Note that the switched capacitor circuits 1 and 2 have the same configuration as the conventional switched capacitor circuit described in detail with reference to FIG.

Next, the operation of this embodiment will be described with reference to FIG.

The current flowing from the power supply that supplies the internal ground voltage to the switched capacitor circuit 1 is, as described above,
−fsC ₁ V _i (where fs is the sampling frequency and V _i
Is the input signal voltage, and C ₁ is the capacitance value of the input capacitance element C ₁ ). Similarly, the current flowing from the power supply that supplies the internal ground voltage to the switched capacitor circuit 2 is fsC ₁
V _i .

Therefore, the sum of the currents flowing from the power supply for supplying the internal ground voltage becomes zero, and the sum is completely canceled.

Therefore, in this embodiment, the noise characteristic of the power supply for supplying the internal ground voltage can always maintain a good noise characteristic regardless of the charging / discharging current due to switching.

Although the above description has been made on the average current, the transient current is similarly canceled.

In this embodiment, the circuit for inverting a signal is composed of, for example, an inverting amplifier including an operational amplifier and a resistor as shown in FIG. 2, when the resistance value of the resistor R _i and a feedback resistor R _f identical, from the output of the operational amplifier, a signal whose polarity is inverted is obtained with the same amplitude and the input signal.

[0052]

Embodiment 2 FIG. 3 is a diagram showing a second embodiment of the switched capacitor circuit of the present invention.

Referring to FIG. 3, this embodiment is composed of a switch, a capacitor, and an operational amplifier, and is a switched-capacitor circuit 1 or 2 for commonly inputting an input signal.
In addition to the above, another switched capacitor circuit 3 including a switch, a capacitance element, and an operational amplifier is provided, and the switched capacitor circuit 3 includes the switched capacitor circuit 1 and 2 is input. Here, the configuration of the switched capacitor circuits 1 and 2 is the same as that of the conventional example described with reference to FIG. 4, and includes input capacitance elements C ₁ and _Ca , respectively.

As shown in FIG. 3, the switched capacitor circuit 3 has input capacitance elements C ₁ and C _a connected in parallel.

In the configuration shown in FIG. 3, the currents flowing from the power supplies for supplying the internal ground voltages to the switched capacitor circuits 1 and 2 are -fsC, respectively, as described above.
₁ V _i, the -fsC _a V _i.

The current flowing from the power supply for supplying the internal ground voltage to the switched capacitor circuit 3 is fsC ₁
The V _i + fsC _a V _i.

Accordingly, the sum of the currents flowing from the power supply for supplying the internal ground voltage becomes zero, and is completely canceled. In this manner, the noise characteristics of the power supply that supplies the internal ground voltage can maintain good characteristics regardless of the charging / discharging current due to switching.

The circuit for inverting the signal can be constituted by a circuit as shown in FIG. 2, as in the first embodiment.

[0059]

As described above, according to the switched-capacitor circuit of the present invention, the current flowing from the power supply for supplying the internal ground voltage can be made zero, so that the switching charge-discharge current caused by the switching can be reduced. However, there is an effect that good noise characteristics can be maintained.

Further, according to the switched capacitor circuit of the present invention, the charge / discharge current at the time of switching is canceled out to zero by a simple configuration in which an inverting circuit and a switched capacitor circuit are added. This has the effect of suppressing components and greatly reducing noise.

Further, in the present invention, the switched
Also in a circuit having a plurality of capacitor circuits, a signal obtained by inverting the input signal of the switched capacitor circuit is provided as an input signal, and the input capacitor has an input capacitance equal to the sum of the input capacitances of the plurality of first switched capacitor circuits. By providing a separate switched capacitor circuit,
The current flowing out of the power supply that supplies the internal ground voltage is reduced to zero, so that good noise characteristics can be maintained irrespective of the charging / discharging current due to switching.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a first embodiment of a switched capacitor circuit according to the present invention.

FIG. 2 is an example of a signal inversion circuit.

FIG. 3 is a diagram showing a configuration of a second embodiment of the switched capacitor circuit according to the present invention.

FIG. 4 is a diagram showing a configuration of a conventional switched capacitor circuit.

[Description of sign]

C _1, C _a capacitance (input capacitance element) C _2, C ₃ capacity SW1~SW4 switch V _i input signal voltage V _o the output signal voltage

Claims (4)

(57) [Claims] In a switched capacitor circuit including at least a switch, a capacitor, and an operational amplifier, a current flowing in and out of a power supply for supplying an internal ground potential to the switched capacitor circuit is opposite in polarity. A switched capacitor circuit comprising means for flowing the same amount of current into and out of the power supply at the same timing. 2. A switched-capacitor circuit including at least a switch, a capacitor, and an operational amplifier.
Switch-capacitor circuit ").
A switched capacitor circuit (referred to as a “second switched capacitor circuit”), and a signal obtained by inverting an input signal of the first switched capacitor circuit is input to the second switched capacitor circuit. Switched, characterized by being given as a signal
Capacitor circuit. 3. The capacitance value of the input capacitance element of the second switched capacitor circuit is equal to the capacitance value of the input capacitance element of the first switched capacitor circuit. Switched capacitor circuit. 4. A circuit provided with a plurality of switched capacitor circuits (referred to as "first switched capacitor circuits") including at least a switch, a capacitor, and an operational amplifier and commonly inputting one input signal. In addition, a switched capacitor circuit (referred to as “second switched capacitor circuit”) is provided, and a signal obtained by inverting an input signal of the first switched capacitor circuit is supplied to the second switched capacitor circuit. The capacitance value of the input capacitance element of the second switched capacitor circuit is equal to the sum of the capacitance values of the input capacitance elements of the plurality of first switched capacitor circuits. Characterized switched capacitor circuit.