JP3450246B2 - DA conversion circuit and charge / discharge method thereof - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a DA conversion circuit and a charging / discharging method thereof, and in particular, a digital signal generated by a voltage dividing circuit is stored as an analog signal in an integrator while maintaining a differential condition. The present invention relates to a DA conversion circuit such as an SC circuit and a charging / discharging method thereof.

[0002]

2. Description of the Related Art A DA converter circuit is accompanied by an SC (switched capacitor) circuit. The DA conversion circuit is a circuit that converts a digital signal into an analog signal, and integrates / accumulates a voltage that is specified for one of the number of pulses corresponding to the absolute value and that is output in the capacitor, and then integrates the integration. A voice generation circuit of an audio device that outputs a value is exemplified. Therefore, high speed response is required for such an SC circuit that requires real-time output. S
A buffer circuit is attached to the C circuit. From the buffer circuit, as shown in FIG. 6, the voltage VP, which is divided by the resistors R1, R2, R3, and R4 of the voltage dividing amplifier,
VC and VN are output. The voltages VP, VC, VN are
It is input to the SC circuit and used as a charging / discharging voltage for the two switched capacities of the SC circuit. S formed by two elements 101 and 102 having a capacitive load C
By switching the switch of the C circuit, as shown in FIG. 7A, charging of the elements 101 and 102 and
As shown in (b), the discharges from the elements 101 and 102 are alternately repeated.

During charging shown in FIG. 7A, the TOP plates of the capacitive load elements 101 and 102 are connected to the VC voltage terminal, and the BOTTOM plate is connected to the VP voltage terminal and the VN voltage terminal. At this time, the amount of charge accumulated in each of the capacitive elements 101 and 102 is C (VP-VC) and C (VN-VC). During the discharge shown in FIG. 7B, the capacitive elements 101, 10
The two TOP plates and the BOTTOM plate have the same potential VC. Then, the state of FIG. 7B is returned to the state of FIG. The charge is supplied at the moment when the state returns in this way. That is, with respect to the BOTTOM plate of the capacitive element 101, the potential VC to the potential VP is increased.
BOTTO of the capacitor 102 due to the change in potential
For the M plate, there is a potential change that changes from the potential VC to the potential VN. During this potential change, each capacitive element 101,
The current Δi flowing through 102 is applied to each buffer amplifier 1
03, 104, 105 supply promptly. Similarly, even in the state of FIG. 7B, the potential fluctuation generated in the BOTTOM plate can be quickly suppressed.

Since the electric charge cannot be supplied at a high speed only with the voltage dividing amplifier, the buffer amplifiers 103, 104, 10 are connected to the VP and VN so that the potential changes rapidly.
5 connections were required. The existence of such a buffer amplifier has led to an increase in the number of constituent elements. In addition to such a problem that the number of constituent elements increases, the differential condition: (VP + VN) is affected by the offset of the buffer amplifiers 103 and 105 in which the SC circuit is separately provided for VP and VN. = 2VC) is apt to collapse, and the problem remains.

A reduction in the number of elements is desired. Furthermore, it is desired to provide a DA conversion circuit such as a buffer circuit for SC circuit that maintains a differential condition and maintains high speed.

[0006]

An object of the present invention is to provide a DA conversion circuit capable of reducing the number of elements and a charging / discharging method thereof. Another object of the present invention is to maintain a differential condition and maintain high speed.
An object is to provide an A conversion circuit and a charging / discharging method thereof.

[0007]

Means for solving the problem Means for solving the problem are expressed as follows. The technical matters appearing in the expression are accompanied by parentheses (), and numbers, symbols and the like are added. The numbers, symbols and the like are technical matters constituting at least one embodiment or plural examples of the embodiments or plural examples of the present invention, particularly the embodiment or examples. It corresponds to the reference numbers, reference symbols, etc. attached to the technical matters expressed in the drawings corresponding to. Such reference numbers and reference symbols clarify correspondences and bridges between the technical matters described in the claims and the technical matters of the embodiments or examples. Such correspondence / bridge does not mean that the technical matters described in the claims are limited to the technical matters of the embodiment or the examples.

The DA converter circuit according to the present invention includes a voltage dividing circuit (2) and an SC circuit (20), and the voltage dividing circuit (2) is provided.
Is a first resistor (6), a second resistor (7) and a third resistor (8)
Is divided into a first voltage, a second voltage and a third voltage by
The C circuit (20) includes a first capacitor (17), a second capacitor (18), and a switching circuit. The switching circuit alternately forms a first connection circuit and a second connection circuit, and the first connection circuit is , The first voltage to the first capacitor (1
7) connected to one pole of the second capacitor (18), and the third voltage connected to the other pole of the first capacitor (17), and the second voltage connected to one pole of the second capacitor (18). The third voltage is connected to the other pole of the second capacitor (18), the second connection circuit connects the third voltage to one pole of the first capacitor (17), and the third voltage is connected to the second capacitor (18). 1), a buffer amplifier is not provided in the first connection line connecting the voltage dividing circuit (2) and the first capacitor (17), and the voltage dividing circuit (2) No buffer amplifier is provided on the second connecting line connecting to the second capacitor (18).

From the switch group, switches (13-1, 2,
Alternate formation of the first connection circuit and the second connection circuit formed by selecting ON / OFF of 14-1 to 4, 15-1, 2, 16-1, 2) is performed periodically. The virtual current Δi flowing through the voltage dividing circuit during charging does not pass through the amplifier, and therefore the operating condition is maintained in good condition.

The first voltage is represented by VP and the second voltage is VN
And the third voltage is represented by VC, and the formula: VP + VN =
2VC is satisfied. Furthermore, the formula: VP = VN + 2r
(I−Δi), VN = RI is satisfied, where r is
The resistance value of the first resistor (6) that generates a voltage between the first voltage and the third voltage, and r is the second resistor (6) that generates a voltage between the third voltage and the second voltage. 7), R is the resistance of the third resistor (8) that generates the second voltage, and the first resistor (6), the second resistor (7), and the third resistor (8) are in series. I is a current flowing through the first resistor (6), the second resistor (7) and the third resistor (8), and Δi
A first resistor (6) from the second capacitor (18) to the first capacitor (17) when the first connection circuit is formed.
And a virtual current flowing through the second resistance (7).

The SC circuit (20) further includes a buffer amplifier (12), and the buffer amplifier (12) is interposed in the third connection line where the third voltage is generated. Third
The output terminal of the connection line includes an output-side terminal of the buffer amplifier (12) and an input-side terminal of the buffer amplifier (12). Since the buffer amplifier (12) does not affect the differential condition, there is no inconvenience because it remains as a known device.

The DA conversion circuit according to the present invention includes a first capacitor (17), a second capacitor (18), and a voltage dividing circuit (2), and the voltage dividing circuit (2) includes the first capacitor (1).
7) is supplied with the first voltage VP, the voltage dividing circuit (2) further supplies the second voltage to the second capacitor (18), and the voltage dividing circuit (2) has the first voltage and the second voltage. Differential voltage V between
C is generated and a differential condition represented by the following equation: VP + VN = 2
When the VC is satisfied and the battery is charged, the first capacitor (17)
One pole of the first capacitor (1) and one pole of the second capacitor (18) are connected via the voltage dividing circuit (2), and the first capacitor (1
7) The other pole of the second capacitor is connected to the other pole of the second capacitor, and at the time of discharging, the one pole of the first capacitor (17) and the one pole of the second capacitor (18) share the differential voltage VC and are charged. Sometimes, no buffer amplifier is provided on the connection line connecting the one pole of the first capacitor (17) and the one pole of the second capacitor (18).

At the time of charging, a charging current flows through the voltage dividing circuit (2), and the same virtual current Δi flows from one pole of the first capacitor (17) to one pole of the second capacitor (18) in the opposite direction of the charging current. Flow to. The resistance of the voltage dividing circuit (2) is set smaller so that the charging is performed at high speed. Furthermore, S
Including a C circuit (20), a first capacitor (17) and a second capacitor (17)
The capacitor (18) is connected to the SC circuit (20).

The charging method of the DA converter circuit according to the present invention is as follows.
Supplying the first voltage VP to one pole of the first capacitor (17), and supplying the second voltage VN to one pole of the second capacitor (18).
The second pole of the first capacitor (17)
Supplying the third voltage VC to the other pole of the capacitor (18), satisfying the differential condition represented by the following equation: VP + VN = 2VC, and the one pole and the second pole of the first capacitor (17).
Connecting one pole of the capacitor (18) at the time of charging via the voltage dividing resistor (2) without passing through the amplifier. Furthermore,
During charging, a virtual common current flows from the first capacitor (17) to the second capacitor (18) via the voltage dividing resistor.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Corresponding to the figures, in the embodiment of the DA converter circuit according to the present invention, a power supply circuit is provided together with a voltage dividing circuit. The power supply circuit 1 is connected to a voltage dividing circuit 2 as shown in FIG. The power supply circuit 1 is
A power supply (example: operational amplifier) 3 that is commonly used as a power supply of a known buffer circuit or a known SC (switched capacitor) circuit including the buffer circuit is provided. The power source 3 is connected to a power source resistor 4, the power source resistor 4 is connected in series to a power source resistor 5, and the power source resistor 5 is connected to a reference voltage terminal (earth terminal). The voltage between the power source resistor 4 and the power source resistor 5 is feedback-connected to the power source 3.

The voltage dividing circuit 2 includes a first resistor 6 and a second resistor 7.
And a third resistor 8. The first voltage VP, which is the output voltage of the power supply 3, is applied to the first resistor 6. First resistor 6
Generates the third voltage VC by dividing the first voltage VP.
The second resistor 7 divides the third voltage to generate the second voltage VN. The third voltage is a potential between the first resistor 6 and the second resistor 7. The second voltage is a potential between the second resistor 7 and the third resistor 8. The third resistor 8 is connected to the ground terminal.

The voltage divider circuit includes a first voltage VP and a third voltage VC.
And the second voltage VN is output as it is to the SC circuit in the subsequent stage described later. The third voltage VC is applied to the first output terminal line 9 and the second output terminal line 9.
It is output to the output terminal line 11 in two ways. First output terminal line 9
The third voltage VC output to the buffer amplifier 1
The voltage is output as a third voltage VC ′ via 2. As the voltage output to the second output terminal line 11, the third voltage VC is output as it is.

FIG. 2 shows an SC circuit 20 including a switch circuit.
And the analog output circuit 30. SC circuit 20
Is connected to the analog output circuit 30. The switch circuit consists of two φ1 switches 13-1 and 13 and four φ2 switches.
Switches 14-1 to 4 and two P switches 15-1,
2 and two N switches 16-1 and 16-2.
The SC circuit includes a first capacitor 17 and a second capacitor 18.
Connected to them to include and.

The first capacitor 17 is a P switch 15-
1 and the φ2 switch 14-3. The second capacitor 18 is provided between the N switch 16-2 and the φ2 switch 14-4. φ2 switch 14
-1 is provided between one pole of the first capacitor 17 and the voltage line of the third voltage VC. φ2 switch 14-2
Is interposed between one pole of the second capacitor 18 and the potential line of the third voltage VC.

The φ2 switch 14-3 is connected between the other pole of the first capacitor 17 and the analog output circuit 30. The φ2 switch 14-4 is connected between the other pole of the second capacitor 18 and the analog output circuit 30. The N switch 16-1 is provided between the potential line of the second voltage VN and one pole of the first capacitor 17. N switch 1
6-2 is a potential line of the first voltage VP and the second capacitor 18
It is installed between one pole.

FIG. 3 shows two φ1 switches 13-1 and 13-2.
Shows the equivalent circuit at the time of charging, which is formed when the four φ2 switches 14-1 to 14-4 are opened and the two P switches 15-1 and 15-2 are closed. As shown in the equivalent circuit at the time of charging, one pole (BOTTO) of the first capacitor 17 is
The first voltage VP is applied to M) and the second capacitor 18
The second voltage VN is applied to one pole (BOTTOM) of
The third voltage VC is applied to the other pole (TOP) of the first capacitor 17 and the other pole (TOP) of the second capacitor 18.

At the time of this charging, the following equation holds. VP = VN + 2r (I−Δi), VN = R (I−Δi + Δi) = RI. Here, the resistance value of the first resistor 6 and the resistance value of the second resistor 7 are the same, both these resistance values are represented by r, and the third resistor 8
The resistance value of is represented by R. A current I flows between the potential line of the first voltage VP and the ground terminal (= zero voltage).
I = VP / (2r + R). In the differential circuit shown in FIG. 3, the following equation is established. VP + VN = 2VC.

Virtual current Δ toward the first capacitor 17
i flows in, and the virtual current Δi ′ from the second capacitor 18
Flows out. As for the current I supplied from the power source 3, the virtual current Δi flows into the first capacitor 17, so
The current flowing through 7 decreases to (I-Δi). The virtual current Δi ′ flowing out from the second capacitor 18 flows toward the ground terminal. Therefore, the current flowing through the third resistor 8 is (I−Δi + Δi ′). From the circuit configuration,
= Δi '. Therefore, regarding the current flowing through the third resistor 8,
(I−Δi + Δi) = I.

The above-described virtual current flow is circuitally equivalent to the flow in the virtual circuit in which the virtual current Δi flowing out from the second capacitor 18 flows into the first capacitor 17 via both resistors 7 and 6. is there. In such a virtual circuit, the buffer amplifier provided in the known circuit is not provided.
Since the values of both resistors 6 and 7 can be set appropriately small, the virtual current immediately converges to zero. It takes a short time to converge and the circuit operation is quick. Moreover, the virtual circuit having no buffer amplifier does not have a factor that makes the differential condition unstable by the buffer amplifier.

FIG. 4 shows four φ2 switches 14-1 to 14-4.
Shows the equivalent circuit at the time of discharging when two φ1 switches 13-1 and 13-2 are opened and two P-switches 15-1 and 13-2 are opened. As shown in the equivalent circuit at the time of discharging, the third voltage VC is applied to one pole of the first capacitor 17, the third voltage VC is applied to one pole of the second capacitor 18, and the first capacitor 17 Second pole and second capacitor 1
The other pole of 8 is connected to the analog output circuit 30.

A virtual current Δi flows out from the first capacitor 17, and a virtual current ΔI 'flows out from the second capacitor 18. In this case, Δi + Δi ′ = 0. The short circuit between the one pole of the first capacitor 17 and the one pole of the second capacitor 18 causes the virtual current to disappear quickly, and the discharge is instantly completed.

FIG. 5 shows φ1 switches 13-1 and 13 and φ2.
The time chart of the switching of the switches 14-1 to 4, the P switches 15-1 and 2 and the N switches 16-1 and 16-2 is shown. At the time position I, the circuit in the charged state shown in FIG. 3 is formed. The φ1 switches 13-1, 2 are closed, and the other pole of the first capacitor 17 and the second capacitor 1
The other pole of 8 is short-circuited to the potential line of the third voltage VC, the potential line of the first voltage VP is connected to one pole of the first capacitor 17, and the one pole of the second voltage VN is connected to one pole of the second capacitor 18. The potential line is connected. At the time position I, the differential voltage between the first voltage VP and the second voltage VN charges the first capacitor 17 and the second capacitor 18 with electric charges corresponding to those voltages, respectively.

At time position II, the discharge circuit shown in FIG. 4 is formed. φ1 switch 13-1, 2
Open, the four φ2 switches 14-1 to 4-4 are closed, the P switches 15-1 and 2 are closed, and the other pole of the first capacitor 17 and the other pole of the second capacitor 18 are analog output circuit 30.
And the one pole of the first capacitor 17 is connected to the first voltage VP.
Is disconnected from the potential line of the second capacitor 18, and one pole of the second capacitor 18 is disconnected from the potential line of the second voltage VN.

At time position II, the electric charges on the one pole side of the first capacitor 17 and the second capacitor 18 cancel each other at the time position I, but the electric charges on the other pole side of the first capacitor 17 and the second capacitor 18 are the φ2 switch 14-3 and the φ2 switch 14. -4 and 4 respectively independently flow into the analog output circuit 30. As a result of the occurrence of the current voltage corresponding to the inflowing electric charges, the analog output circuits 30 are independently charged. Due to the discharging of the SC circuit 20 and the charging of the analog output circuit 30 as described above, as shown in FIG. 5, the charge of one time (a half cycle period) of the SC circuit 20 is charged.
Over one period (time position II and time position III). Such positive and negative integration is executed for 3 cycles (from time position II to time position VII).

The circuit configuration of the time position VII differs from the circuit configuration of the time position I in that the on / off relations of the P switches 15-1, 2 and the N switches 16-1, 2 are reversed. Both integrals of the analog output circuit 30 from the time position II to the time position VII are inverted and inversely integrated.

In this way, the switching circuit in the SC circuit is alternately formed as the first connection circuit and the second connection circuit, and the charging and discharging are alternately repeated, and the first connection circuit is
The first voltage is connected to one pole of the first capacitor, and the third voltage
The voltage is connected to the other pole of the first capacitor, the second voltage is connected to one pole of the second capacitor, and the third voltage is connected to the other pole of the second capacitor. The second connection circuit is the third
The voltage is connected to one pole of the first capacitor and the third voltage is connected to one pole of the second capacitor.

No buffer amplifier is provided on the first connecting line connecting the voltage dividing circuit and the first capacitor, and the buffer is also provided on the second connecting line connecting the voltage dividing circuit and the second capacitor. No amplifier is installed. in this way,
The DA converter formed by the voltage divider circuit and the charge / discharge circuit, which does not have the buffer amplifier that makes the differential condition unstable, maintains the differential condition well, and the charge / discharge cycle is increased by the quick self-discharge in the circuit. It realizes integral calculation that can be shortened and has a high operation speed.

[0033]

In the DA converter circuit and the charging / discharging method thereof according to the present invention, the virtual current generated inside is discharged without passing through the amplifier, so that the number of elements can be reduced. , Excellent in maintaining differential conditions and maintaining high speed.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of a voltage divider circuit of a DA conversion circuit portion according to the present invention.

FIG. 2 is an S diagram of a portion of a DA conversion circuit according to the present invention.
It is a circuit diagram showing an embodiment of a C circuit.

FIG. 3 is a circuit diagram showing an equivalent circuit equivalent to a charge / discharge circuit of an SC circuit.

FIG. 4 is a circuit diagram showing another equivalent circuit equivalent to the charge / discharge circuit of the SC circuit.

FIG. 5 is a time chart of input / output signals.

FIG. 6 is a circuit diagram showing a known SC circuit.

7A and 7B are circuit diagrams respectively showing two-state equivalent circuits of a known SC circuit.

[Explanation of symbols]

2 ... Voltage dividing circuit 6 ... 1st resistance 7 ... 2nd resistance 8 ... 3rd resistance 12 ... Buffer amplifier 13-1,2,14-1 to 4,15-1,2,16-
1, 2 ... Switch group 17 ... First capacitor 18 ... Second capacitor 20 ... SC circuit

Claims (7)

(57) [Claims] 1. A voltage divider circuit and an SC circuit, wherein the voltage divider circuit divides into a first voltage, a second voltage and a third voltage by a first resistor, a second resistor and a third resistor. The SC circuit includes a first capacitor, a second capacitor, and a switching circuit, the switching circuit alternately forms a first connection circuit and a second connection circuit, and the first connection circuit includes the first voltage. Is connected to one pole of the first capacitor, the third voltage is connected to the other pole of the first capacitor, and the second voltage is connected to the second pole.
Connecting one pole of a capacitor, further connecting the third voltage to the other pole of the second capacitor, the second connection circuit connecting the third voltage to the one pole of the first capacitor, Also, the third voltage is applied to the second voltage.
Connected to the one pole of a capacitor, the voltage dividing circuit and the first capacitor are directly connected without a buffer amplifier, and the voltage dividing circuit and the second capacitor are not via a buffer amplifier. A DA converter circuit that is directly connected, wherein the first voltage is represented by VP, the second voltage is represented by VN, the third voltage is represented by VC, and the following formula: VP + VN = 2VC is satisfied. 2. The method according to claim 1, further satisfying the following formulas: VP = VN + 2r (I-Δi), VN = RI, wherein r is between the first voltage and the third voltage. Is a resistance value of the first resistor that generates a voltage, and r is a resistance value of the second resistor that generates a voltage between the third voltage and the second voltage, and R is A resistance value of the third resistor that generates the second voltage, the first resistor, the second resistor, and the third resistor are connected in series, and the I is the first resistor and the second resistor. Is a current flowing through the third resistor, and the Δi is the first
A DA conversion circuit, which is a virtual current flowing from the second capacitor to the first capacitor through the first resistor and the second resistor when a connection circuit is formed. 3. A first capacitor, a second capacitor, and a voltage dividing circuit, wherein the voltage dividing circuit supplies the first voltage VP to the first capacitor, and the voltage dividing circuit further comprises the second voltage dividing circuit. Second to capacitor
A voltage is supplied, and the voltage dividing circuit generates a differential voltage VC between the first voltage and the second voltage, and a differential condition represented by the following equation: VP + VN = 2VC is satisfied, At the time of charging, one pole of the first capacitor and one pole of the second capacitor are connected via the voltage dividing circuit, and the other pole of the first capacitor and the other pole of the second capacitor are connected. When discharged, the one pole of the first capacitor and the second pole of the first capacitor are discharged.
A buffer amplifier is interposed between a connection line connecting the one pole of the first capacitor and the one pole of the second capacitor when the battery shares the differential voltage VC with the one pole of the capacitor. DA conversion circuit not done. 4. The charging current according to claim 3, wherein during the charging, a charging current flows through the voltage dividing circuit, and the same virtual current Δi from the one pole of the second capacitor to the one pole of the first capacitor is the charging current. DA conversion circuit that flows in the opposite direction to the direction. 5. The DA conversion circuit according to claim 4, further comprising a switched capacitor circuit, wherein the first capacitor and the second capacitor are connected to the switched capacitor circuit. 6. A first voltage VP is supplied to one pole of the first capacitor, and a second voltage VN is supplied to one pole of the second capacitor,
Supplying a third voltage VC to the other pole of the first capacitor and the other pole of the second capacitor to satisfy the differential condition represented by the following equation: VP + VN = 2VC; By supplying the third voltage VC to one pole and one pole of the second capacitor, and connecting the other pole of the first capacitor and the other pole of the second capacitor to an analog output circuit, the first and the first capacitors are connected. Second step of discharging via a first voltage dividing resistor between the other pole of the two capacitors and the one pole of the second capacitor, and a second voltage dividing resistor between the one pole of the second capacitor and the ground DA including and
How to charge the conversion circuit. 7. The method according to claim 6, further comprising: during the charging, from the second capacitor to the first capacitor, between the other pole of the first and second capacitors and the one pole of the second capacitor. DA further comprising the step of flowing a virtual common current through the first voltage dividing resistor and a third voltage dividing resistor between the one pole of the first capacitor and the other poles of the first and second capacitors. How to charge the conversion circuit.