JPH0512728Y2 - - Google Patents

Description

[Detailed description of the invention] <Industrial field of application> The present invention relates to a displacement converter that converts displacement due to differential pressure or pressure into an electrical signal via capacitance, and in particular improves its resolution. This invention relates to a displacement conversion device.

<Prior Art> FIG. 5 shows a conventional displacement converting device disclosed in Japanese Patent Application Laid-open No. 57-26711 "Capacitive displacement converting device", and this will be explained.

Fixed electrodes FD ₁ and FD ₂ are disposed opposite to the moving electrode MD, forming capacitances C _H and _CL , which change in opposite directions with respect to the displacement of the moving electrode MD.

The moving electrode MD is connected to the input end of the inverter _G1 , and a constant value current limiting circuit _CC1 is connected in a negative feedback manner between the output end and the input end thereof. Inverter G ₁
The output terminal is the input terminal CL of the n-bit counter _CT1 .
, and its output end Q _o is connected via a NAND gate G ₂ to a fixed electrode FD ₁ forming the first electrode of the capacitance C _H , and at the same time an inverter G ₃ and a capacitance via the NAND gate G ₄ It is connected to a fixed electrode FD ₂ forming the second electrode of C _L. Furthermore, the other input ends of the NAND gates G ₂ and G ₄ are connected to the output end of the inverter G ₁ .

Then, inverters G ₁ , G ₃ , NAND gate G ₂ ,
Power supply voltage V _Z is applied to G ₄ and counter CT ₁ , respectively.

With this configuration, the first positive feedback loop to the inverter _G1 is formed by the NAND gate _G2 and the capacitance _CH ,
Inverter G ₁ with NAND gate G ₄ and capacitance C _L
form a second positive feedback loop to _the NAND gate G ₂ ,
The oscillation is continued by switching alternately through _G4 . The output of counter _CT1 is smoothed by filter circuit _FL1 .

Next, the operation of the capacitive displacement converter configured as described above will be explained with reference to the waveform diagram shown in FIG. 6.

The output of NAND gate G ₂ as shown in Figure 6 A
When (A) is set to high level “H” and voltage +V _Z occurs here, the capacitance increases due to its rise.
The combined capacitance C t of C _H , distributed capacitance C _S , and electrostatic capacitance C _L is charged in series, and the input terminal of inverter G ₁ suddenly reaches a constant voltage and rises almost vertically _as shown in FIG. Therefore, the change e ₁ in the terminal voltage of the distributed capacitance C _S with respect to the threshold level V _TH of the inverter G ₁ is expressed by the following equation.

e ₁ = C _H V _Z / (C _H + C _t ) ...(1) At this time, the output (C) of inverter G ₁ is at low level "L", but there is no connection between the input and output terminals of inverter G ₁ . Since the constant value current limiting circuit CC ₁ is connected, the charging electrification of the distributed capacitance C _S and the capacitance _CL immediately starts discharging via the constant value current limiting circuit CC ₁ and the output impedance of the inverter G ₁ .

However, since the discharge current i caused by this discharge is regulated to a constant current value by the constant value current limiting circuit _CC1 , the voltage at the input terminal of the inverter _G1 decreases linearly as shown in FIG. 6B. The discharge time _t1 required to drop to the threshold level _VTH can be obtained from the following equation.

it ₁ = e ₁ (C _H + C _t ) ...(2) From equations (1) and (2), t ₁ = C _H V _Z /i ... (3).

Threshold level V _TH of inverter G ₁
When _the voltage drops to
The output (A) of NAND gate _G2 becomes “L” level,
The voltage at the input terminal of inverter G ₁ has the same value as equation (1) and has the opposite polarity e ₁ ′. After this, constant value current limit circuit
CC ₁ causes a discharge of opposite polarity to occur linearly. As a result, when the threshold level V _TH of inverter G ₁ is reached, the output (C) of inverter G ₁ becomes the sixth
Invert as shown in Figure C. This reverse polarity discharge is also carried out with a constant value of current i, so the discharge time t ₁ ' is also
It becomes equal to t ₁ , and t ₁ = t ₁ ′...(4).

Therefore, on the capacitance C _H side, a pulse output having a period of T _H ′=2t ₁ is obtained.

These relationships are the same even when the output of the counter CT ₁ is switched to the capacitance _CL side after the counter CT ₁ has counted a predetermined value, so the following equation holds true.

t ₂ =C _L V _Z /i (5) Therefore, on the capacitance C _L side, a pulse output having a period of T _L ′=2t ₂ is obtained.

The periods T _H ′ and T _L ′ are proportional to the capacitances C _H and _CL , and the capacitances C _H and _CL change in proportion to the displacement of the moving electrode MD.

In addition, the "H" period T _H of the pulse signal obtained from the output Q _o of the counter CT ₁ is "L" in the capacitance C _H.
The period T _L corresponds to the capacitance C _L , and if this is averaged by the filter circuit FC ₁ , the calculation result of C _H /(C _H + C _L ) related to the duty ratio of the pulse signal is obtained. This calculation result gives a value proportional to the displacement of the moving electrode MD.

<Problem to be solved by the invention> However, in such a conventional displacement converter, the period T _H , T _L of the output pulse signal is a capacitance C _H of a predetermined width, for a displacement of a predetermined width. It operates so that C _L changes.

Therefore, when the variation width of the displacement is small, the variation range of the capacitances C _H and _CL is also small, which causes a problem that the resolution becomes small and the accuracy decreases.

<Means for solving the problems> In order to solve the above problems, this invention uses a capacitance that changes according to the displacement to be detected, and one end of this capacitance connected to the input terminal. an amplifying means; a negative feedback means for supplying an inverted current from the output end of the amplifying means to its input end; a fixed capacitor whose one end is connected to the input end of the amplifying means and whose other end is driven by a voltage in phase with the input of the amplifying means, which has a capacitance value larger than that of the amplifying means; A counting means for counting a predetermined number of pulse signals related to the output and outputting the result as a control signal, a first pulse generating means for producing a pulse output with a constant pulse width in synchronization with the pulse signal, and an inverted pulse obtained by inverting the pulse signal. A second pulse generating means that outputs a pulse with a constant pulse width in synchronization with the signal, a first switch means that turns on/off the pulse signal by the output of the first pulse generating means, and an inversion signal by the output of the second pulse generating means. A second switch means for turning on/off the pulse signal, a third pulse generation means for generating a shift pulse having the same pulse width as the control signal and shifted by a half period from the pulse signal, and an output of the first switch means is switched by the control signal. The apparatus includes first and second smoothing means for smoothing, respectively, and a third smoothing means for smoothing by switching the output of the second switch means by a shift pulse, and using each output of the first, second, and third smoothing means. A displacement output is output by executing a predetermined calculation.

<Operation> With this configuration of the present invention, a pulse signal corresponding to displacement is output with a part of the capacitance reduced by a predetermined value, so resolution is expanded and accuracy is improved even when displacement is small. improves.

<Example> Hereinafter, an example of the present invention will be described based on the drawings. FIG. 1 is a block diagram showing an embodiment of the capacitance/time converter of the present invention. Note that the same reference numerals are given to parts having the same functions as those in the conventional technology, and the description thereof will be omitted as appropriate.

Inverters G ₁ and G ₅ are connected in series to form an amplifier, and inverters G ₆ ,
A series circuit of G ₇ and fixed capacitance _GF is connected in positive feedback.

Also, the output end of inverter G ₆ and inverter G ₁
A series circuit of inverters G ₈ , G ₉ and constant-value current limiting circuit CC ₁ is connected in negative feedback together with inverter G ₆ between the input terminals of .

Furthermore, a fixed electrode FD ₁ facing the moving electrode MD,
The other ends of the differential capacitors C _H and _CL formed by FD ₂ are connected to the output end of the inverter G ₆ and the AND gates G _{10 and 2} , respectively.
Connected via _G11 . The output end of the inverter _G5 is connected to the input end CL of the counter _CT1 , and its n-bit output end _Qo is connected to the AND gates _G10 , _G11.
is directly connected to the input end of the inverter _G12 .

DL is a latch, and a control signal CS is applied to its data terminal D, and the level of the control signal CS corresponding to the rising edge of the output of the counter applied to its clock terminal C is outputted via an output terminal Q to an AND gate _G10. , applied to the input terminal of _G11 .

Next, the operation of the capacitance/time converter _CTV1 configured as described above will be explained using the waveform diagram shown in FIG. 2.

First, the case where the control signal CS is at a high level "H" and in the +E state as shown in FIG. 2A will be described. In this case, the output of the latch DL is at a high level (FIG. 2b).

The output of counter CT ₁ is high level “H” (second
In the state of period T _L ' in Figure C) (Figure 2 D), the output terminal of the AND gate _G10 is maintained at the low level "L", and the fixed electrode _FD1 is maintained at the common potential COM.

Therefore, as shown in Fig. 2D, in the period T _L ' and in the state (first state) where the input of the counter _CT1 is at a low level (Fig. 2D), the inverter
Since the output end of G ₇ is at the potential of the common potential point COM, the other end of the fixed electrode C _F is at zero potential, making it a constant value constant current circuit.
The other end of CC ₁ has a potential of +V _Z , and the other end of differential capacitor C ₁ has a potential of +V _Z.

In this first state, the other end of the constant value constant current circuit CC ₁ is at +V _Z , so each capacitor is charged and the voltage at the input end of the inverter G ₁ rises at a constant rate, resulting in its threshold voltage V _TH When it exceeds the voltage, the voltage at the output terminal of the inverter _G1 is inverted to low level, and the counter enters the second state.

In the second state, the other end of the constant value constant current circuit CC ₁ is at zero potential of the common potential point COM, and the other end of the fixed capacitor C _F is +
The other ends of V _Z and the differential capacitor _CL change to zero potential, respectively.

If the voltage at the input terminal of the inverter at this time is V ⁺ , then the charge in each capacitor immediately before inversion from the first state to the second state is (C _F +C _L +C _S )V _TH −C _L V _Z = (C _F +C _L +C _S )V ⁺ -C _F V _Z V ⁺ =V _TH + {(C _F -C _L )V _Z / (C _F +C _L +C _S )} ...(6) This second The term is a changing voltage e ₁ ' raised from the threshold voltage V _TH , and the discharge time t _{1 during which this changing voltage e 1} ' is reduced by the constant current i of the constant value constant current circuit CC ₁ between the threshold voltage _{V TH} ′ is given by the following equation.

_{it 1 ′ = e 1 ′ ( CF} C _L ) V _Z /i ...(8) is obtained.

When the voltage at the input terminal of the inverter _G1 reaches the threshold voltage _VTH of the inverter G1, the output terminal of the inverter _G1 is inverted to a high level and enters the second state. However, in the first state, V _TH is replaced by V ^- and V ⁺ is replaced by V _TH in equation (6). Therefore,
In this case, the relationship between the charges immediately before and after the inversion is (C _F +C _L +C _S )V _TH -C _F V _Z = (C _F +C _L +C _S )V ^- -C _L V _Z V ^- =V _TH - {(C _F − _{C L} ) V _Z / (C _F + C _L + C _S )} ...(9). The second term is the changing voltage e ₁ that changes from the threshold voltage V _TH , and the discharge time t 1 during which this changing voltage e ₁ is increased by the constant current i of the constant value constant current circuit CC ₁ until the threshold voltage _{V TH} is reached is It is given by the following formula.

it ₁ = e _i (C _F + C _L + C _S ) ...(10) Therefore, from e ₁ in the second term of equation (9) and equation (10), t ₁ = (C _F − C _L )V _Z /i...(11) is obtained.

From equations (8) and (11), the discharge times t ₁ ′ and t ₁ are equal,
T _L ′=2t ₁ , and a pulse signal having a period corresponding to the difference between the differential capacitance C _L and the fixed capacitance C _F is obtained at the terminal TL. In this case, oscillation will not continue unless the relationship C _F > C _L is satisfied.

Next, the output of counter _CT1 is low level “L”
In the state of the period T _H ' (FIG. 2C) (FIG. 2D), the output terminal of the AND gate _G11 is maintained at the low level "L", and the fixed electrode _FD2 is at the common potential COM.
is held in In this case as well, the following equation is obtained by calculating in the same way as when the output of the counter _CT1 is at the high level "H".

T _H ′=2(C _F −C _H )V _Z /i (12) The states of the above periods T _L ′ and T _H ′ are obtained on the input side of the counter CT ₁ .

However, the control signal CS is low level (Fig. 2 A)
Accordingly, the output of the latch DL is also inverted in synchronization with the output of the counter _CT1 (FIG. 2D), turning off the AND gates _G10 and _G11 .
Therefore, oscillation is repeated between a loop formed by inverters G ₆ , G ₇ and fixed capacitance _CF and a loop formed by inverters G ₆ , G ₈ , G ₉ and constant-value current limiting circuit CC ₁ .

Therefore, if the other ends of the differential capacitors C _L and C _H are connected to the common potential point COM in Figure 1, and the same calculation is performed as when the control signal CS is at a high level, the period T _F ' in this case is It will look like this:

T _F ′=C _F V _Z /i ……(13) T _L ′, T _H ′, T _F ′ are the periods of pulses on the input side of counter CT ₁ , and each output terminal of the counter has an n-bit count. T _L =nT _L ′ = {n(C _F −C _L )V _Z /i}+Td ……(13) T _H =nT _H ′ = {n(C _F −C _H )V _Z /i}+Td ...(14) T _F =nT _F ′ = {nC _F V _Z /i}+Td ...(15) A capacitance signal S ₁ is obtained.

Here, Td indicates a delay existing at both ends of the constant value current limiting circuit _CC1 or in the oscillation path.

FIG. 3 is a block diagram showing the overall configuration of the present invention. In the figure, CTV ₁ is the capacity/time converter shown in FIG.

A capacitance signal _S1 , which is the output of the counter _CT1 , is obtained from the terminal TL. This capacitive signal S ₁ is a monostable circuit that outputs a pulse signal S ₂ with a constant time width T ₀ determined by a resistor R ₁ and a capacitor C ₁ from the output terminal Q.
It is connected to the input terminal C of FF ₁ . A capacitance signal S ₁ is applied to one end of the switch SW ₁ , this capacitance signal S ₁ is opened and closed by a pulse signal S ₂ , and outputted to the other end.

In addition, the capacitance signal S ₁ is inverted by the inverter G ₁₃ and converted into a pulse signal S ₃ , which outputs a pulse signal S ₄ with a constant time width T ₀ ′ (=T ₀ ) determined by the resistor R ₂ and the capacitor C ₂ . It is applied to the input terminal C of the monostable circuit FF ₂ outputting from the terminal Q. A pulse signal _S3 is applied to one end of the switch _SW2 , this pulse signal _S3 is opened and closed by a pulse signal _S4 , and outputted to the other end.

The capacitance signal _S1 is applied to the input terminal C of the n-bit counter _CT2 , and the control signal CS is applied from the n-bit output terminal _Qo to the latch DL of the capacitance/time converter _CTV1 .
is applied to the data terminal D of.

One end of the switch SW ₃ of the period control circuit TBC has a constant time width T ₀ obtained at the output end of the monostable circuit FF ₁ .
A pulse signal S ₂ of is applied, and the other end is connected to a resistor R ₃ ,
It is inputted to the non-inverting input terminal (+) of an amplifier Q _A to which the reference voltage V _S is applied to the inverting input terminal (-) via a filter FL ₂ constituted by a capacitor C ₃ . At its output end, a switch is controlled by a control signal CS to obtain a voltage V _Z corresponding to the reference voltage V _S.

This voltage _VZ is used as a power supply voltage for the AND gates _G10 , _G10 , inverters _G7 , _G8 , etc. of the capacitance/time converter _CTV1 .

(n-1) bit output terminal Qo _-1 of counter _CT2
The pulse signal S ₅ and the pulse signal S ₃ are ANDed by an AND gate G ₁₄ and the output is sent to the counter CT _3.
is applied to the input terminal CL of Also, counter CT ₂
The respective outputs of the output terminals Qo _and Qo _-1 are input to the OR gate _G15 , and the output thereof is applied to the reset terminal R of the counter _CT3 . And the output end of counter CT ₃
A pulse signal _S6 is output from _Qo .

The output of the other end of the switch SW ₁ is applied to the common terminal of the switch SW ₄ , and the output of the first switching terminal is applied to the input end of the buffer Q _B1 via the filter FL ₃ , and the voltage V is applied to the output end of the switch SW 4. Get ₁ .

Further, the output of the second switching terminal of the switch _SW4 is applied to the input terminal of the buffer _QB2 via the filter _FL4 , and a voltage _V2 is obtained at its output terminal.

The opening and closing of the switch _SW4 is controlled by the control signal CS.

In addition, a switch opened and closed with a pulse signal S ₆
The output from the other end of switch SW ₂ is applied to one end of SW ₅ , and the output from the other end is applied to the input end of buffer Q _B3 via filter FL ₅ to obtain voltage V ₃ at its output end.

Subtractor Q _B subtracts voltage V ₂ at the output of buffer Q _B1 from voltage V ₂ at the output of buffer Q _B2 to obtain voltage V ₄ at its output. Further, the subtracter Q _C subtracts the voltage _{V 3 at} the output of the buffer Q _B3 from the voltage V 2 at the output of the buffer Q _B2 to obtain the voltage V ₅ at its output.

Next, the operation of the embodiment configured as above will be explained using the waveform diagram shown in FIG. 4.

The capacitance signal S ₁ (Fig. 4 A) at the output terminal of the counter CT ₁ of the capacitance/time converter CTV ₁ is counted.
CT ₂ counts n bits, and outputs the control signal CS shown in Fig. 4 to its output terminal Q _o , and sends a pulse signal S ₅ to its (n-1) bit output terminal Q _o-1 (Fig. 4 H). get. The input terminal of AND gate G ₁₅ receives pulse signal S ₅
and the control signal CS shown in FIG. 4 are input, and the output thereof is input to the reset terminal R of the counter CT ₃ to set the state of the counter CT ₃ to the initial state at the time of startup. The input terminal of AND gate _G14 has a pulse signal
S ₅ and a pulse signal S ₃ (FIG. 4B) obtained by inverting the capacitance signal S ₁ are inputted, respectively, and a pulse signal as shown in FIG. 4H is obtained at the output. The counter CT ₃ starts counting in synchronization with the rise of this pulse signal, and a pulse signal S ₆ as shown in FIG. _4G is obtained at its output terminal Qo.

Monostable circuit synchronized with the rise of capacitive signal S ₁
A pulse signal S ₂ with a constant pulse width T ₀ is output from FF ₁ , which opens and closes the switch SW ₄ . While the control signal CS is at a high level (FIG. 4), the switch _SW4 is switched to the filter _FL3 side, and a voltage _V1 is obtained at the output terminal of the buffer _QB1 .

This voltage V ₁ is given by V ₁ =T _L E/T ₀ (16).

Also, the control signal CS is at low level (see Figure 4).
During this period, the switch SW ₄ is switched to the filter FL ₄ side, and the voltage V ₂ is obtained at the output terminal of the buffer Q _B2 .

This voltage V ₂ is given by V ₂ =T _F E /T ₀ (17).

As for the switch _SW5 , the pulse signal _S6 is shifted by T _L from the control signal CS as shown in Fig. 4,
It turns on at this high level. Therefore, during this period, voltage _V3 is obtained at the output terminal of buffer _QB3 via filter _FL5 . This voltage V ₃ is given by V ₃ = _TH E/T ₀ (18).

Therefore, the outputs of the subtracters Q _B and Q _C are V ₄ =V ₂ −V ₁ ……(19) V ₅ =V ₂ −V ₃ ……(20) respectively.

In addition, the period control circuit TBC has a period (T _L + T _H ))
is controlled to a constant value, but from equations (13) and (14), the term of the fixed capacitance C _F is set to a constant value K′ (T _L + T _H )
When calculating, we obtain nV _Z ( _CL + C _H )/i+K', which is equal to the constant value K''. Therefore, nV _Z (C _L +C _H )/i=K...(21) However, K= K″−K′.

From the above equations (13) to (21), the output voltage V ₀ is given by the following equation.

V ₀ = V ₄ − V ₅ = V _Z (T _F − _{T L} − T _F − T _H ) = nV _Z E (C _L − C _H )/iT ₀ = (KE/T ₀ ) (C _L − C _H ) /(C _L +C _H ) ...(22) In the above manner, an output proportional to the difference in the sum of the differential capacitances can be obtained. This shows that it is possible to obtain an output voltage V ₀ that is proportional to the displacement.

Also, by omitting the periodic control circuit TBC (V ₄ −
The calculation output of V ₅ )/(V ₄ +V ₅ ) may also be output.
Furthermore, as the input of the periodic control circuit TBC (V ₄ +
The same result can be obtained using V ₅ ).

<Effects of the invention> As specifically explained above in conjunction with the embodiments, according to the present invention, the resolution can be improved compared to the conventional method, so accuracy can be further improved, and furthermore, the constant value current limit circuit can be improved. The influence of stray capacitance occurring at both ends or time delay of the oscillation path can be removed. In particular, as the sensor itself becomes smaller and the differential capacitance itself becomes smaller, errors due to delays in the oscillation path become larger, but this method is also effective in such cases.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing one embodiment of the capacitance/time converter of the present invention, Fig. 2 is a waveform diagram for explaining the operation of the circuit shown in Fig. 1, and Fig. 3 is the entire structure of the present invention. A block diagram showing the configuration, FIG. 4 is a waveform diagram for explaining the operation of the circuit shown in FIG. 3, and FIG.
This figure is a block diagram showing the configuration of a converting section of a conventional displacement converting device, and FIG. 6 is a waveform diagram illustrating the operation of the circuit shown in FIG. 5. C _H , C _L ... Capacitance, CT ₁ - _{CT 3} ... Counter, CC ₁ ... Constant value current limit circuit, FL ₁ - _{FL 5} ...
Filter, CTV ₁ ...Capacity/time conversion section, TBC...
...periodic control circuit, FF ₁ , FF ₂ ...monostable circuit.

Claims (1)

[Scope of utility model registration request] A capacitance that changes depending on the displacement to be detected,
an amplifying means in which one end of this capacitance is connected to an input end; a negative feedback means for supplying an inverted current from the output end of the amplifying means to its input end; driving means for driving the other end of the capacitance in opposite phase or fixing it at a predetermined potential; one end is connected to the input end of the amplifying means, and the other end is driven with a voltage in phase with the input of the amplifying means; a fixed capacitor having a capacitance value larger than the capacitance; a counting means for counting a predetermined number of pulse signals related to the output of the amplifying means and outputting the same as the control signal; and a constant pulse in synchronization with the pulse signal. a first pulse generating means for outputting a pulse of width;
a second pulse generating means for outputting a pulse with a constant pulse width in synchronization with an inverted pulse signal obtained by inverting the pulse signal; and a first switch means for turning on/off the pulse signal using the output of the first pulse generating means. , second switch means for turning on/off the inverted pulse signal with the output of the second pulse generating means;
third pulse generating means for generating a shift pulse having the same pulse width as the control signal and shifted by a half period from the pulse signal; and first and second pulse generating means for switching and smoothing the output of the first switch means according to the control signal.
a smoothing means, and a third smoothing means for switching and smoothing the output of the second switch means by the shift pulse, and performing a predetermined calculation using each output of the first, second, and third smoothing means. A displacement converting device characterized in that it executes and outputs a displacement output.