JPH0460532B2 - - Google Patents

Description

[Detailed Description of the Invention] <Industrial Application Field> The present invention relates to a displacement conversion device that converts displacement due to differential pressure or pressure into an electrical signal via capacitance, and particularly relates to a displacement conversion device with improved resolution. This invention relates to a displacement conversion device.

<Prior Art> FIG. 11 shows a conventional displacement converter disclosed in Japanese Patent Application Laid-Open No. 57-26711 entitled "Capacitive Displacement Converter", and this will be explained.

_C One end of the capacitance C _X is connected to the input end of the inverter G ₁ and is also connected to the common potential point COM via the distributed capacitance C _S . A bidirectional constant current circuit CC is connected between the input and output ends of the inverter _G1 , and its output end is connected to the other end of the capacitance _CX via the inverter _G2 . Here, the inverters G ₁ and G ₂ form an amplifying means, and feed back from the output of the inverter G ₂ a voltage that is in phase with the voltage at the input end of the capacitance C _X inverter G ₁ .
Further, the bidirectional constant current circuit CC constitutes a feedback means that feeds back the voltage at the input end of the inverter _G1 in the opposite phase.

Next, the operation of the displacement converter shown in FIG. 11 will be explained using the waveform diagram shown in FIG. 12.

When the output of inverter _G2 is at a high level "H" and a voltage + _E is generated (Fig. 12A), the _series circuit of capacitance C Since the terminal voltage of _S suddenly reaches a constant voltage, it rises almost vertically as shown in FIG. 12B. Also, at this time, the output of inverter _G1 is low level "L" and the common potential point COM has zero potential, so the charge in the distributed capacitor C _S is transferred through the bidirectional constant current circuit CC and the output impedance of the inverter _G1 . The inverter _G1 immediately starts discharging at a constant current i, and the voltage at the input end of the inverter G1 decreases linearly as shown in FIG. 12B. When the inverter G drops to the threshold voltage V _TH of ₁ , the inverter
The output of G ₁ is inverted to +E, which is a high level “H” (Fig. 12 C), and the output of inverter G ₂ becomes low level “L”, so that the residual charge in the distributed capacitance C _S is After rapidly discharging through the capacitor C _X and the voltage at the input end of the inverter G ₁ drops vertically,
Due to the high level "H" at the output end of inverter _G1 , the distributed capacitance C _S is charged by the constant current i from the bidirectional constant current circuit CC, and the voltage at the input end of inverter _G1 increases linearly (Fig. 12). c). The output of inverter _G1 that reaches the threshold voltage V _TH is inverted to low level “L”, thereby causing the inverter to
Since the output of _G2 becomes high level "H", charging from inverter _G2 is performed again, and this operation is repeated.

Here, the changing voltage e ₁₀ across the distributed capacitance C _S with the threshold voltage V _TH as a reference is expressed by the following equation.

_{e 10 = C X / C}

it ₁₀ = e ₁₀ (C _X + C _S ) (2) Using equations (1) and (2), t ₁₀ = C _X E/i (3). Note that as charging and discharging are repeated, a charge corresponding to the threshold is determined as a reference potential in the distributed capacitance C _S and charging and discharging is performed around this, so the change in voltage e ₁₀ on the charging side and the change on the discharging side The voltage e ₂₀ becomes equal, and by performing charging for ₂₀ minutes of this changed voltage e with the constant current i from the bidirectional constant current circuit CC, the times t ₁₀ and t ₂₀ become equal, and the following equation holds true.

t ₁₀ = t ₂₀ = E/iC _X (4) Therefore, the periods t ₁₀ and t ₂₀ are proportional to the capacitance _C
The capacitance C _X changes depending on the displacement of the opposing electrodes.

<Problems to be Solved by the Invention> In such a conventional displacement conversion device, the period t ₁₀ (t ₂₀ ) of the output pulse signal is such that the capacitance _C It operates as follows.

Therefore, when the variation width of the displacement is small, the variation range of the capacitance C _X is also small, which causes a problem that the resolution becomes small and the accuracy decreases.

<Means for solving the problems> In order to solve the above problems, the present invention has the following features:
A capacitance that changes according to the displacement to be detected, an amplifying means with one end of this capacitance connected to an input end, and a negative feedback means for supplying an inverted current from the output end of the amplifying means to its input end. and a drive means for driving the other end of the capacitance in the same phase as the input of the amplification means, and one end of which is connected to the input end of the amplification means and has a value smaller than twice the value of the capacitance. a fixed capacitor, a driving means for driving with a voltage in phase or in phase with the input of the amplifying means and alternately applying 1/2 of the power supply voltage and a predetermined voltage to the other end of the fixed capacitor; The main configuration includes first microcomputer means that executes a predetermined calculation using a pulse signal related to the output of the means and outputs an output corresponding to the previous displacement.

<Function> With the main configuration of the present invention as described above, a pulse signal having a pulse width corresponding to the displacement is output with a portion of the capacitance reduced by a predetermined value.
Resolution is expanded and accuracy is improved.

<Example> Hereinafter, an example of the present invention will be described based on the drawings. FIG. 1 is a block diagram showing one embodiment of the present invention. It should be noted that parts having the same functions as those in the prior art are denoted by the same reference numerals, and the description thereof will be omitted as appropriate.

_{One end of} the capacitance C
Connected to COM. A bidirectional constant current circuit CC is connected between the input and output terminals of the inverter _G1 to form a negative feedback path. In _addition , _the other _end of _the capacitance _C Its opening and closing is controlled by a control signal CS.

A fixed capacitor _CF is connected to the input end of the inverter _G1 , and a drive circuit DRC is connected between the other end and the output end of the inverter _G1 . drive circuit
Inside the DRC, there are switches S ₁ , S ₂ , S ₃ , S ₄ connected in series between the power supply voltage +E and the common potential point COM.
is provided, and +E/ is provided at the connection point of switches S ₂ and S ₃ .
2 voltages are applied. The opening and closing of switches _S1 and _S4 are controlled by the outputs of AND gates _G4 and _G5 , and the opening and closing of switches _S2 and _S3 are controlled by the output of inverter _G6 . Inverter G ₁ is connected to one end of each input of AND gates G ₄ and G ₅ and to the input end of inverter G ₆ .
The output of is applied. Furthermore, and gate
A control signal CS is applied to the other input end of _G4 , and a control signal CS inverted by an inverter _G7 is applied to the other input end of AND gate _G5 to control these. Each connection point of the switches S ₁ and S ₂ and S ₃ and S ₄ is connected to the other end of the fixed capacitor _CF.

The output pulse signal is taken out from the output end of the inverter _G1 via the terminal _TL2 . Note that each inverter, AND gate, and NAND gate are each energized with a power supply voltage +E.

Next, the operation of the capacitance/time converter CTV ₁ shown in FIG. 1 and configured as described above will be explained using FIGS. 2 and 3.

First, a state in which the control signal CS is at a high level "H" and +E as shown in FIG. 3A will be explained.

When the output terminal of the inverter G ₁ is at a high level "H" during period T _X (FIG. 3C), the input terminal of the inverter G ₁ is connected as shown in FIG. 2A. In this state, since the voltage +E is applied to the other end of the bidirectional constant current circuit CC, each capacitor is charged by this, and the voltage at the input end of the inverter _G1 rises at a constant rate, raising its threshold voltage V _TH . When the voltage is exceeded (FIG. 3(b)), the voltage at the output terminal of the inverter _G1 is inverted to the low level "L", resulting in the state shown in FIG. 2(b).

The charging charge of each capacitor immediately before it is reversed from A to B in Figure 2 is (C _F + C _X + C _S ) V _TH −C _F E from A in Figure 2
, and ^the charge in _{each capacitor} immediately after _inversion is ⁽ C _F + _C E-C _X E. Since the total amount of charge immediately before and after the inversion does not change, the following equation holds true.

(C _F +C _{X +} C _S ) _{V TH} −C _F E ⁼ (C _F ⁺ C _X + _{C S} ) _V ⁺ _{−C C F + C _ _ _} The period _T'X , which is the time reduced by the current i, is given by

iT _{′ X =} e′ _{1 ( C F + C} /iE (7) is obtained. Threshold voltage V _TH of inverter G ₁
When the voltage at the input terminal reaches , the output terminal of the inverter _G1 is inverted to a high level "H" and becomes the state shown in FIG. 2A. However, instead of V ⁺ in Figure 2 B, V _HT ,
The voltage V ^- at the input terminal of the inverter G ₁ is substituted for V _TH in Figure 2 A. Therefore, the relationship between the charges immediately before and after the inversion in _this case is (C _F +C _X + _{C S} )V _TH ^-C _F E = (C _F ⁺ _{C TH} −C _X −1/2C _F /(C _F +C _X +C _S )E (8). The second term is the changing voltage e ₁ that drops from the threshold voltage V _TH , and the period is the time during which this changing voltage e ₁ is increased to the threshold voltage V _TH by the constant current i of the bidirectional constant current circuit CC.
T _X is given by the following formula.

_{iT X = e 1 ( CF + C} ) is obtained. From equations (7) and (10), the periods T _X and T′ _X are equal,
In both cases, a pulse signal having a period corresponding to the difference between the capacitance C _X and the fixed capacitance C _F /2 is obtained at the terminal TL ₂ . In this case, oscillation will not continue unless the relationship C _X < ¹ ₂ C _F is satisfied. Comparing equations (4) and (10), we find that in equation ( ₄ ), oscillation with a period t ₁₀ corresponding to capacitance _C The oscillation has a period T _X corresponding to the difference from the capacitance ¹ ₂ C _X , resulting in a higher frequency and improved resolution compared to the case of equation (4).

The above holds true if the constant current i, the power supply voltage E are constant, and the fixed capacitance C _F is known, but by adding an operation to switch the control signal CS to the low level "L" zero state, this can be changed. The resolution can be improved even if the value is not necessarily constant or known. Next, this point will be explained.

In this case, the other end of capacitance _C
High level “H” regardless of the level of the output terminal of _G1
and fixed capacitance C _F to the other end of the drive circuit DRC
Therefore, each voltage of E/2 and the common potential is applied alternately, and oscillation is repeated. Therefore, in Figure 2, the other end _of capacitance _C Then, the periods T _F1 and T' _F1 (Fig. 3 C) become as follows.

T _F1 = T _F ′ ₁ = 1/2C _F /iE (11) Therefore, from equations (10) and (11), when C _F is constant, C _X = C _F /2(T _F1 /T _X −1) (12) When i is constant, C _X = i/E (T _F1 − T _X ) (13) By operating the control signal CS,
The unknown capacitance C _X can be determined using the period T _F1 and T _X of the pulse signal appearing at TL ₂ .

FIG. 4 is a block diagram showing an embodiment in which the capacitance is a differential capacitance in which the capacitance changes differentially with respect to each other.

Inverters G ₈ and G ₉ are connected in series to form an amplifier, and inverters G ₁₀ ,
A drive circuit DRC and a fixed capacitor C _F are connected in series. In addition, the output of inverter _G10 is connected to the fixed electrode facing the moving electrode MD via the drive circuit DCC.
The movable electrode MD is connected to the other ends of differential capacitors C _H and _CL formed by FD ₁ and FD ₂ , and is connected to the input end of an inverter G ₈ . The drive circuit DCC is composed of NAND gates G ₁₁ and G ₁₂ , and each output terminal thereof is connected to fixed electrodes FD ₁ and FD ₂ . nand gate
The first input terminals of G ₁₁ and G ₁₂ are the output of the inverter G ₁₀ , and the second input terminals are the output terminals of the counter CT ₁ Q _o
and the voltage level obtained by inverting this level with the inverter _G13 , each of the third input terminals is latched.
A voltage of a level obtained by inverting the output of DL by inverter _G14 is applied to each. In addition, the inverter
The input terminal of _G10 is connected to the input terminal CL of the counter _CT1 , and the other input terminal of the AND gate _G4 of the drive circuit DRC is connected to the output terminal of the inverter _G14 .

DL is a latch, and a control signal CS is applied to its data terminal D, and the level of the control signal CS corresponding to the rising edge of the output of the counter _CT1 applied to its clock terminal C is outputted to its output terminal Q.

Furthermore, one end of the bidirectional constant current circuit CC is connected to one end of the input of the inverter _G8 , and the other end is connected to the output end of _G16 via the NAND gates _G15 and _G16 . Each input terminal of NAND gate G ₁₅ is a latch DL
The output terminal Q of is connected to the output terminal of inverter G ₁₀ , and each input terminal of NAND gate G ₁₆ is connected to the output terminal of inverter G 10.
It is connected to each output terminal of G ₁₁ , G ₁₂ , and G ₁₅ .

Next, the capacity/time converter configured as above
The operation of CTV ₂ will be explained using the waveform diagram shown in FIG.

First, the case where the control signal CS is at a low level "L" and zero as shown in FIG. 5A will be described. In this case, the output of the latch DL is at a low level. Therefore, the output of inverter _G14 is at a high level.

The output of counter CT ₁ is high level “H” (5th
In the state of period T _L in Figure C (Figure 5 D), the output of inverter _G13 is low level, so the output of NAND gate _G12 is high level regardless of the level of the output of inverter _G10 . It is held at +E. On the other hand, the second and third of Nand Gate G ₁₁
Since each input terminal of is held at a high level, a voltage at a level depending on the output level of inverter _G10 is applied to fixed electrode _FD2 .

Therefore, in this case, the distributed capacitance C _S
Since the relationship is functionally equivalent to that in which differential capacitance C _H is connected in parallel to capacitance C _X and differential capacitance C _L is connected in place of capacitance C In the same way as above, we obtain the following equation.

T _L =n(C _L -2/1C _F /i)E (14) However, in the case shown in Fig. 4, the _NAND gate G is ₁₁ and G ₁₂ select the differential capacitor C _L side and repeat oscillation, so it is multiplied by n in equation (14).

When the output level of the NAND gate _G11 is inverted n times, the output of the counter _CT1 is inverted to the low level "L" (FIG. 5C) and enters the state of period T _H. In this state, the outputs of inverter _G13 and NAND gate _G11 remain at high level. and,
A voltage whose level depends on the output level of the inverter _G10 is applied to the fixed electrode _FD1 via the NAND gate _G12 . Therefore, this case is functionally equivalent to the relationship in Figure 1 where differential capacitance C _L is connected in parallel to distributed capacitance C _S and differential capacitance C _H is connected in place of electrostatic capacitance C _X. Therefore, we obtain the following equation in the same way as we derived equation (14).

T _H =n(C _H -1/2C _F /i)E (15) Repeat the above state. Therefore, fixed capacity
Since the oscillation has periods T _L and T _H corresponding to the difference between C _F /2 and the differential capacitance C _L or C _H , the differential capacitance
A high-frequency pulse signal can be obtained from the terminal TL ₂ relative to the oscillation caused by C _L and _CH themselves, resulting in a capacitance/time converter CTV ₂ with high resolution.

However, if the constant current i and the power supply voltage E change over time and are not constant, or if the fixed capacitance is not known, the accuracy can be further improved by taking the following measures.

In this case, the control signal CS is inverted to +E, which is a high level "H", as shown in FIG. 5A.
At this time, the output of the latch DL is inverted to a high level "H" according to the rising timing of the output of the counter _CT1 (FIG. 5C). In this state, the outputs of NAND gates G ₁₁ and G ₁₂ are both high level “H”
The voltage level at the other end of the fixed capacitor C _F changes to E/2, which is zero, and oscillation is repeated. Therefore, in this case, it is equivalent to connecting the differential capacitors C _L and C _H in parallel to the distributed capacitance C _S in Figure 1, and in the same way as formula (11) was derived, the following formula is obtained. is obtained.

T _F2 = nC _F /iE (16) Therefore, from equations (14), (15), and (16), when C _F is constant, When i is constant, terminal by manipulating the control signal CS as
The unknown differential capacitances C _L and C _H can be determined using the periods T _F2 , T _L , and T _H of the pulse signals appearing at TL ₂ .

Note that there is stray capacitance at both ends of the bidirectional constant current circuit CC.
In the presence of C _i and if there is an overall delay T _d in the oscillation path, the periods T _L ′, T _H ′, T _F ′ ₂ are T _L ′=n(C _L −1/2C _F −C _i /i)E+T _d (19) T _H ′=n(C _H −1/2C _F −C _i /i)E+T _d (20) T _F ′ ₂ =n(C _F2 −2C _i /i)E+T _d (21) However, using these formulas, C _L = i/nE (T _L ′/T _F2 + 1/2) C _F (22) C _H = i/nE (T _H ′/T _F2 +1/2) C _F (23) and the stray capacitance C _i and delay T _d are removed. In particular, as the differential capacitances C _L and C _H become smaller, errors due to delays in the oscillation path tend to occur, but according to equations (22) and (23), this is not a cause of errors.

FIG. 6 is a block diagram showing the configuration of a microcomputer section which receives pulse signals from the capacitance/time conversion sections CVT ₁ and CVT ₂ and processes the signals.
The case where CVT ₂ is used as a capacity/time converter will be explained as an example.

Reference numeral 10 denotes a microcomputer section to which a pulse signal from the capacitance/time conversion section CVT ₂ is input, processes the signal, and outputs the signal. 11 is a timer counter that converts a time signal into a digital value. 12 is
RAM (random access memory), 13 is ROM
(read-only memory), and these addresses are specified from the CPU (processor) 14 to the bus 15,
This is done via the latch decoder 16. Output data from timer counter 11 is stored in RAM 12 via data bus 17. A predetermined calculation program and initial data are stored in the ROM 13, and calculations are performed according to the calculation procedure stored in the ROM 13 under the control of the CPU 14, and the results are stored in the RAM 12. 18 is a control bus, and timer counter 1 is controlled by the CPU 14.
1. Controls the operations of the RAM 12 and ROM 13 and outputs a control signal CS to the capacity/time converter CVT ₂ .

The final calculation result is converted into a duty signal by a timer counter 19, and the duty signal is converted into an analog signal by a duty/analog conversion section 20 and outputted to an output terminal 21.

Next, signal processing in the microcomputer section shown in FIG. 6 will be explained using the flowchart shown in FIG.

First, in the step, the period T _F2 is set as initial data.
is set from ROM13 to RAM12. next,
The spring constant K of the moving electrode MD, the fixed capacitance C _F , the constant current i, the number of bits n of the counter CT ₁ , the power supply voltage E, and the value C _p of each differential capacitance C _L and C _H when the differential pressure ΔP is zero. etc. are set from ROM 13 to RAM 12 (step). In the step, the capacity/time conversion section
Cycle of pulse signal output from CVT ₂ T _L , T _H
is loaded. Next, using the arithmetic program built into the ROM 13, equations (17), (18) or (22) are
The calculation of equation (23) is executed and the differential capacitances C _L and C _H are calculated (step).

The calculation in the step is performed as follows. The differential capacitances C _L and C _H are each expressed by the following equations.

From these equations, the differential pressure ΔP can be expressed as ΔP=1/K(C _L −C _H /C _L +C _H ) (25). Therefore, C _L , C _H obtained in step
The differential pressure ΔP is calculated using the calculation program shown in equation (25) stored in the ROM 13.
Also, the displacement is determined by multiplying by the spring constant K. The calculation result is outputted to an output terminal 21 via a timer counter 19 and a duty/analog converter 20.

Since the period T _F2 does not change in a short time, the period T _L ,
Since the cycle T _F2 can be read in 1/5 to 1/10 cycles of reading T _H , the correction cycle is determined in the step. If the correction cycle is not reached, the process returns to the step, and when the correction cycle is reached, the process returns to the step. Then, the control signal CS is manipulated to read the period T _F2 , and thereafter the calculations (17), (18), (22), and (23) are executed using this period T _F2 .

FIG. 8 is a block diagram showing a third embodiment of the capacity/time converter. This capacity/time converter
CVT ₃ shows a case where the phase of the moving electrode MD and the input phase of the input terminal _CL of the counter CT ₁ are different.
In this case, inverter _G17 is inserted between the input terminal C _L of counter _CT1 and inverter _G5 , and the counter
The input phase of CT ₁ is inverted. When doing this, an inverter _G18 is inserted between the output terminal of the counter _CT1 and the clock terminal C of the latch DL, and the AND gates _G4 , _G5 , NUN gates _G11 , _G12 , If G ₁₅ and G ₁₆ are replaced with Norgates G ₁₉ , G ₂₀ , G ₂₁ , G ₂₂ , G ₂₃ and G ₂₄ , the same operation as shown in FIG. 4 will occur.

FIG. 9 is a block diagram showing a fourth embodiment of the capacity/time converter. This capacity/time converter
CVT ₄ uses two types of reference capacitance C _F and switches the resolution in two stages. drive circuit
A double-throw changeover switch SW ₁ is provided at the output end of the DRC to switch between fixed capacitances C _F1 and C _F2 , and the output end of the counter CT ₁ is set to two types, Q _n and Q _o, and the switch SW ₂ is used to switch between them. Output to TL ₂ . The opening and closing of these switches SW ₁ and SW ₂ is controlled by a switching signal SS ₁ applied via a control bus 18 of the microcomputer section 10.

FIG. 10 is a block diagram showing a fifth embodiment of the capacity/time converter. This capacity/time converter
CVT ₅ switches the voltage that excites the fixed capacitor C _F to two types, V ₁ and V ₂ , when the phase of the moving electrode MD and the input phase of the input terminal CL of the counter CT ₁ are different.
It is switched via S ₅ and S ₆ and has one fixed capacitance _CF. Switches S ₁ and S ₄ further supply switching signals SS ₁ to the inputs of AND gates G ₄ and G ₅ in FIG.
The input terminal applied through the inverter G ₂₅ is controlled by the output of the additional AND gates G ₄ ′ and G ₅ ′. The opening and closing of switches S ₅ and S ₆ are controlled by the outputs of AND gates G ₂₆ and G ₂₇ , and switches S ₁ , S ₅ and S ₄
and _S6 are opened and closed in an antiphase relationship with each other by the switching signal _SS1 . Therefore, the switching signal SS ₁ causes a voltage V ₁ instead of the supply voltage +E, and a voltage V 1 instead of zero voltage.
Each fixed capacitance C _F can be excited with V ₂ . In the embodiments shown in FIGS. 9 and 10, the output of the counter CT ₁ is switched by the switch SW ₂ , but the same result can be obtained by changing the constant current value i of the bidirectional constant current circuit CC instead. is obtained.

<Effects of the Invention> As specifically explained above in conjunction with the embodiments, according to the first invention, the resolution can be improved compared to the conventional method, so that the accuracy can be further improved. According to the invention, in addition to the effects of the first invention, there is a change over time in the current value of the bidirectional constant current circuit,
It is possible to eliminate all stray capacitances occurring at both ends, time delays in the oscillation path, and fluctuations in power supply voltage. In particular, as the sensor itself becomes smaller and the differential capacitance itself becomes smaller, errors due to time delays in the oscillation path become larger; in this case, even more effective effects can be achieved.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the capacitance/time converter of the present invention, FIG. 2 is a connection diagram for explaining the operation of the circuit shown in FIG. 1, and FIG.
Waveform diagram showing the waveforms of each part of the example shown in the figure, No. 4
The figure is a block diagram showing a second embodiment of the capacity/time converter of the present invention, FIG. 5 is a waveform diagram showing waveforms of each part of the embodiment shown in FIG. 4, and FIG. 6 is the overall configuration of the present invention. FIG. 7 is a flowchart showing the signal processing procedure of the embodiment shown in FIG. 6, and FIGS. Block diagram showing 5 embodiments,
FIG. 11 is a block diagram showing a conventional displacement converter, and FIG. 12 is a waveform diagram showing waveforms of various parts of the displacement converter shown in FIG. C _X ...Capacitance, C _S ...Distributed capacitance, C _L , C _H ...
...differential capacitance, CC...bidirectional constant current circuit, C _F ...
Fixed capacitance, CS...control signal, CT ₁ ...counter,
DL...Latch, CVT ₁ to CVT...Capacity/time conversion section, 10...Microcomputer section, 11,
19...Timer counter, 17...Data bus,
18...Control bus, 20...Duty/
analog converter.

Claims (1)

[Claims] 1. A capacitance that changes according to the displacement to be detected, an amplifying means with one end of this capacitance connected to an input end, and an inverting capacitance from the output end of the amplifying means to its input end. negative feedback means for supplying current; first driving means for driving the other end of the capacitance in the same phase as the input of the amplification means; and one end of the capacitance connected to the input end of the amplification means. a fixed capacitor having a value smaller than twice the value; and a second voltage source, which is driven by a voltage in phase with or in phase with the input of the amplifying means, and alternately applies 1/2 of the power supply voltage and a predetermined voltage to the other end of the fixed capacitor. 2 driving means; and first microcomputer means for performing a predetermined calculation using a pulse signal related to the output of the amplifying means and outputting an output corresponding to the displacement. 2. A capacitance that changes differentially according to the displacement to be detected, an amplifying means in which the moving end of this capacitance is connected to the input end, and an inverted current flowing from the output end of this amplifying means to its input end. and negative feedback means for supplying the control signal, and a cycle of repeating the power supply voltage and a predetermined potential in the same phase as the input of the amplification means at a predetermined level of the control signal is applied alternately to the two fixed ends of the capacitance, thereby increasing the control signal. a third driving means for fixing the two fixed ends of the capacitance at a predetermined potential at an inversion level; and a fixed capacitor whose one end is connected to the input end of the amplification means and whose value is smaller than twice the capacitance. and a second driving means that is driven with a voltage that is in phase or in phase with the input of the amplification means and alternately applies 1/2 of the power supply voltage and a predetermined voltage to the other end of the fixed capacitor;
a second microcomputer means that outputs the control signal based on a predetermined procedure, performs a predetermined calculation using a pulse signal related to the output of the amplification means, and outputs an output corresponding to the displacement. Device.