JPH0512729Y2 - - Google Patents

Description

[Detailed description of the invention] <Industrial application field> The present invention relates to a displacement conversion device that converts displacement caused by differential pressure or pressure into an electrical signal via capacitance, and in particular, it is concerned with improving the accuracy of the displacement conversion device. The present invention relates to a displacement conversion device.

<Prior Art> FIG. 8 shows a conventional displacement converter disclosed in Japanese Patent Application Laid-Open No. 57-26711 entitled "Capacitive Displacement Converter", and this will be explained.

C _X is a variable capacitor whose capacitance changes in response to displacement due to pressure, etc. One end of the variable capacitor C _X is connected to the input end of the inverter G ₁ and is also connected to the common potential point COM via the distributed capacitor C _S .

A bidirectional constant current circuit CC is connected between the input and output terminals of inverter _G1 , and its output terminal is connected to the inverter G1.
_G2 is connected to the other end of variable capacitor _CX .
Here, inverters G ₁ and G ₂ form an amplifying means, and the output of inverter G ₂ is connected to the variable capacitor _C
Feedback the voltage in phase with the voltage at the input terminal of _G1 .

Further, the bidirectional constant current circuit CC constitutes a period means that feeds back in phase opposite to the voltage at the input end of the inverter _G1 .

Next, the operation of the displacement converting device shown in FIG. 8 will be explained using the waveform diagram shown in FIG. 9.

When the output of the inverter _G1 is at high level "H" and a voltage +E is generated (Fig. 9A), the rising edge rapidly charges the series circuit of the variable capacitance C _X and the distributed capacitance C _S , and the terminal voltage of the distributed capacitance C _S reaches a constant voltage abruptly, rising almost vertically as shown in Fig. 9B. At this time, the output of the inverter _G1 is at low level "L" and the common potential point COM becomes zero potential, so the charge on the distributed capacitance C _S immediately starts discharging at a constant current i via the bidirectional constant current circuit CC and the output impedance of the inverter _G1 , and the voltage at the input end of the inverter _G1 drops linearly as shown in Fig. 9B.

When the threshold voltage of inverter _G1 drops to _VTH , the output of inverter _G1 becomes high level “H”
is inverted to +E (Fig. 9c), and as a result, the output of inverter _G2 becomes low level "L", so
After _the residual charge of _the variable capacitor C _S is rapidly discharged through _the variable capacitor C The distributed capacitance C _S is charged by the constant current i from the constant current circuit CC, and the inverter
The voltage at the input terminal of _G1 increases linearly (Figure 9c).

When the threshold voltage V _TH is reached, the inverter
Since the output of _G1 is inverted to low level "L" and the output of inverter _G2 becomes high level "H", charging from inverter _G2 is performed again and this operation is repeated.

Here, the changing voltage e ₁₀ across the distributed capacitance C _S with the threshold voltage V _TH as a reference is expressed by the following equation.

e _{10 = C X} E _{/ ( C}

it ₁₀ = e ₁₀ (C _X + C _S ) ...(2) Using equations (1) and (2), t ₁₀ = _C Note that as charging and discharging are repeated, a charge corresponding to the threshold is determined as a reference potential in the distributed capacitance C _S , and charging and discharging are performed around this, so the changing voltage e ₁₀ on the charging side and the discharging side The changing voltage e ₂₀ becomes equal, and by performing charging for ₂₀ minutes of the changing voltage e with the constant current i by the bidirectional constant current circuit CC, the times t ₁₀ and t ₂₀ become equal, and the following equation holds true.

_{t 10 =} t _{20 = EC}
The variable capacitance C _X changes depending on the displacement of the opposing electrodes.

<Problems to be solved by the invention> However, in order to miniaturize the sensor, such conventional displacement transducers reduce the area of the opposing electrodes without changing the displacement span of the electrodes. The value of capacitance C _X becomes smaller, and as a result,
There is a problem in that as the oscillation frequency increases, delays in the oscillation circuit become a problem and cause a decrease in accuracy.

<Means for solving the problems> In order to solve the above problems, this invention
A variable capacitor that changes according to the displacement to be detected, an amplifying means with one end of the variable capacitor connected to an input end, and a negative feedback means for supplying an inverted current from the output end of the amplifying means to the input end thereof. Driving means for driving the other end of the variable capacitor in phase with the input of the amplifying means or fixing it at a predetermined potential; and driving means for driving the other end of the variable capacitor in phase with the input of the amplifying means, one end being connected to the input end of the amplifying means, and the other end being driven with a voltage in phase with the input of the amplifying means. a fixed capacitor, a counting means for counting a predetermined number of pulse signals related to the output of the amplifying means and outputting the result as a control signal, and a first pulse generating means for producing a pulse output having a constant pulse width in synchronization with the pulse signal. , a second pulse generating means for outputting a pulse with a constant pulse width in synchronization with an inverted pulse signal obtained by inverting the pulse signal; and a first switch means for turning on/off the pulse signal using the output of the first pulse generating means;
a second switch means for turning on/off the inverted pulse signal using the output of the second pulse generation means; a third pulse generation means for generating a shift pulse having the same pulse width as the control signal but shifted by a half period from the pulse signal; first and second smoothing means that switch and smooth the output of the first switch means, and third smoothing means that switch and smooth the output of the second switch means using a shift pulse.
A displacement output is produced by executing a predetermined calculation using each output of the first, second, and third smoothing means.

<Example> Hereinafter, an example of the present invention will be described based on the drawings. FIG. 1 is a block diagram showing one embodiment of the present invention. Note that parts having the same functions as those in the prior art are given the same symbols, and the explanation thereof will be omitted as appropriate.

One end of the variable capacitor C _X is connected to the input end of an inverter G ₁ functioning as an amplifying means, and is also connected to the common potential point COM via the distributed capacitor C _S . A bidirectional constant current circuit CC is connected between the input and output terminals of the inverter _G1 to form a negative feedback circuit.
In _addition , _the other end of _the variable _{capacitor C} Its opening and closing is controlled by a control signal CS. Further, a series circuit of a fixed capacitor C _F and an inverter G ₄ is connected between the input and output terminals of the inverter G ₁ .

The output pulse signal is taken out from the output end of the inverter _G1 via the terminal _TL2 . In addition, each inverter G ₁ , G ₃ and NAND gate G ₃ are connected to the power supply voltage +V _Z
is energized by

Next, the operation of the capacitance/time converter CTV ₁ shown in FIG. 1 and configured as described above will be explained with reference to FIGS. 2 and 3.

First, a state in which the control signal CS is at a high level "H" and +E as shown in FIG. 3A will be explained.
In this case, NAND gate _G3 functions simply as an inverter.

When the output terminal of the inverter G ₁ is at a high level "H" during period T _X (FIG. 3C), the input terminal of the inverter G ₁ is connected as shown in FIG. 2A. In this state, a voltage of +V _Z is applied to the other end of the bidirectional constant current circuit CC, so each capacitor is charged and the voltage at the input end of inverter G ₁ rises at a constant rate, reaching its threshold. When the voltage exceeds _VTH (FIG. 3B), the voltage at the output terminal of the inverter _G1 is inverted to the low level "L", resulting in the state shown in FIG. 2B.

The charge in each capacitor immediately before it is reversed from A to _B in Figure ₂ is (C _F + _C If the voltage at the input terminal of G ₁ is V ⁺ , then
From Figure 2 B (C _F +C _X +C _S )V ⁺ -(C _F +C _X )V _Z
becomes. Since the total amount of charge immediately before and after the inversion does not change, the following equation holds true.

(C _F +C _{X + C S} )V _{TH =} (C _F +C _X + _{C S} )V ^{+ −} ( _{C F} + _{C C F + C ​ ​ ​} The period T _X ', which is the time reduced by the constant current i of CC, is given by the following equation.

iT _X ′= _{e 1 ′ ( C F + C} ) V _Z /i ...(7) is obtained.

When the voltage at the input terminal of the inverter _G1 reaches the threshold voltage _VTH of the inverter G1, the output terminal of the inverter _G1 is inverted to a high level "H" and becomes the state shown in FIG. 2A. However, instead of V ⁺ in Figure 2 B, V _TH , 2
The voltage V ^- at the input terminal of inverter G ₁ is substituted for V _TH in Figure A. Therefore, the relationship between the charges immediately before and after the inversion in this case is (C _F +C _X +C _S )V ^- = (C _F +C _X +C _S )V _TH ⁺ - (C _{F + C} Therefore, V ^- = V _TH - {(C _F + C _X ) V _Z / (C _F + C _X + C _S )} ...(8). The second term is a changing voltage _e1 that drops from the threshold voltage _VTH , and the period is the time during which this changing voltage _e1 is increased by the constant current i of the bidirectional constant current circuit CC between the threshold voltages _VTH . T _X
is given by the following equation.

_{iT X = e 1 ( CF + C ​} i...(10) is obtained.

From equations (7) and (10), a pulse signal is obtained at the terminal TL ₂ , in which the periods T _{X and} T _X ′ are equal and each has a period corresponding to the sum of the variable capacitance _C

Next, when the control signal CS is switched to the zero state of low level "L", the other end of variable capacitor C _X remains fixed at high level "H" regardless of the level change at the output end of inverter _G1 . inverter g ₄
Oscillation is repeated through a series circuit with fixed capacitor C _F.

Therefore, in Fig. 2, assuming that the other end of variable capacitor C _X is connected to power supply voltage +V _Z , control signal CS
If we do the same calculation as when is at a high level, we get (5),
In the charge balance equation when formula (8 _{) is} derived, _−C , and the periods T _F1 and T _F1 ' (Figure 3 C) are as follows.

T _F1 =T _F1 '=C _F V _Z /i (11) FIG. 4 is a block diagram showing an embodiment in the case of distributed capacitors whose capacitances vary differentially with each other as variable capacitors.

Inverters G ₁ and G ₅ are connected in series to form an amplifier, and an inverter G ₆ ,
A series circuit of G ₇ and fixed capacitance C _F is connected in positive feedback. Furthermore, a series circuit of inverters G _{8 ,} G ₉ and a bidirectional constant current circuit CC is connected together with inverter G ₆ by negative feedback between the output terminal of inverter G 6 and the input terminal of inverter G ₁ .

Furthermore, a fixed electrode FD ₁ facing the moving electrode MD,
The other ends of the variable capacitors C _H and _CL formed by FD ₂ are the output ends of the inverter G ₆ and the NAND gates G _{10 and 2} , respectively,
Connected via _G11 . The output end of the inverter _G6 is connected to the input end CL of the counter _CT1 , and its n-bit output end _Qo is connected to the NAND gates _G10 , G11 _.
is directly connected to the input end of the inverter _G12 .

DL is a latch, and a control signal CS is applied to its data terminal D, and the level of the control signal CS corresponding to the rising edge of the output of the counter applied to its clock terminal C is outputted via an output terminal Q to a NAND gate _G10 , Apply to the input end of _G11 .

Next, the operation of the capacitance/time converter _CTV2 configured as described above will be explained using the waveform diagram shown in FIG.

First, a case where the control signal CS is at a high level "H" and in the +E state as shown in FIG. 5A will be described. In this case, the output of latch DL is at a high level.

The output of counter CT ₁ is high level “H” (5th
In the state of period T _L in Figure C) (Figure 5 D), the output terminal of the NAND gate _G10 is maintained at a high level "H" and the fixed electrode _FD1 is maintained at a voltage of + _VZ . Therefore, in this case, oscillation continues via the NAND gate _G11 , and considering that -C _H V _Z is always added to the left and right sides in the charge balance equation, and C _H is eventually erased, (7) The following equation is obtained in the same way as equation (10) was derived.

T _L = nV _Z (C _F + C _L )/i ...(12) However, in the case shown in Fig. 4, compared to the case shown in Fig. 1, while counting n bits of the counter, the NAND gates G ₁₀ , G Since the variable capacitor C _L is selected by ₁₁ and repeats oscillation, it is multiplied by n in equation (12).

When the output levels of the inverters G ₁ and G ₅ are inverted n times, the output of the counter CT ₁ is inverted to the low level "L" (FIG. 5C) and enters the state of period T _H. In this state, the output of NAND gate _G11 becomes high level and is fixed at the power supply voltage + _VZ , so the next oscillation period T _H is obtained in the same way as when formula (12) was derived via NAND gate _G10 . .

T _H = nV _Z (C _F +C _H )/i...(13) The above equations (12) and (13) are repeated.

Therefore, fixed capacitance C _F and variable capacitance C _H or
This results in oscillation with periods T _H and T _L corresponding to the sum of C L and C _L.

Next, the control signal CS is inverted to low level "L" as shown in FIG. 5A. At this time, the output of the latch DL becomes low level "L" due to the rising timing of the output of the counter _CT1 (Fig. 5 C).
to be reversed. In this state, NAND gate G ₁₀ ,
The outputs of _G11 are both fixed at high level "H". Therefore, in this case, oscillation continues via the fixed capacitor C _F , and its periods T _F1 and T _F1 ' (Fig. 5 D) are
In the same way as when formula (11) was derived, the following formula is obtained.

T _F2 =T _F2 ′=nC _F V _Z /i ...(14) Furthermore, there is a stray capacitance at both ends of the bidirectional constant current circuit CC.
The periods T _Ld , T _Hd , T _Fd when C _i exists and when there is a delay T _d in the oscillation path as a whole are T _Ld = {nV _Z ( _CL + C _F2 − C _i )/i} + Td... …(15) T _Hd = {nV _Z (C _H +C _F2 −C _i )/i}+Td …(16) T _Fd = {nV _Z (C _F2 −C _i )/i}+Td …(17) becomes.

FIG. 6 is a block diagram showing the overall configuration of the present invention. In the figure, CTV ₂ shown in FIG. 4 is representative as the capacity/time converter.

A capacitance signal _S1 , which is the output of the counter _CT1 , is obtained from the terminal _TL2 . This capacitive signal S ₁ is a monostable circuit that outputs a pulse signal S ₂ with a constant time width T ₀ determined by a resistor R ₁ and a capacitor C ₁ from the output terminal Q.
Applied to input terminal C of _FF1 . A capacitance signal S ₁ is applied to one end of the switch SW ₁ , this capacitance signal S ₁ is opened and closed by a pulse signal S ₂ , and outputted to the other end.

In addition, the capacitance signal S ₁ is inverted by the inverter G ₁₃ and converted into a pulse signal S ₃ , which outputs a pulse signal S ₄ with a constant time width T ₀ ′ (=T ₀ ) determined by the resistor R ₂ and the capacitor C ₂ . It is applied to the input terminal C of the monostable circuit FF ₂ outputting from the terminal Q. A pulse signal _S3 is applied to one end of the switch _SW2 , this pulse signal _S3 is opened and closed by a pulse signal _S4 , and outputted to the other end.

The capacitance signal _S1 is applied to the input terminal C of the n-bit counter _CT2 , and the control signal CS is applied from the n-bit output terminal _Qo to the latch DL of the capacitance/time converter _CTV2.
is applied to the data terminal D of.

One end of the switch SW ₃ of the period control circuit TBC has a constant time width T ₀ obtained at the output end of the monostable circuit FF ₁ .
A pulse signal S ₂ of is applied, and the other end is connected to a resistor R ₃ ,
It is inputted to the non-inverting input terminal (+) of an amplifier Q _A to which the reference voltage V _S is applied to the inverting input terminal (-) via a filter FL ₂ constituted by a capacitor C ₃ . At its output end, a switch is controlled by a control signal CS to obtain a power supply voltage V _Z corresponding to the reference voltage V _S.

This power supply voltage V _Z is used as a power supply voltage for the NAND gates G ₁₀ , G ₁₁ , inverters G ₇ , G ₉ , etc. of the capacitance/time converter CTV ₂ .

(n-1) bit output terminal Qo _-1 of counter _CT2
The pulse signal S ₅ and the pulse signal S ₃ are ANDed by an AND gate G ₁₄ and the output is sent to the counter CT _3.
is applied to the input terminal CL of Also, counter CT ₂
The respective outputs of the output terminals Qo _and Qo _-1 are input to the OR gate _G15 , and the output thereof is applied to the reset terminal R of the counter _CT3 . And the output end of counter CT ₃
A pulse signal _S6 is output from _Qo .

The output of the other end of the switch SW ₁ is applied to the common terminal of the switch SW ₄ , and the output of the first switching terminal is applied to the input end of the buffer Q _B1 via the filter FL ₃ , and the voltage V is applied to the output end of the switch SW 4. Get ₁ .

Further, the output of the second switching terminal of the switch _SW4 is applied to the input terminal of the buffer _QB2 via the filter _FL4 , and a voltage _V2 is obtained at its output terminal.

The opening and closing of the switch _SW4 is controlled by the control signal CS.

In addition, a switch opened and closed with a pulse signal S ₆
The output from the other end of switch SW ₂ is applied to one end of SW ₅ , and the output from the other end is applied to the input end of buffer Q _B3 via filter FL ₅ to obtain voltage V ₃ at its output end.

Subtractor Q _B subtracts voltage V ₂ at the output of buffer Q _B1 from voltage V ₂ at the output of buffer Q _B2 to obtain voltage V ₄ at its output. Further, the subtracter Q _C subtracts the voltage _{V 3 at} the output of the buffer Q _B3 from the voltage V 2 at the output of the buffer Q _B2 to obtain the voltage V ₅ at its output.

Next, the operation of the embodiment configured as above will be explained using the waveform diagram shown in FIG. 7.

The capacitance signal S ₁ (Fig. 7 A) at the output terminal of the counter CT ₁ of the capacitance/time converter CTV ₂ is counted.
CT ₂ counts n bits and outputs the control signal CS shown in Fig. 7 to its output terminal Q _o , and pulse signal S ₅ to its (n-1) bit output terminal Q _o-1 (Fig. 7 H). get. The input terminal of AND gate G ₁₅ receives pulse signal S ₅
and the control signal CS shown in FIG. 7 are input, and the output thereof is input to the reset terminal R of the counter CT ₃ to set the state of the counter CT ₃ to the initial state at the time of startup. The input terminal of AND gate _G14 has a pulse signal
S ₅ and a pulse signal S ₃ (FIG. 7B) obtained by inverting the capacitance signal S ₁ are inputted, respectively, and a pulse signal as shown in FIG. 7H is obtained at the output. The counter _CT3 starts counting in synchronization with the rise of this pulse signal, and a pulse signal _S6 as shown in FIG. 7G is obtained at its output terminal _Qo .

Monostable circuit synchronized with the rise of capacitive signal S ₁
A pulse signal S ₂ with a constant pulse width T ₀ is output from FF ₁ , which opens and closes the switch SW ₄ . While the control signal CS is at a high level (FIG. 7), the switch _SW4 is switched to the filter _FL3 side, and a voltage _V1 is obtained at the output terminal of the buffer _QB1 .

This voltage V ₁ is given by V ₁ =T _Ld V _Z /T ₀ (18).

Also, the control signal CS is at low level (see Figure 7).
During this period, switch SW ₄ is switched to the filter FL ₄ side, and voltage V ₂ is obtained at the output terminal of buffer Q _B2 .

This voltage V ₂ is given by V ₂ =T _Fd V _Z /T ₀ (19).

As for the switch _SW5 , the pulse signal _S6 is shifted by T _Ld from the control signal CS as shown in FIG.
It turns on at this high level. Therefore, during this period, voltage _V3 is obtained at the output terminal of buffer _QB3 via filter _FL5 . This voltage V ₃ is given by V ₃ =T _Hd V _Z /T ₀ (20).

Therefore, the outputs of the subtracters Q _B and Q _C are V ₄ =V ₂ −V ₁ ……(21) V ₅ =V ₂ −V ₃ ……(22) respectively.

In addition, the period control circuit TBC has a period (T _Ld + T _Hd )
is controlled to a constant value, but from equations (15) and (16), the term of the fixed capacitance C _F is set to a constant value K′ (T _Ld + T _Hd ).
By calculating , we obtain nV _Z ( _CL + C _H )/i+K', which is equal to the constant value K''. Therefore, nV _Z (C _L +C _H )/i=K...(23) However, K= K″−K′.

From the above equations (15) to (23), the output voltage V ₀ is given by the following equation.

V ₀ = V ₄ − V ₅ = V _Z (T _Ld − T _Fd − T _Hd + T _Fd ) = nV _Z E (C _L − C _H )/iT ₀ = (KE/T ₀ ) (C _L − C _H ) /(C _L +C _H ) ...(24) Also, the variable capacitances C _H and C _L are each expressed as follows, assuming that the spring constant of the moving electrode MD is K _S and the differential pressure for displacing the moving electrode MD is ΔP. It is shown by the formula.

C _H = C ₀ / (1 + K _S ΔP) ... (25) C _L = C ₀ / (1 - K _S ΔP) ... (26) However, C ₀ is the H when the displacement of the moving electrode MD is zero. , _CL is the capacitance value.

From these formulas, the differential pressure ΔP can be expressed as ΔP=(C _L −C _H )/{K _S (C _L +C _H )} (27).

Therefore, using (24), the output voltage V ₀ becomes V ₀ =(KE/T ₀ )K _S ΔP (28). (K _S ΔP) represents the displacement of the moving electrode MD.

In the above manner, the output voltage proportional to the displacement
You can get V ₀ .

Also, by omitting the periodic control circuit TBC (V ₄ −
The same result can be obtained by outputting the calculation output of V ₅ )/(V ₄ +V ₅ ) or by using (V ₄ +V ₅ ) as the input to the periodic control circuit TBC.

<Effects of the invention> As explained above in detail along with the embodiments, according to the invention, even if the variable capacitance becomes smaller and the oscillation frequency increases due to miniaturization of the sensor, by adding a fixed capacitance, Since it is possible to lower the oscillation frequency and also eliminate delays occurring in the oscillation circuit, accuracy can be improved.
Furthermore, even if there is stray capacitance in the oscillation circuit, it will not be affected by this.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the capacitance/time converter of the present invention, FIG. 2 is an equivalent circuit diagram for explaining the operation of the circuit shown in FIG. 1, and FIG. 3 is the same as that shown in FIG. 1. A waveform diagram showing the waveforms of each part of the example shown in
FIG. 4 is a block diagram showing a second embodiment of the capacitance/time converter of the present invention, FIG. 5 is a waveform diagram showing waveforms of each part of the embodiment shown in FIG. 4, and FIG. A block diagram showing the overall configuration, FIG. 7 is a waveform diagram of each part of the embodiment shown in FIG. 6, FIG. 8 is a block diagram showing a conventional displacement converter, and FIG. 9 is a displacement converter shown in FIG. 8. FIG. C _X , C _H , C _L ...variable capacitance, C _S ...distributed capacitance,
CC...Bidirectional constant current circuit, C _F ...Fixed capacitance, CS
...Control signal, CT ₁ to CT ₃ ...Counter, DL...
...Latch, CTV ₁ , CTV ₂ ...Capacity/time conversion section,
TBC...periodic control circuit, FF ₁ , FF ₂ ...monostable circuit, Q _B1 to Q _B3 ...buffer.

Claims (1)

[Scope of utility model registration request] A variable capacitance that changes depending on the displacement to be detected,
an amplifying means in which one end of the variable capacitor is connected to the input end; a negative feedback means for supplying an inverted current from the output end of the amplifying means to its input end; a driving means for driving or fixing the other end of the variable capacitor to a predetermined potential; and a fixed capacitor, one end of which is connected to the input end of the amplifying means, and the other end of which is driven by a voltage in phase with the input of the amplifying means. , a counting means for counting a predetermined number of pulse signals related to the output of the amplifying means and outputting the same as the control signal; and a first pulse generating means for producing a pulse output having a constant pulse width in synchronization with the pulse signal. a second pulse generating means for outputting a pulse with a constant pulse width in synchronization with an inverted pulse signal obtained by inverting the pulse signal; and a first switch means for turning on/off the pulse signal using the output of the first pulse generating means. , a second switch means for turning on/off the inverted pulse signal using the output of the second pulse generation means, and a third pulse generation means for generating a shift pulse having the same pulse width as the control signal but shifted by a half period from the pulse signal. and first and second smoothing means which switch and smooth the output of the first switch means by the control signal, and third smoothing means which switch and smooth the output of the second switch means by the shift pulse. A displacement converting device comprising: a displacement converting device that performs a predetermined calculation using each output of the first, second, and third smoothing means to output a displacement output.