JP3102589B2 - Boost circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a booster circuit for efficiently obtaining a voltage three times (positive or negative) the power supply voltage from a single DC power supply.

[0002]

2. Description of the Related Art Conventionally, when a voltage three times (positive or negative) of an input voltage is required, power is separately supplied from the outside or boosted by a booster circuit.

[0003]

However, the method of supplying power from the outside requires a new power supply, and the conventional method using a booster circuit has a problem that the conversion efficiency is not good.

[0004] It is an object of the present invention to provide a digital camera without using an external power supply.
It is an object of the present invention to provide a booster circuit that generates a double (positive or negative) voltage and has significantly improved conversion efficiency.

[0005]

For this reason, the booster circuit of the first invention comprises a first capacitor (C1), a second capacitor (C2), a third capacitor (C3), and a fourth capacitor (C4). ), A fifth capacitor (C5), a sixth capacitor (C6), a seventh capacitor (C5) having one end connected to the first output terminal (3) and the other end connected to the ground (2).
7) and an eighth capacitor (C8) having one end grounded to the second output terminal (4) and the other end connected to the ground.
Connecting the first and third capacitors between a power supply terminal (1) and the ground at a first timing .
Fourth, tenth, and ninth switch means (S1, S4, S1
0, S9) and connecting the second, fourth, and sixth capacitors at the first timing to the power terminal and the ground so that the second capacitor is on the power side and the sixth capacitor is on the ground side. 7th, 6th, 16th, 22nd series connected in series
Switch means (S7, S6, S16, S22) and the first, second and fourth capacitors at the first timing so that the second capacitor is on the power supply side and the eighth capacitor is on the ground side. Between the power terminal and the ground .
7, the first 15 of the switch means connected in series via the switching means of the 6 (S15), the fifth in the first timing, a first connecting the seventh capacitor in a closed loop
Seventh and eighteenth switch means (S17 and S18), and the second and fourth capacitors are respectively connected between the power supply terminal and the ground at a second timing alternately generated with the first timing. Fifth , eighth, thirteenth, and fourteenth switch means (S5, S8, S13, and S14), and the first capacitor supplies power to the first, third, and fifth capacitors at the second timing. , Second, third, twelfth, and nineteenth switch means (S2, S5) connected in series between the power terminal and the ground so that the first and fifth capacitors are on the ground side.
S3, S12, S19) and at the second timing, the first, third, and eighth capacitors are connected to the power terminal and the ground so that the first capacitor is on the power side and the eighth capacitor is on the ground side. Between the second and third switch means
Eleventh switch means (S11) connected in series via
And a twentieth and a twenty-first switch means (S20, S21) for connecting the sixth and seventh capacitors in a closed loop at the second timing, wherein the first and the second capacitors are connected at the first timing. A third capacitor is charged with the voltage of the power supply terminal, and the second capacitor is charged at the second timing.
Are charged with the voltage of the power supply terminal, and the sixth capacitor is charged at the first timing by the second and the second capacitors.
The battery is charged with a voltage obtained by adding each voltage of the fourth capacitor and the voltage of the power supply terminal with the same polarity, and the fifth capacitor is charged at the second timing with each voltage of the first and third capacitors and the power supply. The terminal is charged with a voltage obtained by adding the voltages of the terminals with the same polarity, the seventh capacitor is charged with the voltage of the fifth capacitor at the first timing, and the seventh capacitor is charged at the second timing. The battery is charged with a voltage of a sixth capacitor, a voltage that is -3 times the voltage of the power supply terminal is output from the first output terminal, and the eighth capacitor is charged at the second timing with the first and second capacitors. 3 is charged with a voltage obtained by adding the voltages of the capacitors and the voltage of the power supply terminal with the same polarity, and the eighth capacitor is replaced at the first timing by the voltages of the second and fourth capacitors and the power supply terminal. Of the same polarity In Charge in addition to the voltage, and configured to output 3 times the voltage of the power supply voltage from said second output terminal.

A booster circuit according to a second aspect of the present invention comprises a first capacitor (C1), a second capacitor (C2), a third capacitor (C3), a fourth capacitor (C4), and a fifth capacitor (C5). ), A sixth capacitor (C6), a seventh capacitor (C7) having one end connected to the first output terminal (3) and the other end connected to the ground (2), and one end connected to the second output terminal. An eighth capacitor (C8) grounded to (4) and the other end connected to the ground; and a power supply terminal (1) connecting the first, second, third, and fourth capacitors at a first timing.
, A fourth, a fifth, and a fifth
Eighth, ninth, tenth, thirteenth, and fourteenth switch means (S
1, S4, S5, S8, S9, S10, S13, S1
4), seventeenth and eighteenth switch means (S17, S18) for connecting the fifth and seventh capacitors in a closed loop at the first timing, and the sixth and seventh switch means at the first timing. No. 7 connecting capacitor 7 in a closed loop
20th, 21st switch means (S20, S21), and the first capacitor connects the first, third, and fifth capacitors at a second timing alternately generated with the first timing. A fifth capacitor connected in series between the power supply terminal and the ground so that the fifth capacitor is on the ground side.
Second, third, twelfth, and nineteenth switch means (S2, S
3, S12, S19), and at the second timing, the first, third, and eighth capacitors are connected to the power supply terminal such that the first capacitor is on the power supply side and the eighth capacitor is on the ground side. And the third switch between the ground and the ground.
An eleventh switch means (S11) connected in series via a switch means, the second capacitor connecting the second, fourth, and sixth capacitors at the second timing to the power supply side; Seventh, sixth, and sixth capacitors connected in series between the power supply terminal and the ground so that the capacitor is on the ground side .
Sixteenth and twenty-second switch means (S7, S6, S16, S
22) and connecting the second, fourth, and eighth capacitors at the second timing to the power supply terminal and the ground so that the second capacitor is on the power supply side and the eighth capacitor is on the ground side. Between the seventh and sixth switch means during
And a fifteenth switch means (S15) connected in series with each other to charge the first and third capacitors with the voltage of the power supply terminal at the first timing, respectively, Each of the capacitors is charged with the voltage of the power supply terminal, and at the second timing, the fifth capacitor is charged with a voltage obtained by adding the voltages of the first and third capacitors and the voltage of the power supply terminal with the same polarity. At the same time, the sixth capacitor is charged with a voltage obtained by adding the voltages of the second and fourth capacitors and the voltage of the power supply terminal with the same polarity, and the seventh capacitor is charged at the first timing. While charging with the voltage of the fifth capacitor, the sixth capacitor
And outputs a voltage -3 times the power supply voltage from the first output terminal, and connects the eighth capacitor with each voltage of the first and third capacitors at the second timing. While charging with the voltage which added the voltage of the said power supply terminal with the same polarity, and charged with the voltage which added each voltage of the said 2nd, 4th capacitor and the voltage of the said power supply terminal with the same polarity, the said 2nd The output terminal is configured to output three times the power supply voltage.

[0007]

[0008]

[0009]

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below. FIG. 1 is a circuit diagram for explaining the principle. 1 is a power supply terminal (input terminal), 2 is ground (GND), 3 is a first output terminal, and 4 is a second output terminal.
Output terminals, C1 to C8 are capacitors, and S1 to S22 are switches.

In this circuit, the switches S1 to S22 are turned on / off and controlled in the following sequence. (1). S1, S4, S6, S7, S9, S10, S1
5 to S18, S22 are turned on, and the remaining S2, S3, S
5, S8, S11 to S14 and S19 to S21 are turned off. (2). S2, S3, S5, S8, S11 to S14, S
19 to S21 are turned on, and the remaining S1, S4, S6, S
7, S9, S10, S15 to S18, and S22 are turned off. (3). (1) and (2) are repeated.

As a result, in the step (1), the capacitors C1 and C3 are respectively connected in series between the power supply terminal 1 and the ground 2, and each of them is charged with the voltage of Vcc. The capacitors C2, C4 and C6 are connected to the power supply terminal 1 and the ground 2
, The capacitor C6 is connected to the capacitor C6.
2, the total charge (3 Vcc) of the charge of C4 (2 Vcc in total) and the voltage Vcc of the power supply terminal 1 is discharged. Similarly, since the capacitors C2, C4, and C8 are connected in series between the power supply terminal 1 and the ground 2, the capacitor C8 is connected to the capacitor C8.
2, the total charge (3 Vcc) of the charge of C4 (2 Vcc in total) and the voltage Vcc of the power supply terminal 1 is discharged, and a voltage of 3 Vcc is generated at the second output terminal 4. Further, since the capacitors C5 and C7 are connected in a loop, the capacitors C5 and C7 are connected in a loop.
(3 Vcc as described later) is discharged to the capacitor C7 so that the ground 2 side is positive, and a voltage of -3 Vcc is generated at the first output terminal 3.

In the step (2), the capacitors C2,
C4 are respectively connected in series between the power supply terminal 1 and the ground 2, and each of them is charged with the voltage of Vcc. Also, since the capacitors C1, C3, and C5 are connected in series between the power supply terminal 1 and the ground 2, the charge (2Vcc in total) of the capacitors C1 and C3 and the total voltage (3Vcc) of the power supply terminal 1 are added to the capacitor C5. Is discharged. Similarly, the capacitor C
1, C3 and C8 are connected in series between the power supply terminal 1 and the ground 2, so that the charge (2Vcc in total) of the capacitors C1 and C3 and the voltage Vcc of the power supply terminal 1 (3Vcc) is discharged to the capacitor C8. Then, 3 is output to the second output terminal 4.
A voltage of Vcc is generated. Further, capacitors C6 and C7
Is connected in a loop, the electric charge of the capacitor C6 (3 Vcc as described above) is discharged to the capacitor C7 so that the ground 2 side is positive, and -3 is applied to the first output terminal 3.
A voltage of Vcc is generated.

Thus, for the capacitor C7,
The capacitors C5 and C6 discharge alternately, and the capacitor C8
, The capacitors C1 and C3 and the capacitors C2 and C4 discharge alternately, so that the capacitors C7 and C8 have a constant voltage of -3Vc in any of the steps (1) and (2).
c, 3Vcc is charged, and from Vcc to -3Vcc, 3V
The conversion efficiency to cc increases.

FIG. 2 is a circuit diagram of a specific embodiment of this booster circuit. Here, the switches S1 to S3, S5 to S
7, S10 to S12 and S14 to S16 are referred to as P-channel MOS transistors MP1 to MP3, MP5 to MP7,
MP10 to MP12, MP14 to MP16, and switches S4, S8, S9, S13, S17 to S22 are set to N
Channel MOS transistors MN4, MN8, MN
9, MN13, MN17 to MN22. 5
Is an inverter, and 6 is a clock input terminal.

In this circuit, when the clock input to the input terminal 6 is at "L" level, MP1, MN4, M
P6, MP7, MN9, MP10, MP15, MP1
6, only MN17, MN18 and MN22 are turned on and the above step (1) is executed. When the signal is at “H” level, MP2, MP3, MP5, MN8, MP11, MP
12, MN13, MP14, and only MN19 to MN21 are turned on, and the above step (2) is executed. here,
For each half cycle of the clock, the capacitors C5 and C6 are alternately discharged to the capacitor C7, and the capacitors C1 and C3 and C2 and C4 are alternately discharged to the capacitor C8.

The circuit shown in FIG. 1 operates similarly in the following sequence. (A). S1, S4, S5, S8 to S10, S13, S
14, S17, S18, S20, S21 are turned on, and the other S2, S3, S6, S7, S11, S12, S15, S
16, S19 and S22 are turned off. (B). S2, S3, S6, S7, S11, S12, S
15, S16, S19, and S22 are turned on, and other S1, S
4, S5, S8 to S10, S13, S14, S17, S
18, S20 and S21 are turned off. (C). (A) and (B) are repeated.

In this example, in step (A), the capacitors C1 to C4 are each charged with Vcc and the capacitor C5 is charged (3Vc
c) and the charge (3Vc) charged in the capacitor C6.
c) is simultaneously inverted and transferred to the capacitor C7. Also,
In step (B), 3 Vcc obtained by adding the power supply Vcc to the charges of the capacitors C1 and C3 (total of 2 Vcc) is charged in the capacitors C5 and C8,
The capacitors C6 and C8 are charged with 3Vcc obtained by adding the power supply Vcc to the charges of 2 and C4 (2Vcc in total).

That is, in this example, in step (A), the capacitor C7 is simultaneously charged with -3 Vcc from two systems, and in step (B), the capacitor C7 is charged.
8 is charged by 3 Vcc from two systems,
As in the case where steps (1) to (3) are used, the conversion efficiency is increased.

In the embodiment of FIG. 2, the switch S1
Although S22 to S22 are configured by MOS transistors, they can be configured by ordinary bipolar transistors.

[0021]

As described above, according to the present invention, a voltage three times or -3 times the power supply voltage can be obtained without using an external power supply, and the conversion efficiency can be greatly increased. There is an advantage.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a booster circuit for explaining the principle of the present invention.

FIG. 2 is a circuit diagram of a booster circuit according to one embodiment of the present invention.

[Explanation of symbols]

1: power supply terminal (input terminal), 2: ground (GND), 3:
First output terminal, 4: second output terminal, 5: inverter,
6: Clock input terminal.

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H02M 3/07

Claims (2)

(57) [Claims] 1. A first capacitor (C1), a second capacitor (C2), a third capacitor (C3), a fourth capacitor (C4), a fifth capacitor (C5), and a sixth capacitor (C1). C6), a seventh capacitor (C7) having one end connected to the first output terminal (3) and the other end connected to the ground (2), and one end connected to the second output terminal (4). An eighth capacitor (C) having an end connected to the ground.
8) and first and third connecting the first and third capacitors between the power supply terminal (1) and the ground at the first timing, respectively .
Fourth, tenth and ninth switch means (S1, S4, S1
0, S9), at the first timing, the second and fourth capacitors are connected to the power supply terminal and the ground such that the second capacitor is on the power supply side and the sixth capacitor is on the ground side. A seventh, sixth, sixteenth, and twenty-second switch means (S7, S6, S16, S22) connected in series between the second, fourth, and eighth capacitors at the first timing; capacitor power supply side, capacitors eighth the between the ground and the power supply terminal to the ground side
A fifteenth series connected in series via seventh and sixth switch means
Switch means (S15), seventeenth and eighteenth switch means (S17, S18) for connecting the fifth and seventh capacitors in a closed loop at the first timing, and alternately with the first timing 5th , 8th, 13th, and 14th , respectively, connecting the second and fourth capacitors between the power supply terminal and the ground at the second timing generated at
Switch means (S5, S8, S13, S14), and the first, third, and fifth capacitors are connected to the power supply side and the fifth capacitor to the ground side at the second timing. Second, third, twelfth, and nineteenth switch means (S2, S3, S12, S19) connected in series between the power supply terminal and the ground; and the first, third, and third switch means at the second timing. the capacitor of the eighth first capacitor power supply side, between the capacitor eighth and the ground and the power supply terminal to the ground side
Second and 11 connected in series via a third switching means
Switch means (S11), and twentieth and twenty-first switch means (S20, S21) for connecting the sixth and seventh capacitors in a closed loop at the second timing. At the timing, the first and third capacitors are respectively charged with the voltage of the power supply terminal, and at the second timing, the second and fourth capacitors are charged with the voltage of the power supply terminal, respectively. At the timing, the sixth capacitor is charged with a voltage obtained by adding each voltage of the second and fourth capacitors and the voltage of the power supply terminal with the same polarity, and the fifth capacitor is charged at the second timing. 1, charging with a voltage obtained by adding each voltage of the third capacitor and the voltage of the power supply terminal with the same polarity, and charging the seventh capacitor with the voltage of the fifth capacitor at the first timing; At the timing of 2, the seventh capacitor is charged with the voltage of the sixth capacitor, a voltage of -3 times the voltage of the power supply terminal is output from the first output terminal, and at the second timing, The eighth capacitor is charged with a voltage obtained by adding the voltages of the first and third capacitors and the voltage of the power supply terminal with the same polarity, and the eighth capacitor is charged at the first timing with the second and third capacitors. A booster circuit, which is charged with a voltage obtained by adding each voltage of a fourth capacitor and the voltage of the power supply terminal with the same polarity, and outputs a voltage three times the power supply voltage from the second output terminal. 2. A first capacitor (C1), a second capacitor (C2), a third capacitor (C3), a fourth capacitor (C4), a fifth capacitor (C5), and a sixth capacitor (C1). C6), a seventh capacitor (C7) having one end connected to the first output terminal (3) and the other end connected to the ground (2), and one end connected to the second output terminal (4). An eighth capacitor (C) having an end connected to the ground.
8) connecting the first, second, third and fourth capacitors between the power supply terminal (1) and the ground at the first timing . , Ninth, tenth, thirteenth, thirteenth
Fourteen switch means (S1, S4, S5, S8, S9,
S10, S13, S14); Seventeenth and eighteenth switch means (S17, S18) for connecting the fifth and seventh capacitors in a closed loop at the first timing; A twentieth and a twenty-first switch means (S20, S21) for connecting the sixth and seventh capacitors in a closed loop; and a second timing alternately generated with the first timing. A second, a third, a twelfth, and a nineteenth are connected in series between the power supply terminal and the ground so that the fifth capacitor is on the power supply side and the fifth capacitor is on the ground side . Switch means (S2, S
3, S12, S19) and the power supply terminal at the second timing so that the first, third, and eighth capacitors are on the power supply side and the eighth capacitor is on the ground side. An eleventh switch means (S11) connected in series between the power supply and the ground via the third and second switch means, and the second, fourth, and sixth capacitors are connected at the second timing. Seventh, sixth, sixteenth, and twenty-second switch means (S7) connected in series between the power supply terminal and the ground so that the second capacitor is on the power supply side and the sixth capacitor is on the ground side. , S6, S16, S22). At the second timing, the second, fourth, and eighth capacitors are connected to the power supply such that the second capacitor is on the power supply side and the eighth capacitor is on the ground side. It said between the ground and the terminal 7, through the switch means 6 comprises a first 15 of the switch means connected in series (S15), is charged with the said first timing first, third voltage of each said power supply terminals of the capacitor With the second,
Charging each of the fourth capacitors with the voltage of the power supply terminal;
At the second timing, the fifth capacitor is charged with a voltage obtained by adding the voltages of the first and third capacitors and the voltage of the power supply terminal with the same polarity, and the sixth capacitor is charged with the second voltage. , The voltage of the fourth capacitor and the voltage of the power supply terminal are added with the same polarity, and the seventh capacitor is charged with the voltage of the fifth capacitor at the first timing. The battery is charged with a sixth capacitor, and the power supply voltage is negative from the first output terminal.
Outputting the tripled voltage, charging the eighth capacitor at the second timing with a voltage obtained by adding the voltages of the first and third capacitors and the voltage of the power supply terminal with the same polarity, The power supply terminal is charged with a voltage obtained by adding the voltages of the second and fourth capacitors and the voltage of the power supply terminal with the same polarity, and a voltage three times the power supply voltage is output from the second output terminal. Boost circuit.