JP3422928B2 - Charge pump drive circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a charge pump type drive circuit, and more particularly to a charge pump type drive circuit used in a drive portion of a so-called high side switch having a switching element on the upper side of a load. Is.

[0002]

2. Description of the Related Art FIG. 5 is a diagram showing a conventional charge pump type drive circuit. 6A is a diagram showing voltage waveforms at various points in the charge pump drive circuit shown in FIG.
6B is a diagram showing a waveform of the input control signal A, and FIG.
(C) is a diagram showing a waveform of the input pulse signal B.

As can be seen from FIG. 5, this charge pump type drive circuit comprises a charge pump circuit CPC 'and a switch circuit SW'. The charge pump circuit CPC ′ has a diode D1 connected in series.
~ D4 and inverter X12 also connected in series
To X3, these diodes D1 to D4 and the inverter X
1 to X3 and capacitors C1 to C3 connected in parallel
And C3. Further, the switch circuit SW ′ is a bipolar transistor Q that forms a current mirror circuit on the front side of the charge pump circuit CPC ′.
1, Q2, a resistor R1 and a MOS transistor M1 connected in series to the bipolar transistor Q1, and a MOS transistor M2 connected to the rear side of the charge pump circuit.

The input control signal A shown in FIG. 6 (b) is applied to the control terminal of the MOS transistor M1, and the input pulse signal B shown in FIG. 6 (c) is applied to the inverter X1. When the input control signal A changes from low level to high level, the MOS transistor M1 is turned on and the bipolar transistors Q1 and Q2 are turned on. Therefore, charging of the charge pump capacitor C1 is started. The capacitor C1 is charged from the power supply VDH via the bipolar transistor Q2 and the diode D1 when the output of the inverter X1 is at a low level, and the charge of about VDH-VF is stored.

Next, when the output of the inverter X1 changes from the low level to the high level, VDL-VF of the charges accumulated in the capacitor C1 moves to the capacitor C2. Therefore, the capacitor C2 has about VDH + V
The charge of DL-VF is stored. By repeating the same operation, the capacitor C3 has about VDH + 2VDL.
A charge of -2VF is stored. Such an operation is continuously performed in synchronization with the input pulse signal B. Therefore, assuming that the output of the inverter X3 is the node m1 and the node between the diodes D3 and D4 is the node m2,
The voltage waveforms of these nodes m1 and m2 are as shown in FIG. As can be seen from FIG. 6A, this charge pump circuit CPC ′ allows the power source VDH
Higher voltage is generated.

[0006]

As can be seen from the above description, the conventional charge pump drive circuit accumulates electric charges with respect to the ground potential and secures the drive power supply for the high side switch. However, M, which is a switching element used for the power supply VDH and the output stage,
Since a voltage higher than the withstand voltage of the OS transistor MOUT (voltage drive type device including MOSFET, IGBT, etc.) is applied to the drive circuit including the charge pump circuit, the device withstand voltage of the capacitors C1 to C3 is the power supply VDH or the output. There is a problem that it is necessary to use one having a breakdown voltage higher than that of the stage element.

That is, since a voltage higher than the power supply VDH is applied to the capacitors C1 to C3, the charge pump capacitors C1 to C3 are bipolar transistors Q1 and Q which are switching elements.
A breakdown voltage higher than 2 or the like is required. Generally, in the IC process, a capacitor is formed using an insulator such as an oxide film, and the breakdown voltage of the capacitor is determined by the oxide film thickness. Therefore, in order to obtain the breakdown voltage of this capacitor, it is necessary to make this oxide film thick.
If the oxide film is thickened, the capacity per unit area is decreased, and the chip size becomes large, which is a disadvantage. In addition, when a capacitor is constructed using components, there is a problem that a capacitor having a high breakdown voltage must be selected.

Therefore, the present invention has been made in view of the above problems, and an object thereof is to provide a charge pump type drive circuit in which a voltage higher than that of a power source is not applied to a capacitor forming a charge pump. To do.
That is, it is an object of the present invention to provide a charge pump type drive circuit in which a withstand voltage of a capacitor forming a charge pump does not depend on a power supply.

[0009]

In order to solve the above problems, a charge pump type drive circuit according to the present invention generates a first power supply voltage and a second power supply voltage higher than the first power supply voltage. A power source and a second of the power source
A plurality of diodes connected in series to the power supply voltage of
In a plurality of inverters connected in series, an input pulse signal is input to the first-stage inverter, and the pulse output of each inverter is the second power supply voltage and the second power supply voltage. A plurality of inverters that oscillate between a third power supply voltage that is a constant voltage drop from
A plurality of capacitors that respectively connect the nodes between the plurality of inverters in parallel, and the output of the diode in the last stage of the plurality of diodes is connected to the control terminal of the output transistor. Along with the output of the diode in the last stage and the control terminal of the transistor for output, the diode in the last stage and the transistor for output are disconnected only when the transistor for output is in the off state. For this reason, a switch circuit on the rear stage side is provided.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS [First Embodiment] A first embodiment of the present invention is used in a charge pump type drive circuit by driving the charge pump circuit with a negative power source based on a power source. The voltage applied across the capacitor is reduced. Furthermore, by inserting a switch circuit between the charge pump circuit and the output transistor, the charge pump circuit and the output transistor are separated, and both ends of the capacitor are irrespective of whether the output transistor is in the ON state or the OFF state. The voltage applied to is independent of the power supply. Hereinafter, a more detailed description will be given based on the drawings.

FIG. 1 is a diagram showing a charge pump type drive circuit according to a first embodiment of the present invention. Figure 2 (a) shows
It is a figure which shows the voltage waveform in each place of the charge pump type drive circuit shown in this FIG. 1, FIG.2 (b) is a figure which shows the waveform of the input control signal A, and FIG.2 (c) is the figure of the input pulse signal B. It is a figure which shows a waveform.

As can be seen from the left side of FIG. 1, a power supply VDH is connected between the ground terminal GND and the node n1. As can be seen from the right side of FIG. 1, an n-type MOS transistor MOUT which is an output element and a resistor RL are connected in series between the node n1 and the ground GND. MOS transistor M for this output
A node n2 is provided between OUT and the node n1. This node n2 and the MOS transistor MOUT
Between the control terminals of the limiting resistor R2 and the diodes D1 to D1.
D4 and the n-type MOS transistor M3 are connected in series, and nodes n3 to n7 are formed between them. A resistor R3 is connected between the control terminal of the MOS transistor M3 and the node n6. A node n8 is formed between the ground GND and the resistor RL, and an npn-type bipolar transistor Q3 and an n-type MOS transistor M2 are connected in series between the node n8 and the node n7. ing. The control terminal of the bipolar transistor Q3 is connected to its output terminal and constitutes a so-called diode connection. A node n9 between the bipolar transistor Q3 and the MOS transistor M2 and a node n10 between the MOS transistor M3 and the resistor R3 are commonly connected to each other. The input control signal A is input to the control terminal of the MOS transistor M2 via the inverter X4. The MOS transistors M2 and M3 and the inverter X described above.
4, the resistor R3, and the bipolar transistor Q3,
The switch circuit SW1 in this embodiment is configured.

A node n11 is provided below the node n1 in the figure.
A closed loop LP formed by closing the loop is provided. A negative power supply VDL is provided in the closed loop LP on the lower side of the node n11 in the drawing. The negative power source VDL is a negative power source with the voltage of the power source VDH as a reference. With the closed loop LP, the inverters X1 and X
The voltage VDH and the voltage VDH-VDL are supplied to the logic circuit composed of 2 and X3. The input pulse signal B is input to the first stage inverter X1 located on the input side of the logic circuit. Inverters X1, X2, X3
Nodes n12 and n13 are formed between the respective nodes. The output of the inverter X3 is connected to the node 14. The capacitor C1 is connected between the node n12 and the node n3. The capacitor C2 is connected between the node n13 and the node n4. Output of inverter X3 (node n14) and node n
A capacitor C3 is connected between the first and second terminals. That is, the diodes D1 to D4 and the inverters X1 to X3
, And capacitors C1 to C3 are connected in parallel. The diodes D1 to D4, the inverters X1 to X3, and the capacitors C1 to C3 form a charge pump circuit CPC in this embodiment.

Next, the operation of this charge pump type drive circuit will be described.

As can be seen from FIG. 1, the input pulse signal B shown in FIG. 2 (c) is input to the inverter X1.
The input pulse signal B performs an amplitude operation between the voltage VDH (high level) and the voltage VDH-VDL (low level). As can be seen from FIG. 2A, the inverters X1 to X
The output of 3 also swings between VDH and VDH-VDL. In this amplitude operation, since the inverters X1 to X3 are connected in series, the inverters X1 to X3 are connected.
The adjacent outputs of the above are in a relationship of being alternately inverted from each other.

Focusing on the capacitor C1, when the output of the inverter X1 is VDH-VDL, that is, when the output of the inverter X1 is at a low level, the electric charge of VDL-VF is accumulated through the limiting resistor R2 and the diode D1. To be When the output of the inverter X1 changes to VDH, that is, when the output of the inverter X1 changes to a high level, the electric charge stored in the capacitor C1 is charged in the capacitor C2. Next, the output of the inverter X2 is V
When the voltage changes to DH-VDL, that is, when the output of the inverter X2 changes to low level, this capacitor C
2 includes the charge transferred from the capacitor C1 and 2
The electric charge of VDL-2VF is stored. Similarly, when the output of the inverter X2 changes to VDH, that is, when the output of the inverter X2 changes to high level, the electric charge accumulated in the capacitor C2 is charged in the capacitor C3. Next, the output of the inverter X3 is VDH-V.
When it changes to DL, that is, when the output of the inverter X3 changes to low level, this capacitor C3 has
3VDL-in combination with the charge transferred from the capacitor C2
A charge of 3VF is stored. The above operation is continuously performed, and the nodes n3, n4, n5, n12, n
The voltage at 14 changes as shown in FIG.

Whether the charge pump circuit CPC is driven or not is controlled by the input control signal A. That is, as shown in FIG. 2B, when the input control signal A becomes high level, this charge pump drive circuit operates. As you can see from Figure 1,
The input control signal A is input to the control terminal of the MOS transistor M2 via the inverter X4. That is, when the input control signal A changes from the low level to the high level, the MOS transistor M2 changes from the on state to the off state. When the MOS transistor M2 is turned off, the diode transistor-connected MOS transistor M3 is turned on by the resistor R3 from the diode D4, and as a result, the output of the diode D4 is input to the control terminal of the MOS transistor MOUT. The voltage of the node n7 at this time is, as shown in FIG.
The voltage is higher than the voltage of DH. That is, VD
Forward resistance V of diode D4 from H + 3 (VDL-VF)
The voltage has dropped by the ON resistance of F and the MOS transistor M3. With this voltage, the MOS transistor MOUT is turned on, and the output voltage V is output from the resistor RL.
out is output. As can be seen from FIG. 2B, when the input control signal A changes from high level to low level, M
The OS transistor M2 changes from the off state to the on state,
Diode connected bipolar transistor Q3
Is also turned on. Therefore, the node n7 becomes the ground level. Therefore, the MOS transistor MOUT is turned off. At the same time, since the node n10 also becomes the ground level, the MOS transistor M3 is also turned off. That is, when the input control signal becomes low level, the voltage is extracted from the control terminals of the MOS transistors MOUT and M3, and the diode D4 which is the output of the charge pump circuit and the MOS transistor MOUT are disconnected. Therefore, although the voltage of the node n7 is at the ground level, the voltage of the node n6 is approximately V
Maintained at DH-4VF. In this case, the voltage of the node n5 is VDH-3VF, the voltage of the node n4 is VDH-2VF, and the voltage of the node n3 is VDH-.
It is VF.

As described above, according to the charge pump type drive circuit of the present embodiment, the charge pump circuit uses the voltage of the power source VDH as a reference, and the negative side voltage VDH-
Since it is driven by VDL, the voltage applied across the capacitors C1 to C3 used in the charge pump circuit CPC can be reduced. That is, as can be seen from FIG. 2, since the output pulses of the inverters X1 to X2 are made to oscillate in the width of the voltage VDH to the voltage VDH-VDL, the voltage applied to the capacitors C1 to C3 can be made smaller than in the conventional case. it can. Moreover, the voltage applied to these capacitors C1 to C3 is VDL-
Since it is expressed by VF, 2VDL-2VF, and 3VDL-3VF, the voltages stored in the capacitors C1 to C3 can be made independent of the power supply VDH.

Further, as can be seen from FIG. 1, when the MOS transistor MOUT is turned off, this MO
Since the control terminal of the S-transistor MOUT and the diode D4 that is the output of the charge pump circuit are separated, it is not necessary to drop the node n6 to the ground level. Therefore, a high voltage depending on VDH is applied to the capacitor C3 and the like. It can be prevented from being applied. That is, it can be prevented that the node n14 becomes VDH and the node n5 becomes the ground level and a high voltage is applied to the capacitor C3 and the like.

[Second Embodiment] A second embodiment of the present invention is a charge pump type drive circuit according to the above-described first embodiment, in which a switch circuit is also provided in the preceding stage of the charge pump type drive circuit. The steady current flowing when the drive circuit is off is reduced to reduce power consumption. Hereinafter, a more detailed description will be given based on the drawings. FIG. 3 is a diagram showing a charge pump type drive circuit according to the second embodiment of the present invention. Figure 4 (a)
FIG. 4 is a diagram showing voltage waveforms at various points in the charge pump drive circuit shown in FIG. 1, FIG. 4 (b) is a diagram showing a waveform of the input control signal A, and FIG. 4 (c) is an input pulse signal. It is a figure which shows the waveform of B.

As can be seen from FIG. 3, the charge pump drive circuit according to the second embodiment is similar to the first embodiment in that the switch circuit SW1 is provided at the subsequent stage of the charge pump circuit CPC.
And a switch circuit SW2 is additionally provided in the preceding stage of the charge pump circuit CPC.

The switch circuit SW2 on the preceding stage side includes a bipolar transistor Q1, a resistor R1, and a MOS transistor M1 which are connected in series between the power supply VDH and the ground. A bipolar transistor Q2 is connected to the bipolar transistor Q1 so that the control terminals are commonly connected. That is,
The bipolar transistors Q1 and Q2 form a current mirror circuit. The output terminal of the bipolar transistor Q2 is connected to the diode D1 of the charge pump circuit. The input control signal A is input to the control terminal of the MOS transistor M1. The input control signal A is also input to the inverter X4 of the switch circuit SW1 on the subsequent stage side. Except for these points, the configuration of the charge pump drive circuit according to the second embodiment is similar to that of the first embodiment.

Next, the operation of the charge pump drive circuit according to the second embodiment will be described. As can be seen from FIG. 4, the operation of the charge pump drive circuit according to the second embodiment is the first operation. The operation is similar to that of the charge pump drive circuit according to the embodiment.

As described above, according to the charge pump type drive circuit of this embodiment, since the switch circuit SW2 is also provided in the preceding stage side of the charge pump circuit, the steady state current is turned off in the charge pump type drive circuit. Can be prevented from flowing and power consumption can be suppressed. More specifically, as can be seen from FIG. 1, in the first embodiment, when the charge pump drive circuit is in the off state, the MOS transistor M2 is in the on state. Therefore, a steady current flows from the diode D4, which is the output of the charge pump circuit CPC, to the ground via the resistor R3 and the MOS transistor M2. On the other hand, as can be seen from FIG. 3, also in the second embodiment,
When the charge pump drive circuit is off, the MOS transistor M2 is on. Further, since the MOS transistor M1 is turned off, the bipolar transistor Q2 forming the current mirror is also turned off. That is, the switch circuit SW2 in the preceding stage of the charge pump circuit CPC is turned off. Therefore, it is possible to prevent the voltage supply from the power supply VDH to the charge pump circuit CPC from being cut off, and prevent a steady current from flowing from the diode D4 to the ground via the resistor R3 and the MOS transistor M2. Therefore, it is possible to reduce power consumption when the charge pump drive circuit is in the off state.

The present invention is not limited to the above embodiment, and various modifications can be made. For example, as can be seen from FIGS. 1 and 3, the MOS transistor MO has a protection function.
It is also possible to linearly reduce the voltage of the control terminal of the UT. In this case, if the voltage of the control terminal of the MOS transistor MOUT is reduced, the voltage of the control terminal of the MOS transistor M3 can be reduced at the same time. That is,
The present invention can be applied to the case where the voltage at the node n9 is linearly controlled by using an operational amplifier or the like.

As can be seen from FIGS. 2 and 4, in the above-described embodiment, the input pulse signal B is continuously supplied regardless of the high level / low level state of the input control signal A. However, the input pulse signal B can be linked with the state of the input control signal A. That is, it is possible to supply the input pulse signal B only during the period when the input control signal A turns on the charge pump drive circuit, that is, during the high state. By doing so, the power consumption can be reduced by the amount of the unnecessary input pulse signal B.

[0027]

As described above, according to the present invention,
Since the charge pump circuit is driven by the negative power supply with the power supply as the reference, the voltage applied to both ends of the capacitor used in the charge pump circuit can be reduced and the breakdown voltage of the capacitor does not depend on the power supply. You can

[Brief description of drawings]

FIG. 1 is a diagram showing an example of a circuit configuration of a charge pump drive circuit according to a first embodiment of the present invention.

2A is a diagram showing voltage waveforms at various points in the charge pump drive circuit shown in FIG. 1, FIG. 2B is a diagram showing an input control signal, and FIG. 2C is a diagram showing an input pulse signal. It is a figure.

FIG. 3 is a diagram showing an example of a circuit configuration of a charge pump type drive circuit according to a second embodiment of the present invention.

4A is a diagram showing voltage waveforms at various points in the charge pump drive circuit shown in FIG. 3, FIG. 4B is a diagram showing an input control signal, and FIG. 4C is a diagram showing an input pulse signal. It is a figure.

FIG. 5 is a diagram showing an example of a circuit configuration of a conventional charge pump drive circuit.

6A is a diagram showing voltage waveforms at various points in the charge pump drive circuit shown in FIG. 5, FIG. 6B is a diagram showing an input control signal, and FIG. 6C is a diagram showing an input pulse signal. It is a figure.

[Explanation of symbols]

SW1 Switch circuit on the rear side SW2 Switch circuit on the front side CPC charge pump circuit X1-X4 inverter D1-D4 diode M1 to M3 MOS transistors MOS transistor for MOUT output Q1 to Q3 bipolar transistors

─────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-4-172963 (JP, A) JP-A-2-164268 (JP, A) JP-A-8-306870 (JP, A) (58) Field (Int.Cl. ⁷ , DB name) H01L 21/822 H01L 27/04 H02M 3/07

Claims (4)

(57) [Claims] 1. A power supply for generating a first power supply voltage and a second power supply voltage higher than the first power supply voltage, and a power supply connected in series to the second power supply voltage of the power power supply. A plurality of diodes and a plurality of inverters connected in series, wherein an input pulse signal is input to the first stage inverter, and the pulse output of each inverter is A plurality of inverters that oscillate between the second power supply voltage and a third power supply voltage that is a constant voltage drop, each node between the plurality of diodes, and each node between the plurality of inverters. and a plurality of capacitors in parallel connected to each comprise a diode of the last stage in the plurality of diodes
When the output is connected to the control terminal of the output transistor
In both cases, the output of the diode in the last stage and the output transistor
Between the control terminal of the transistor, the output transistor
Only in the off state, the diode in the last stage and the front
The switch on the rear side to disconnect the output transistor.
Switch circuit is provided, a charge pump drive circuit. 2. The latter-stage switch circuit includes an input terminal connected to a diode in the last stage, an output terminal connected to a control terminal of the output transistor, and the last resistor via a first resistor. A first transistor having a control terminal connected to the stage diode, an input terminal connected to the control terminal of the first transistor, and an output terminal connected to the first power supply voltage of the power supply; A second transistor having a control terminal to which an input control signal for switching between the ON state and the OFF state of the output transistor is input; and an input terminal and a control terminal connected to the control terminal of the output transistor. , Ji according to claim 1, wherein the second and a output terminal connected to the input terminal of the transistor, comprising a third transistor, a Charge pump type drive circuit. 3. When the output transistor is in an off state between the input of the first stage diode of the plurality of diodes and the second power supply voltage of the power source, the first stage Second of the diode and the power supply
The charge pump drive circuit according to claim 1 or 2 , further comprising: a switch circuit on a front stage side for disconnecting the power supply voltage from the power supply voltage. 4. The fourth-stage switch circuit has a fourth transistor having an input terminal connected to a second power supply voltage of the power supply, and one end side thereof is connected to an output terminal and a control terminal of the fourth transistor. Also, a second resistor, an input terminal connected to the other end of the second resistor, an output terminal connected to the first power supply voltage of the power source, and an ON state and an OFF state of the output transistor. A fifth transistor having a control terminal for receiving an input control signal for switching between, and an input terminal connected to the second power supply voltage of the power supply, and connected to the control terminal of the fourth transistor. a control terminal, said having a plurality of output terminals connected to the first stage of the diodes of the diode, according to claim 3, characterized in that it comprises a sixth transistor, a A charge pump type drive circuit.