JP3064573B2 - Boost circuit - Google Patents
Boost circuitInfo
- Publication number
- JP3064573B2 JP3064573B2 JP3272138A JP27213891A JP3064573B2 JP 3064573 B2 JP3064573 B2 JP 3064573B2 JP 3272138 A JP3272138 A JP 3272138A JP 27213891 A JP27213891 A JP 27213891A JP 3064573 B2 JP3064573 B2 JP 3064573B2
- Authority
- JP
- Japan
- Prior art keywords
- capacitor
- voltage
- switch
- power supply
- terminal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/0083—Converters characterised by their input or output configuration
- H02M1/009—Converters characterised by their input or output configuration having two or more independently controlled outputs
Description
【０００１】[0001]
【産業上の利用分野】本発明は、直流入力電圧の正側、
負側をその入力電圧よりも０．５倍だけ拡大して出力す
る昇圧回路に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention
The present invention relates to a booster circuit that enlarges the negative side by 0.5 times the input voltage and outputs the result.
【０００２】[0002]
【従来の技術】従来から、デジタル回路とアナログ回路
が混在する集積回路では、アナログ回路部分の電源をデ
ジタル回路部分のそれと共用するか、外部から別に供給
するか、あるいはデジタル回路部分に供給されている電
源を昇圧して±２Ｖｃｃの電圧を作り、これをアナログ
回路部分の電源として供給していた。2. Description of the Related Art Conventionally, in an integrated circuit in which a digital circuit and an analog circuit are mixed, the power of the analog circuit is shared with that of the digital circuit, separately supplied from the outside, or supplied to the digital circuit. The voltage of the power supply is stepped up to generate a voltage of ± 2 Vcc, and this voltage is supplied as power for the analog circuit portion.
【０００３】[0003]
【発明が解決しようとする課題】しかし、アナログ回路
部分の電源をデジタル回路部分の電源と共用する方法で
はアナログ回路部分の電源電圧のマージン（余裕）が少
なくなり、また別電源を供給する方法では新たに電源を
用意しなければならず、更にデジタル回路部分の電源を
利用して±２Ｖｃｃの電圧を作る方法ではマージンの取
り過ぎで電力消費が大きくなるという問題があった。However, in the method in which the power supply of the analog circuit portion is shared with the power supply of the digital circuit portion, the margin of the power supply voltage in the analog circuit portion is reduced. A new power source must be prepared, and the method of generating a voltage of ± 2 Vcc by using the power source of the digital circuit portion has a problem that power consumption is increased due to excessive margin.
【０００４】本発明の目的は、デジタル回路とアナログ
回路が混在する集積回路に適用して、アナログ回路部分
の電源電圧のマージンが少なくなることはなく、別電源
も必要とせず、また無駄な電力消費も生じないようにし
た昇圧回路を提供することである。An object of the present invention is to apply the present invention to an integrated circuit in which a digital circuit and an analog circuit are mixed, so that the margin of the power supply voltage in the analog circuit portion is not reduced, no separate power supply is required, and wasted power is not required. An object of the present invention is to provide a booster circuit in which consumption does not occur.
【０００５】[0005]
【課題を解決するための手段】このため本発明の昇圧回
路は、第１のコンデンサ（Ｃ１）と、第２のコンデンサ
（Ｃ２）と、一端が電源端子（１）に接続され他端が第
１の出力端子（３）に接続された第３のコンデンサ（Ｃ
３）と、一端が接地（２）に接続され他端が第２の出力
端子（４）に接続された第４のコンデンサ（Ｃ４）と、
前記第１のコンデンサの一端と前記第２のコンデンサの
一端に接続された第１のスイッチ（Ｓ１）と、前記第１
のコンデンサの前記一端と前記電源端子との間に接続さ
れた第２のスイッチ（Ｓ２）と、前記第１のコンデンサ
の他端と前記電源端子との間に接続された第３のスイッ
チ（Ｓ３）と、前記第１のコンデンサの前記他端と前記
第３のコンデンサの前記他端との間に接続された第４の
スイッチ（Ｓ４）と、前記第２のコンデンサの前記一端
と接地との間に接続された第５のスイッチ（Ｓ５）と、
前記第２のコンデンサの他端と前記接地との間に接続さ
れた第６のスイッチ（Ｓ６）と、前記第２のコンデンサ
の前記他端と前記第４のコンデンサの前記他端との間に
接続された第７のスイッチ（Ｓ７）とを有し、前記第
１，第３，第６のスイッチの一群と前記第２，第４，第
５，第７のスイッチの一群を交互にオン／オフさせ、前
記第１の出力端子から前記電源端子の電圧の１．５倍の
電圧を出力させ、前記第２の出力端子から電源端子の電
圧の−０．５倍の電圧を出力させるように構成した。Therefore, a booster circuit according to the present invention comprises a first capacitor (C1) and a second capacitor (C1).
(C2), one end is connected to the power supply terminal (1) and the other end is
1 is connected to a third capacitor (C) connected to the output terminal (3).
3) and one end is connected to the ground (2) and the other end is a second output.
A fourth capacitor (C4) connected to the terminal (4);
One end of the first capacitor and the other end of the second capacitor
A first switch (S1) connected to one end;
Connected between the one end of the capacitor and the power supply terminal.
The second switch (S2) and the first capacitor
A third switch connected between the other end of the
(S3), the other end of the first capacitor and the
A fourth capacitor connected between the third capacitor and the other end;
A switch (S4) and the one end of the second capacitor;
A fifth switch (S5) connected between the switch and ground,
Connected between the other end of the second capacitor and the ground.
The sixth switch (S6) and the second capacitor
Between the other end of the fourth capacitor and the other end of the fourth capacitor
And a seventh switch (S7) connected thereto.
A group of first, third and sixth switches and the second, fourth and fourth switches
5, turn on / off a group of seventh switches alternately,
The voltage of the first output terminal is 1.5 times the voltage of the power supply terminal.
A voltage is output from the second output terminal to the power supply terminal.
It was configured to output a voltage of -0.5 times the pressure .
【０００６】[0006]
【作用】本発明では、第１の出力端子に入力電圧の１．
５倍の電圧が発生し、第２の出力端子に入力電圧の半分
の負の電圧が発生する。つまり、正側が入力電圧よりも
その入力電圧の０．５倍だけ高く、負側が０．５倍だけ
低い電圧となる。このため、デジタル回路とアナログ回
路が混在する集積回路において、上記入力電圧をデジタ
ル回路の電源電圧とすることにより、上記得られた正負
電圧を適正なマージンで消費電力を抑えたアナログ回路
用電源として利用できる。According to the present invention, the first output terminal receives the input voltage of 1.0.
Five times the voltage is generated, and a negative voltage that is half the input voltage is generated at the second output terminal. That is, the positive side is higher than the input voltage by 0.5 times the input voltage, and the negative side is lower by 0.5 times the input voltage. For this reason, in an integrated circuit in which digital circuits and analog circuits are mixed, the input voltage is used as the power supply voltage of the digital circuit. Available.
【０００７】[0007]
【実施例】以下、本発明の実施例について説明する。図
１はその昇圧回路の原理回路図である。１は電源端子
（入力端子）、２は接地、３は第１出力端子、４は第２
出力端子である。またＳ１〜Ｓ７はスイッチ、Ｃ１〜Ｃ
４はコンデンサである。Embodiments of the present invention will be described below. FIG. 1 is a principle circuit diagram of the booster circuit. 1 is a power supply terminal (input terminal), 2 is ground, 3 is a first output terminal, and 4 is a second output terminal.
Output terminal. S1 to S7 are switches, C1 to C
4 is a capacitor.
【０００８】この回路では、次のシーケンスでスイッチ
Ｓ１〜Ｓ７をオン／オフ制御する。 （１）．Ｓ１、Ｓ３、Ｓ６をオンし、Ｓ２、Ｓ４、Ｓ
５、Ｓ７をオフする。 （２）．Ｓ２、Ｓ４、Ｓ５、Ｓ７をオンし、Ｓ１、Ｓ
３、Ｓ６をオフする。 （３）．（１）と（２）を繰り返す。In this circuit, the switches S1 to S7 are turned on / off in the following sequence. (1). S1, S3 and S6 are turned on, and S2, S4 and S
5. Turn off S7. (2). S2, S4, S5, and S7 are turned on, and S1, S
3. Turn off S6. (3). (1) and (2) are repeated.
【０００９】この結果、（１）のステップでは、コンデ
ンサＣ１、Ｃ２に電源電圧Ｖｃｃが印加して、コンデン
サＣ１はＶｃｃ−０．５Ｖｃｃの電圧、またコンデンサ
Ｃ２は０．５Ｖｃｃ−０（接地電位）の電圧となるよう
電荷が充電される。As a result, in the step (1), the power supply voltage Vcc is applied to the capacitors C1 and C2, and the capacitor C1 has a voltage of Vcc-0.5 Vcc, and the capacitor C2 has a voltage of 0.5 Vcc-0 (ground potential). Is charged so as to have a voltage of
【００１０】次の（２）のステップでは、コンデンサＣ
１がコンデンサＣ３とループ接続され、またコンデンサ
Ｃ２がコンデンサＣ４とループ接続される。よって、コ
ンデンサＣ３にはコンデンサＣ１の０．５Ｖｃｃの電荷
が充電され、そのコンデンサＣ３の負極側に電源端子１
の電圧Ｖｃｃが印加するので、第１出力端子３には１．
５Ｖｃｃの電圧が出力する。また、コンデンサＣ４には
コンデンサＣ２の０．５Ｖｃｃの電荷が接地側を正とし
て充電されるので、第２出力端子４には−０．５Ｖｃｃ
の電圧が出力する。In the next step (2), the capacitor C
1 is loop-connected to the capacitor C3, and the capacitor C2 is loop-connected to the capacitor C4. Accordingly, the capacitor C3 is charged with the charge of 0.5 Vcc of the capacitor C1, and the power supply terminal 1 is connected to the negative electrode side of the capacitor C3.
Is applied to the first output terminal 3.
A voltage of 5 Vcc is output. Since the capacitor C4 is charged with the charge of 0.5 Vcc of the capacitor C2 with the ground side being positive, the second output terminal 4 has -0.5 Vcc.
Output voltage.
【００１１】以上の出力端子３、４の電圧は、上記した
（１）、（２）の動作の繰返しが少ないうちは、上記し
た電圧１．５Ｖｃｃ、−０．５Ｖｃｃに達しないが、所
定回数以上繰り返して行われることにより、コンデンサ
Ｃ３、Ｃ４の充電電荷が充分となり、安定して発生す
る。The voltage at the output terminals 3 and 4 does not reach the above-mentioned voltages of 1.5 Vcc and -0.5 Vcc while the repetition of the above operations (1) and (2) is small. By repeating the above, the charged charges of the capacitors C3 and C4 become sufficient, and the charges are stably generated.
【００１２】図２は上記した昇圧回路の具体的回路図で
ある。ここでは、スイッチＳ１〜Ｓ４をＰチャンネルＭ
ＯＳトランジスタＭＰ１〜ＭＰ４で構成し、スイッチＳ
５〜Ｓ７をＮチャンネルＭＯＳトランジスタＭＮ５〜Ｍ
Ｎ７で構成している。５〜７はインバータ、８はクロッ
ク入力端子である。FIG. 2 is a specific circuit diagram of the booster circuit described above. Here, the switches S1 to S4 are set to P channel M
The switch S is composed of OS transistors MP1 to MP4.
5 to S7 are N-channel MOS transistors MN5 to MN
N7. 5 to 7 are inverters, and 8 is a clock input terminal.
【００１３】この回路では、入力端子８に入力するクロ
ックが”Ｌ”レベルのとき、ＭＰ１、ＭＰ３、ＭＮ６が
オンして他がオフし、これによりコンデンサＣ１、Ｃ２
に電荷が充電される。また、”Ｈ”レベルのとき、ＭＰ
２、ＭＰ４、ＭＮ５、ＭＮ７がオンして他がオフし、こ
れによりコンデンサＣ１の電荷がコンデンサＣ３に転移
し、コンデンサＣ２の電荷がコンデンサＣ４に転移す
る。In this circuit, when the clock input to the input terminal 8 is at the "L" level, MP1, MP3 and MN6 are turned on and the others are turned off, whereby the capacitors C1 and C2 are turned off.
Is charged. When the signal is at the “H” level, MP
2, MP4, MN5 and MN7 are turned on and the others are turned off, whereby the charge of the capacitor C1 is transferred to the capacitor C3, and the charge of the capacitor C2 is transferred to the capacitor C4.
【００１４】図３は図２におけるＰチャンネルＭＯＳト
ランジスタＭＰ１に並列に、ＮチャンネルＭＯＳトラン
ジスタＭＮ１を接続してトランスミッショゲート化した
ものであって、入力端子８に印加するクロックが”Ｌ”
レベルのときに、このＭＮ１がＭＰ１と同時にオンして
その部分の導通抵抗を低下させ、”Ｈ”レベルのときに
ＭＰ１と同時にオフする。FIG. 3 shows an N-channel MOS transistor MN1 connected in parallel with the P-channel MOS transistor MP1 in FIG. 2 to form a transmission gate. The clock applied to the input terminal 8 is "L".
When the level is at the level, the MN1 is turned on at the same time as the MP1 to reduce the conduction resistance of the portion, and when at the "H" level, the MN1 is turned off at the same time as the MP1.
【００１５】なお、上記した説明ではスイッチＳ１〜Ｓ
７をＭＯＳトランジスタで構成しているが、通常のバイ
ポーラトランジスタで構成することもできる。In the above description, the switches S1 to S
Although 7 is constituted by a MOS transistor, it can be constituted by a normal bipolar transistor.
【００１６】[0016]
【発明の効果】以上のように本発明の昇圧回路によれ
ば、＋Ｖｃｃの電圧を入力して＋１．５Ｖｃｃの電圧
と、−０．５Ｖｃｃの電圧を得ることができる。このた
め、デジタル回路とアナログ回路が混在する集積回路の
アナログ回路の電源用としてこれを利用することによ
り、別電源を用意する必要はない。デジタル回路にＶｃ
ｃを印加させ、このＶｃｃを昇圧することで入力電圧の
正側、負側に各々０．５倍だけ広がった電圧を得ること
ができるので、適正マージンで無駄な消費電力も生じな
くなる。As described above, according to the booster circuit of the present invention, a voltage of +1.5 Vcc and a voltage of -0.5 Vcc can be obtained by inputting a voltage of + Vcc. For this reason, it is not necessary to prepare a separate power supply by using this as a power supply for an analog circuit of an integrated circuit in which a digital circuit and an analog circuit are mixed. Vc for digital circuit
By applying c and boosting this Vcc, it is possible to obtain a voltage that is 0.5 times wider on each of the positive side and the negative side of the input voltage, so that there is no wasteful power consumption with a proper margin.
【図１】 本発明の原理の説明のための昇圧回路の回
路図である。FIG. 1 is a circuit diagram of a booster circuit for explaining the principle of the present invention.
【図２】 本発明の一実施例の昇圧回路の回路図であ
る。FIG. 2 is a circuit diagram of a booster circuit according to one embodiment of the present invention.
【図３】 本発明の別の実施例の昇圧回路の回路図で
ある。FIG. 3 is a circuit diagram of a booster circuit according to another embodiment of the present invention.
１：電源端子（入力端子）、２：接地、３：第１出力端
子、４：第２出力端子、５〜７：インバータ、８：クロ
ック入力端子、ＭＰ１〜ＭＰ４：ＰチャンネルＭＯＳト
ランジスタ、ＭＮ１、ＭＮ５〜ＭＮ７：ＮチャンネルＭ
ＯＳトランジスタ。1: power supply terminal (input terminal), 2: ground, 3: first output terminal, 4: second output terminal, 5 to 7: inverter, 8: clock input terminal, MP1 to MP4: P-channel MOS transistor, MN1, MN5 to MN7: N channel M
OS transistor.
───────────────────────────────────────────────────── フロントページの続き (58)調査した分野(Int.Cl.7，ＤＢ名) H02M 3/07 ──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int.Cl. 7 , DB name) H02M 3/07
Claims (1)
デンサ（Ｃ２）と、一端が電源端子（１）に接続され他
端が第１の出力端子（３）に接続された第３のコンデン
サ（Ｃ３）と、一端が接地（２）に接続され他端が第２
の出力端子（４）に接続された第４のコンデンサ（Ｃ
４）と、前記第１のコンデンサの一端と前記第２のコン
デンサの一端に接続された第１のスイッチ（Ｓ１）と、
前記第１のコンデンサの前記一端と前記電源端子との間
に接続された第２のスイッチ（Ｓ２）と、前記第１のコ
ンデンサの他端と前記電源端子との間に接続された第３
のスイッチ（Ｓ３）と、前記第１のコンデンサの前記他
端と前記第３のコンデンサの前記他端との間に接続され
た第４のスイッチ（Ｓ４）と、前記第２のコンデンサの
前記一端と接地との間に接続された第５のスイッチ（Ｓ
５）と、前記第２のコンデンサの他端と前記接地との間
に接続された第６のスイッチ（Ｓ６）と、前記第２のコ
ンデンサの前記他端と前記第４のコンデンサの前記他端
との間に接続された第７のスイッチ（Ｓ７）とを有し、 前記第１，第３，第６のスイッチの一群と前記第２，第
４，第５，第７のスイッチの一群を交互にオン／オフさ
せ、 前記第１の出力端子から前記電源端子の電圧の１．５倍
の電圧を出力させ、前記第２の出力端子から電源端子の
電圧の−０．５倍の電圧を出力させるようにした ことを
特徴とする昇圧回路。(1)The first capacitor (C1) and the second capacitor
A capacitor (C2) and one end connected to the power supply terminal (1)
A third capacitor having an end connected to the first output terminal (3)
(C3), one end is connected to the ground (2) and the other end is connected to the second
A fourth capacitor (C) connected to the output terminal (4)
4), one end of the first capacitor and the second capacitor
A first switch (S1) connected to one end of the capacitor;
Between the one end of the first capacitor and the power supply terminal
A second switch (S2) connected to the first switch;
A third terminal connected between the other end of the capacitor and the power terminal.
Switch (S3) and the other of the first capacitor
Connected between the other end of the third capacitor and the other end of the third capacitor.
A fourth switch (S4), and a second switch (S4)
A fifth switch (S) connected between the one end and ground;
5) and between the other end of the second capacitor and the ground.
A sixth switch (S6) connected to the second switch;
The other end of the capacitor and the other end of the fourth capacitor
And a seventh switch (S7) connected between A group of the first, third, and sixth switches and the second,
A group of the fourth, fifth and seventh switches are alternately turned on / off.
Let 1.5 times the voltage of the power supply terminal from the first output terminal
Of the power supply terminal from the second output terminal.
Output voltage of -0.5 times of voltage That
Characteristic booster circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3272138A JP3064573B2 (en) | 1991-09-24 | 1991-09-24 | Boost circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3272138A JP3064573B2 (en) | 1991-09-24 | 1991-09-24 | Boost circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0591726A JPH0591726A (en) | 1993-04-09 |
| JP3064573B2 true JP3064573B2 (en) | 2000-07-12 |
Family
ID=17509619
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3272138A Expired - Fee Related JP3064573B2 (en) | 1991-09-24 | 1991-09-24 | Boost circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3064573B2 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4417262B2 (en) | 2003-01-17 | 2010-02-17 | ティーピーオー、ホンコン、ホールディング、リミテッド | Charge pump circuit |
| US8310218B2 (en) * | 2007-08-08 | 2012-11-13 | Advanced Analogic Technologies, Inc. | Time-multiplexed-capacitor DC/DC converter with multiple outputs |
| WO2012063494A1 (en) * | 2010-11-12 | 2012-05-18 | 旭化成エレクトロニクス株式会社 | Charge pump circuit, method for controlling same, and semiconductor integrated circuit |
-
1991
- 1991-09-24 JP JP3272138A patent/JP3064573B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0591726A (en) | 1993-04-09 |
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