JP3012558B2 - Power supply circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a power supply circuit for reducing power consumption, and more particularly to a power supply circuit for reducing power consumption supplied to a logic circuit such as a microcomputer.

[0002]

2. Description of the Related Art An internal step-down circuit that steps down a power supply voltage and supplies the stepped-down voltage to another circuit such as a logic circuit of a semiconductor integrated circuit. There is a circuit that divides a power supply voltage and supplies the divided voltage to a driving transistor, thereby reducing power consumption in the driving transistor. One example is disclosed in JP-A-63-12146.
No. 7 discloses this as an “internal step-down circuit”. According to this example, although not shown , two voltage dividing capacitors C1 and C2 arranged between the power supply voltage Vdd1 and the ground voltage.
, A voltage holding capacitor C3, and these voltage dividing capacitors C3.
And five switches S1 to S5 for converting a connection relationship between the first and second capacitors C1 and C3 and a voltage holding capacitor C3. Further, a main component is a circuit portion which has a Barton circuit configuration by a differential amplifier and a driving transistor M5. And
However, power consumption of the driving transistor is reduced by reducing the power supply voltage to the driving transistor, and it is difficult to sufficiently reduce power consumption.

Conventionally, a power supply voltage is supplied as it is to a logic circuit, so that in a logic circuit operating at a specific frequency, the voltage becomes excessive with respect to the minimum operating voltage of the logic circuit, and the logic circuit consumes power. In some cases, the current increased more than necessary. For this reason, power consumption has been reduced by using a regulator circuit to reduce the power supply voltage to an optimum voltage including an operation margin with respect to the minimum operation voltage of the logic circuit and to supply the voltage to the logic circuit. In addition, the power consumption is further reduced by using a Herber circuit to reduce the power supply voltage to half and supplying it to the logic circuit, as compared with the case where a regulator circuit is used.

First, a power supply circuit using a regulator circuit will be briefly described. As shown in FIG. 7, the reference voltage generation circuit 11a driven by the power supply voltage VDD1 is preset so as to generate a voltage V11 obtained by adding an operation margin to the minimum operation voltage of the logic circuit 21 operating at a certain specific frequency. I do. Using this voltage V11 as a reference voltage, it is connected to one input of a comparator circuit 11b driven by the power supply voltage VDD1. The output of the comparator 11b is connected to the gate of the driving transistor MP11, and the source of the driving transistor MP11 is supplied from the power supply voltage VDD1. The drain of the driving transistor MP11 is connected to the other input as negative feedback to the comparator circuit 11b, and is further supplied to the logic circuit 21 as power. At this time, as the voltage V12 supplied to the logic circuit 21, a voltage equivalent to the voltage V11 set in advance by the reference voltage generation circuit 11a is generated. As a result, the voltage V stepped down from the power supply voltage VDD1 by the regulator circuit 11 is applied to the logic circuit 21.
12, the power consumption of the logic circuit 21 is reduced by the optimized voltage.

Next, a power supply circuit using a herber circuit will be briefly described. As shown in FIG. 8, the ground voltage GND
Is the switch SW14 and the power supply voltage VDD1 is the switch S
W11, and the power supply voltage VDD1
Between the switches SW11 to SW14 and the ground voltage GND.
Are connected in series. Further, the clock signals CK11 and CK12 are input and the clock signal CK11 is connected to the gate control of the switches SW11 and SW13, and the clock signal CK12 is connected to the gate control of the switches SW12 and SW14. Switches SW11 to SW1
4 is turned on when the gate voltage is at the Hi level,
It is formed from an element that is in a non-conductive state when it is at the w level. Further, a connection point CH11 between the switch SW11 and the switch SW12, a switch SW13, and a switch SW14.
A capacitor C11 is connected to a connection point CL11 between the switch SW12 and the connection point V13 between the switches SW12 and SW13, and a capacitor C12 is connected to the ground voltage GND. By connecting these capacitors C11 and C12 in series and parallel in correspondence with the clock signals CK11 and CK12, a voltage with the power supply voltage VDD1 reduced to 1/2 is generated at the output V13 of the herber circuit 3.

[0006]

However, the first problem here is that in a power supply circuit using a conventional regulator circuit, an output voltage is arbitrarily generated in a range from a power supply voltage to a ground voltage. However, a loss of power consumption has occurred in the driving transistor in the output stage of the regulator circuit.

That is, since the current flowing through the driving transistor is equivalent to the current consumption flowing into the logic circuit, the power consumption obtained by multiplying the current by the source-drain voltage generated in the driving transistor becomes a loss. ing.

A second problem is that, in a power supply circuit using a conventional Herber circuit, the first problem, that is, loss of power consumption generated in a driving transistor can be reduced. Cannot be set to the power supply voltage / 2 or more. However, by increasing the number of capacitors connected to the herber circuit, the power supply voltage / 2
Although the above voltage can be generated, in a logic circuit such as a microcomputer that consumes a large amount of power, it is difficult to incorporate the LSI into the LSI due to the problem of the capacitance value of the capacitor. Results in an increase in the number of terminals.

That is, the Herber circuit generates a voltage by connecting a plurality of capacitors in series and parallel at a certain specific clock, and therefore can generate only a voltage corresponding to the number of capacitors. That is, if two capacitors are connected in series and parallel, the voltage that can be generated from this Herber circuit is the power supply voltage / 2.

[0010]

SUMMARY OF THE INVENTION A power supply circuit according to the present invention has been made in order to solve the above-mentioned problems. In a power supply circuit for lowering a power supply voltage and supplying the voltage to a logic circuit, a first power supply voltage is provided. And a voltage obtained by stepping down the second power supply voltage by the regulator circuit to the herber circuit,
It is possible to generate a voltage equal to or higher than the first power supply voltage / 2 from the herber circuit.

According to a power supply circuit of the present invention, in a power supply circuit for supplying a voltage obtained by stepping down a power supply voltage to each logic circuit of a semiconductor device, a first power supply voltage and the first power supply voltage A step-down voltage obtained by stepping down a power supply voltage obtained by connecting two power supply voltages in series to an arbitrary voltage by a regulator circuit;
A herber circuit that receives a first clock signal and a second clock signal, wherein the herber circuit is connected between the first power supply voltage and a ground voltage in response to the first clock signal. A first switch circuit group that connects a plurality of capacitors provided in series, and one end of a certain capacitor among the plurality of capacitors is connected to the step-down voltage, which is the output of the regulator circuit, and one end of the remaining capacitor is connected to the A second switch circuit group connected to a ground voltage and connecting the other ends of the plurality of capacitors in parallel with the output voltage of the Herber circuit, wherein the plurality of capacitors are connected to the first clock signal and the first clock signal. A predetermined voltage is generated by repeating series or parallel connection by the second clock signal.

According to another aspect of the present invention, a power supply circuit for supplying a voltage obtained by stepping down a power supply voltage to each logic circuit of a semiconductor device has a potential lower than the power supply voltage between the power supply voltage and a reference voltage. And a cascade switching means for every one of at least four cascaded switching means which are turned on / off repeatedly in response to a clock signal between the power supply voltage and the output of the regulator circuit. A first capacitor connected in parallel to the load output in accordance with the high / low level of the clock signal, and alternately connected to a parallel connection and a serial output. And a second capacitor.

More specifically, a voltage obtained by stepping down the first power supply voltage and the second power supply voltage by the regulator circuit is supplied to a herber circuit composed of a switch group in which a plurality of capacitors are connected in parallel. Further, the Herber circuit is operated by an input clock signal, and particularly when the capacitors are in parallel with the ground potential, the second power supply voltage is supplied to the certain capacitor among the capacitors instead of the ground potential. The voltage is raised by connecting to the potential lowered by the circuit, and as a result, a voltage of (first power supply voltage + regulator output voltage) / 2 can be generated from the Herber circuit.

[Operation] For example, in terms of specific numerical values, an application for driving a microcomputer at a voltage of 3.0 V by connecting two 1.5 V batteries in series.
In the system, assuming that the minimum operating voltage of this microcomputer at a specific frequency is 2.0 V, a 3.0 V voltage as a first power supply and a 2.0 V voltage as a second power supply.
5V voltage was further reduced by a regulator circuit.
The voltage (3.0 v + 1.0 v) / 2 generated by the Herber circuit using the v voltage as a supply source can be used as the power supply of the microcomputer.

[0015]

BEST MODE FOR CARRYING OUT THE INVENTION

[First Embodiment] FIG. 1 is a block diagram of a power supply circuit according to a first embodiment of the present invention. In FIG. 1, the power supply circuit includes a first power supply voltage VDD1, a second power supply voltage VDD2, a regulator circuit 1, a herber circuit 3, and a logic circuit 2 which is a load of the power supply circuit.

As for the second power supply voltage VDD2, the voltage V2 stepped down by the regulator circuit 1 is supplied to the switch SW4 of the herber circuit 3, and the first power supply voltage VDD1 is supplied to the switch SW.
1 respectively. In the regulator circuit 1, the comparator circuit 1b receives the voltage V1 generated from the reference voltage generation circuit 1a, controls the gate of the driving transistor MP1, and outputs a voltage V2 obtained by stepping down the second power supply voltage VDD2. The herber circuit 3 switches the switch SW1 between the first power supply voltage VDD1 and the voltage V2 obtained by stepping down the second power supply voltage VDD2 by the regulator circuit 1.
To SW4 are connected in series.

Further, the clock signals CK1 and CK2 are input and the clock signal CK1 is connected to the gate control of the switches SW1 and SW3, and the clock signal CK2 is connected to the gate control of the switches SW2 and SW4. Switches SW1 to S
W4 is formed of an element which is turned on when a gate voltage for supplying a clock signal is at a Hi level and is turned off when it is at a Low level. Further, the switch SW1
A capacitor C1 is connected to a connection point CH1 between the switch SW2 and the connection point CL1 between the switches SW3 and SW4, and a connection point V between the switch SW2 and the switch SW3.
3 and the ground voltage GND are connected to a capacitor C2. Further, the output V3 of the herber circuit 3 is supplied as power to the logic circuit 2 as a load. Previous capacitor C
1 and the capacitor C2 are connected in series and parallel according to the states of the clock signals CK1 and CK2, so that a voltage of (VDD1 + V2) / 2 is generated at the output V3 of the herber circuit.

Next, a description will be given with reference to the timing chart of FIG. As shown in FIG. 2, the clock signal CK1
And CK2 are alternately input high and low alternately, and the switches SW1 to SW4 start operating. First, the clock signal CK1 is at the Hi level and the clock signal CK2 is at the L level.
At the time of the low level, the switches SW1 and SW3
Is in a conducting state, the switches SW2 and SW4 are in a non-conducting state, and the capacitors C1 and C2 are connected in series between the first power supply voltage VDD1 and the ground voltage GND (state A in FIG. 3). The clock signal CK1 is Lo.
At the w level, when the clock signal CK2 is at the Hi level, the switches SW1 and SW3 are turned off, the switches SW2 and SW4 are turned on, the capacitor C2 is connected to the ground voltage GND, and the capacitor C2 is turned on.
1 is connected to the voltage V2 obtained by stepping down the second power supply voltage VDD2 by the regulator circuit 1, and the other sides of the respective capacitors C2 and C1 are connected to each other (state B in FIG. 3). By repeating the connection state of the capacitor in time series with respect to the clock signals CK1 and CK2, (VD
D1 + V2) / 2 is generated and supplied to the logic circuit 2 as a power supply.

[Second Embodiment] FIG. 4 shows a second embodiment of the present invention.
FIG. 3 is a block diagram of a power supply circuit according to the embodiment. In FIG. 4, the power supply voltage V is as low as 3 V as a specific number.
The power supply circuit includes a DD, a regulator circuit 1, a herber circuit 3, and a logic circuit 2 which is a load of the power supply circuit.
The regulator circuit 1 is connected between the power supply voltage VDD and the ground of the reference voltage and further outputs a low voltage V1. The reference voltage generation circuit 1a outputs the voltage V1 generated by the reference voltage generation circuit 1a to a non-inverting input terminal. Comparator circuit 1 that receives as a negative feedback circuit from the drain of the FET to the inverting input terminal
b, a p-type MOS (MP1) of a driving transistor whose source receives the output of the comparator circuit 1b at its gate and receives the power supply voltage VDD, and a resistor R1 connected between the drain of the p-type MOS MP1 and ground. Consists of

The herber circuit 3 cascade-connects the p-type MOSs Q1 to Q3 and the n-type MOS Q4 between the power supply voltage VDD and the drain of the driving transistor MP1 of the regulator circuit 1, and receives a clock signal at its input. A connection point between the inverters IN1 and IN2 and a gate of the p-type MOS Q2 are connected to each other, and an output of the inverter IN2 is connected to the p-type MOS Q
1, Q3 and the gate of the n-type MOS Q4.
Further, a connection point CH1 between the p-type MOSs Q1 and Q2 and the MOSQ
A capacitor C1 is connected between a connection point CL1 between the gates 3 and Q4, and a capacitor C2 and a logic circuit 2 as a load are connected in parallel between the connection point between the p-type MOSs Q1 and Q2 and ground.

Next, the operation of this embodiment will be described. The regulator circuit 1 outputs a constant voltage smaller than the power supply voltage VDD by the reference voltage generation circuit 1a, and V2 is supplied to the drain of the output MOS transistor MP1 of the negative feedback circuit.
Output, for example, 0.4V. The resistor R1 may be a capacitor and has a constant load. Next, the clock signal is repeatedly supplied high and low as shown in FIG. During the period of FIG. 5, the inverter IN2
Is low, MOS Q2 and Q4 are off, MOS Q1 and Q3 are on, and output V3 is
The voltage of the capacitor C2 is obtained as shown in FIG. Also,
Since the output of the inverter IN2 is high during the period of FIG. 5, the MOSs Q2 and Q4 are turned on, and the MOSs Q1 and Q4 are turned on.
3, the output V3 becomes a voltage obtained by adding the voltage of the capacitor C2 to the voltage of the capacitor C2 and the output of the regulator circuit 1 as shown in FIG. Therefore, the state of FIG. 6 changes to the state of FIG. 6, and the voltage V3 is averaged.

As shown in FIG. 6, this capacitor C1,
By repeating the connection state of C2 in a time series with the clock signal CK, (VD
D + V2) / 2 is generated, and the output V3 is supplied to the logic circuit 2 as a power supply. Assuming that the load resistance of the logic circuit 2 is 85 kΩ, the logic circuit 2 has an IDD
= 20 μA flows.

As described above, for a digital circuit and an analog circuit such as a microcomputer and a logic circuit operating on a low-voltage power supply, the power consumption of the conventional MOS transistor is reduced, and the constant voltage of the regulator circuit is varied. Any power supply voltage equal to or lower than the voltage can be obtained.

The minimum operating voltage of the logic circuit is VD
Even if D / 2 or more, the output voltage of the Herber circuit is V
Since the voltage can be finely adjusted to DD / 2 or more, the logic circuit can be effectively operated by the power supply circuit of the present invention. As a result, it is possible to obtain an effect that the current viewed from the battery voltage, which is a characteristic of the Herber circuit, is half the logic current.

Here, in the conventional power supply circuit including only the regulator circuit, it is assumed that the current as viewed from the battery power supply = 20 μA + the regulator circuit current.

In the power supply circuit of the present embodiment, by setting the ground voltage of the Herber circuit to, for example, 0.4 V (the output of the regulator circuit), an output voltage of 1.7 V is generated. The power supply circuit using this method has a current of 10 μA (= 20 μA / 2) +
Regulator circuit current + Herber circuit current (about 0 μA), and the minimum operating voltage of the logic circuit is the battery voltage VDD.
The power supply current of the power supply voltage VDD can be reduced to a value of about 1/2 even if the characteristics are half or more of the above, and the effect of the Herber circuit can be sufficiently obtained.

Although the above embodiment has been described using specific values, the effects of the present invention are not limited to this, and a wide range of applications are possible by following technical ideas.

[0028]

According to the present invention, a voltage higher than the first power supply voltage / 2, that is, a voltage obtained by stepping down the first power supply voltage and the second power supply voltage by the regulator circuit, is supplied to the herber circuit. There is an effect that a voltage of (first power supply voltage + regulator output voltage) / 2 can be generated from the output of the herber circuit. That is, in the operation of the Herber circuit, in particular, when the capacitor is in parallel with the ground potential, by connecting the second power supply voltage to the voltage stepped down by the regulator circuit instead of the ground potential only for a specific capacitor, This is because a voltage obtained by adding the regulator output voltage / 2 to the first power supply voltage / 2 is generated at the output of the herber circuit.

Further, by supplying a voltage of (first power supply voltage + regulator output voltage) / 2 generated by the herber circuit as a power supply of the logic circuit, it is possible to reduce the power consumption. That is, the power consumption is reduced by generating a voltage stepped down from the second power supply voltage by the regulator circuit, particularly by the Herber circuit using a supply source of the voltage obtained by stepping down the first power supply voltage and the second power supply voltage by the regulator circuit. Loss can be reduced.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a power supply circuit according to an embodiment of the present invention.

FIG. 2 is a timing diagram of the embodiment shown in FIG.

FIG. 3 is a diagram showing a connection state of the capacitor according to the embodiment shown in FIG. 1;

FIG. 4 is a configuration diagram of a power supply circuit according to an embodiment of the present invention.

FIG. 5 is a timing diagram of the embodiment shown in FIG. 1;

FIG. 6 is a diagram illustrating a capacitor connection state of the embodiment shown in FIG. 1;

FIG. 7 is a configuration diagram of a regulator circuit of a conventional power supply circuit.

FIG. 8 is a configuration diagram of a herber circuit of a conventional power supply circuit.

[Explanation of symbols]

 1,11 Regulator circuit 2,21 Logic circuit 3,31 Herber circuit 1a, 11a Reference voltage generation circuit 1b, 11b Comparator circuit C1, C2, C3, C12, C13 Capacitor MP1, MP11 Driving transistor SW1-SW4, SW11-SW14 Switch CK1, CK2, CK11, CK12 Clock signal V1, V11 Reference voltage V2, V12 Output voltage of regulator circuit V3, V13 Output voltage of herber circuit

Continuation of the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H02M 3/07 G06F 1/26

Claims (3)

(57) [Claims] 1. A power supply circuit for supplying a voltage obtained by stepping down the power supply voltage to each logic circuit of the semiconductor device, the second power supply voltage to the first power supply voltage first power supply voltage
, A regulator circuit for outputting a step-down voltage obtained by stepping down a power supply voltage to an arbitrary voltage, and a first clock signal and a regulator circuit synchronized with the first clock signal.
A second clock signal having an opposite phase to the second clock signal. The herber circuit includes a plurality of capacitors connected in series between the first power supply voltage and a ground voltage. a first switch circuit group to the plurality of a certain voltage of the herbalists circuit other end of the particular capacitor connected to the output of the step-down voltage at one end of the regulator circuit of a particular capacitor of a capacitor
A second switch circuit group connected to an output and respectively connecting the plurality of capacitors in parallel; and a second capacitor between a voltage output of the herber circuit and a ground point.
Includes a capacitor, a power supply circuit in which the plurality of capacitors and wherein the generating a predetermined voltage by repeating the series or parallel connection by the second clock signal and the first clock signal. 2. A power supply circuit according to claim 1, before
Serial Each switch circuit group composed of MOS transistors, the power supply circuit, wherein said first power supply voltage and the second power supply voltage is a battery power supply. 3. The power supply circuit according to claim 1, wherein two capacitors are connected to the first switch circuit group by the first clock signal and the second clock signal.
And repeating the series or parallel connection by turning on / off the second switch circuit group and the second switch circuit group , the predetermined voltage becomes ｛(first power supply voltage + regulator circuit output voltage)
/ 2}.