JPH11145413A - Semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent inversion between values of internal voltage to be outputted to each step-down circuit due to noise by a method, wherein a second internal power source is generated by stepping down a first internal power source using a second step-down circuit. SOLUTION: An external power source VCC controlled by the reference voltage VR1 is dropped, it is applied to a step-down circuit 1 which creates a prescribed internal voltage V11, an internal power source V11 controlled by the reference voltage VR2 is dropped, and a step-down circuit 2 which creates a prescribed voltage V12 is provided. The step-down circuits 1 and 2 output internal voltages V11 and V12 of normal value, respectively. Then, when the step-down circuits 1 and 2 malfunctions due to noise, etc., and the internal voltage V11 and V12 are changed, the internal voltage V11 is dropped by the step-down circuit 2. As a result, the internal voltage V12 does not exceed the internal voltage V11. That is, the internal voltages are V11=V12 even in the worst case, and the inversion between the internal voltages can be prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to a semiconductor integrated circuit device having an internal step-down circuit for generating a plurality of internal voltages for low-voltage operation from an external power supply voltage.

[0002]

2. Description of the Related Art In recent years, in a semiconductor integrated circuit device, especially a large capacity semiconductor memory device, the gate oxide films of these transistors have been made thinner with the miniaturization of transistor elements according to the scaling rule. On the other hand, the supply power supply voltage has been reduced due to the problem of the withstand voltage of the gate oxide film.
However, at present, the power supply voltage of a semiconductor integrated circuit device equipped with this type of semiconductor storage device has been reduced, and it cannot be said that other logic circuits and the like are not necessarily miniaturized as in the case of the storage device. Since there are many devices that need to be supplied with the same power supply voltage, the change is gradual. As a result, if an external power supply is used directly in this type of semiconductor integrated circuit device, there is a possibility that the gate oxide film of a transistor element constituting a storage circuit or the like composed of miniaturized elements is destroyed and an operation failure is caused. .

Therefore, in recent semiconductor integrated circuit devices including large-capacity semiconductor memory devices, a step-down circuit for stepping down an external power supply voltage is provided on a semiconductor chip in order to solve these problems, and the step-down circuit of the step-down circuit is provided. An internal voltage that is an output is used as a power supply voltage of an internal circuit.

Further, in order to reduce the current consumption of the semiconductor integrated circuit device, a portion requiring high-speed operation and a portion not requiring high-speed operation are used by changing the power supply voltage, or a case having a sense amplifier driven in an overdrive mode is used. Requires multiple step-down internal voltages. The use of a plurality of step-down internal voltages in this manner is very useful in improving the degree of circuit design. On the other hand, it is more important to design a step-down circuit in consideration of the influence of noise and the like.

For example, referring to FIGS. 6A and 6B showing circuit diagrams of an example of a delay circuit using a known cascade-connected inverter, the effect of a plurality of internal voltages will be described.
A first delay circuit using a single internal voltage VI1 as a power supply as shown in FIG. 6A includes a P-type MOS transistor P71 having a gate as an input, a source connected to the internal voltage VI1, and a drain as an output. A plurality of inverters each comprising an N-type MOS transistor N71 having a gate input, a source connected to the ground, and a drain connected to the drain of the transistor P71 are connected in cascade in a plurality of stages, and have a capacitor C71 inserted between the output of each stage and the ground.

A second delay circuit using two internal voltages VI1 and VI2 (VIl> VI2) as shown in FIG. 6B provides a reverse bias between a source P + diffusion layer and an N-type well region. P-type MOS transistor P72 having a gate connected to the input, a source connected to the internal voltage VI2, and a drain connected to the input, a gate connected to the input, the source connected to the ground, and a drain connected to the drain of the transistor P72. N-type MOS transistor N
A plurality of inverters 71 are connected in cascade, and a capacitor C71 is inserted between the output of each stage and ground.

As compared with the first delay circuit using a single internal voltage VI1 as a power supply, two internal voltages VI1 and VI2 are used.
In the second delay circuit using (Vl> VI2), the threshold voltage | VT | is increased by applying a reverse bias between the P + diffusion layer of the source of the P-type MOS transistor P72 and the N-type well region. As a result, the current supply capability of the transistor P72 can be reduced even with the same gate voltage.

Therefore, when comparing the delay circuit for realizing the same delay time with the area occupied on the semiconductor chip, the second delay circuit using two internal voltages can reduce the number of transistors. , Can be made smaller than the single internal voltage first delay circuit.

Referring to FIG. 7, which is a block diagram of a conventional semiconductor integrated circuit device having a plurality of internal voltage down converters for generating a plurality of internal voltages, the conventional semiconductor integrated circuit device is controlled by a reference voltage VR1 and externally controlled. A step-down circuit 1 that steps down the power supply Vcc to generate a predetermined internal voltage VI1;
A step-down circuit 2 controlled by a reference voltage VR2 to step down an external power supply Vcc to generate a predetermined internal voltage VI2.

The step-down circuit 1 has a P-type MOS transistor P11 having a source connected to a power supply Vcc and outputting an internal voltage VI1 from a drain, a reference voltage VR1 supplied to an inverting input terminal, and an internal voltage VI1 supplied to a positive input terminal. An operational amplifier (op-amp) 11 that supplies a difference voltage signal D1 between the receiving reference voltage VR1 and the internal voltage VI1 to the gate of the transistor P11.

The step-down circuit 2 has a P-type MOS transistor P21 having a source connected to a power supply Vcc and outputting an internal voltage VI2 from a drain, a reference voltage VR2 supplied to an inverting input terminal, and an internal voltage VI2 supplied to a positive input terminal. An operational amplifier 21 is provided for supplying a difference voltage signal D2 between the receiving reference voltage VR2 and the internal voltage VI2 to the gate of the transistor P21.

Here, assuming that the reference voltage VR1 <VR2 and the difference voltage signal D1 D2, the obtained internal voltage VI1
<VI2.

However, in such a semiconductor integrated circuit device having a plurality of stepped-down internal voltages, the influence of noise in the internal step-down circuit is a serious problem. That is, the noise in the step-down circuit prevents the normal operation of the operational amplifiers 11 and 21 and the like, and the desired internal voltages VI1 and VI2 are also changed to abnormal values by setting the output difference voltages D1 and D2 to abnormal values.

Furthermore, since these step-down circuits 1 and 2 use a common external power supply Vcc, in the worst case, the output internal voltage VI1 becomes larger than VI2 due to the abnormalities of the difference voltages D1 and D2 due to noise in the step-down circuit. Inversion of the voltage level occurs. As a result, a circuit operation failure occurs.

One of the reasons is that P
The internal voltage VI depends on the gate control signals of the MOS transistors P11 and P12, that is, the difference voltage signals D1 and D2.
1, VI2 are Vcc ≧ VI1 ≧ VR1 and Vcc ≧ V
This is because a voltage value in which I2 ≧ VR2 and its variation range overlap can be obtained.

An example of the above-mentioned circuit operation failure is a latch-up phenomenon due to a parasitic bipolar element described below.

FIG. 8 is a sectional view showing an example of a vertical sectional structure of the gate of the P-type MOS transistor P72 among the MOS transistors constituting the second delay circuit shown in FIG. 6B. Then, the P + diffusion layer 91 at the source portion of the P-type MOS transistor, the N-type well region 93 forming the substrate of the P-type MOS transistor, and the P-type substrate 94 serving as a bulk substrate to which the bias VBB is applied
Thereby, the parasitic PNP biboler element 96 is configured. The gate electrode 90 is supplied with an input signal Vin, an internal voltage VI1 via an N + diffusion layer 92, and an internal voltage VI2 via a P + diffusion layer 91, respectively. The P + diffusion layer 95 constitutes a drain and outputs an output signal to the next stage gate.

During normal operation, that is, VI1>VI2> V
In the case of BB, the P + diffusion layer 91 and the N-type well region 93
A reverse bias is applied between the N-type well region 93 and the P-type substrate 94, and the parasitic PNP bipolar element 96 is in an off state. However, the internal voltages VI1, V1
Inversion of the voltage level occurs in I2, and VI2>VI1> VB
When it becomes B, the bias between the P + diffusion layer 91 and the N-type well region 93 becomes forward, and the N-type well region 93
Current flows from the P + diffusion layer 91 to turn on the parasitic PNP bipolar transistor 96. That is, the internal voltage V
A through current flows between I2 and the bias voltage VBB, and a latch-up state occurs, causing a circuit operation failure.

[0019]

The above-mentioned conventional semiconductor integrated circuit device is configured so that a single external power supply voltage is stepped down by an independent step-down circuit to generate a desired internal voltage. If the operation of each step-down circuit becomes abnormal, the output internal voltage can take a voltage value that overlaps each other as an abnormal value range, and in the worst case, the voltage value reverses, and the cause of the malfunction of each circuit of the load There was a disadvantage that it becomes.

An object of the present invention is to provide a highly reliable semiconductor integrated circuit device which prevents inversion between internal voltage values of internal voltages output from respective step-down circuits due to noise or the like.

[0021]

According to the semiconductor integrated circuit device of the present invention, the power supply voltage is stepped down to a first voltage lower than the power supply voltage.
First and second step-down circuits for respectively generating a first internal power supply of a first voltage and a second internal power supply of a second voltage lower than the first voltage are provided on a semiconductor chip; In the semiconductor integrated circuit device supplying the two power supplies to the corresponding internal circuits, the second step-down circuit steps down the first internal power supply to generate the second internal power supply. Things.

[0022]

FIG. 1 is a block diagram showing a first embodiment of the present invention, in which constituent elements common to those in FIG. The semiconductor integrated circuit device according to the present embodiment shown in this figure includes a step-down circuit 2 controlled by a common reference voltage VR1 and a step-down circuit 2 which steps down an external power supply Vcc to generate a predetermined internal voltage VI1. And a step-down circuit 2A controlled by the reference voltage VR2 to step down the internal power supply VI1 to generate a predetermined internal voltage VI2.

The step-down circuit 1 comprises a P-type MOS transistor P11 having a common source connected to a power supply Vcc and outputting an internal voltage VI1 from a drain, and a reference voltage VR1 supplied to an inverting input terminal and an internal voltage supplied to a positive input terminal. An operational amplifier 11 that receives the supply of VI1 and supplies a difference voltage signal D1 between the reference voltage VR1 and the internal voltage VI1 to the gate of the transistor P11.

The step-down circuit 2A receives a supply of the internal voltage VI1 of the output of the step-down circuit 1 at the source and outputs the internal voltage VI2 from the drain, and a reference voltage VR2 lower than the reference voltage VR1 at the inverting input terminal. And an operational amplifier 21 receiving the supply of the internal voltage VI2 at the positive input terminal thereof and supplying a difference voltage signal D2 between the reference voltage VR2 and the internal voltage VI2 to the gate of the transistor P21.

Next, the operation of the present embodiment will be described with reference to FIG. 1. First, in a normal state, the same operation as that of the conventional circuit is performed, and each of the step-down circuits 1 and 2A has a normal internal voltage VI1. , VI2. Next, the step-down circuits 1 and 2A operate abnormally due to noise or the like, and the internal voltage VI
1 and VI2 fluctuate, the step-down circuit 2A is configured to step down the internal voltage VI1.
I2 cannot exceed internal voltage VI1. That is, in the worst case, VI2 = VI1, and no reversal occurs between the internal voltages.

Next, referring to FIG. 2, which shows a second embodiment of the present invention, in which constituent elements common to FIG. The present embodiment is different from the above-described first embodiment in that, instead of the step-down circuit 2A, a P-type MOS transistor P21 common to the step-down circuit 2A and an operational amplifier 21 and the supply of a control signal φ In response to the internal voltage VI1 as the operating power supply, the internal voltage VI2 and the transistor P2
A step-down circuit 2B having a switch circuit 22 for switching the supply to one of the sources.

The switch circuit 22 is connected between the internal voltage VI1 and the source of the transistor P21 and receives a control signal φ
In response to the supply of the internal voltage VI1, the switching transistor M22 for supplying the internal voltage VI1 to the source of the transistor P21, the inverter I21 for inverting the control signal φ and outputting the inverted control signal φB, and one end connected to the internal voltage VI1 A switching transistor M23 having an end connected to the internal voltage VI2 and conducting in response to the supply of the inversion control signal φB.

Next, the operation of the present embodiment will be described with reference to FIG. 2. In the first embodiment, the load capacity of the output internal voltage VI2 of the step-down circuit 2A is equal to that of the step-down circuit 2A. Since the battery is charged by the internal voltage VI1, which is the operating power supply, the charging time is longer than in the conventional case where the external power supply Vcc is used. The step-down circuit 2B characterizing the present embodiment realizes a reduction in charging time of the output internal voltage VI2 to the load capacitance.

First, in response to the supply of the power supply Vcc, the step-down circuit 1 starts operating, and at the same time, the control signal φ goes to the H level. In response to the H level of the control signal φ, the switch circuit 22 of the step-down circuit 2B The transistor M22 turns off, and the transistor M23 turns on in response to the L level of the inversion control signal φB. Therefore, during this period, each load capacitance of the step-down circuits 1 and 2B is charged by the output internal voltage VI1 of the step-down circuit 1.

Next, after a predetermined time has elapsed under the condition that the voltage value of the internal voltage VI2 is equal to or lower than the reference voltage VR2, the control signal φ changes from the H level to the L level, and this control signal φ
Turns on in response to the L level of the transistor M2, and the transistor M2 responds to the H level of the inversion control signal φB.
3 turns off. Therefore, during this period, the same operation as in the first embodiment is performed, and the load capacity of the step-down circuit 1 is charged by the internal voltage VI1, and the load capacity of the step-down circuit 2B is charged by the internal voltage VI2.

As described above, when the step-down circuit is initially operated, the load capacitance of the step-down circuit 2B is charged by using the step-down circuit 1 using the external power supply Vcc as an operation power supply, thereby making it possible to reduce the internal voltage as compared with the first embodiment. The charging time to the load capacity of VI2 can be shortened.

Next, a third embodiment of the present invention will be described with reference to FIG. 3 in which constituent elements common to those in FIG. The difference of the present embodiment from the first embodiment is that the step-down circuit 3 which generates the predetermined internal voltage VI3 by stepping down the internal power supply VI1 controlled by the reference voltage VR3 in addition to the step-down circuit 2A is provided. It is to prepare further.

The relationship between the step-down circuit 1 and the step-down circuits 2A and 3 is as follows.
This is the same as the first embodiment, and uses the output internal voltage VI1 of the step-down circuit 1 as an operation power supply.

Next, a fourth embodiment of the present invention will be described with reference to FIG. 4, in which constituent elements common to those in FIG. This embodiment is different from the above-described first embodiment in that a reference voltage V common to the step-down circuit 2A is added to the step-down circuit 2A.
The circuit further includes a step-down circuit 3A controlled by R2 to step down internal power supply VI1 to generate a predetermined internal voltage VI2.

According to the present embodiment, the same internal voltage VI2 can be supplied independently to two loads, and the mutual noise interference between these load circuits can be suppressed.

Next, referring to FIG. 5, which shows a fifth embodiment of the present invention in which components common to those in FIG. This embodiment is different from the above-described third embodiment in that a step-down circuit 3B controlled by a reference voltage VR3 instead of the step-down circuit 3 to step down an internal power supply VI2 to generate a predetermined internal voltage VI3. It is to have.

In the present embodiment, the internal voltage VI2 is generated from the internal voltage VI1, and the internal voltage VI3 is generated from the internal voltage VI2.

[0038]

As described above, the semiconductor integrated circuit device of the present invention reduces the high potential internal voltage to generate the low potential internal potential, thereby essentially inverting the potential of the high and low internal voltages. This has the effect of being able to be removed altogether.

In the case where the margin between the voltage values of the plurality of internal voltages is reduced by lowering the voltage of the external power supply, the order of the plurality of internal voltages can be determined. There is an effect that values can be easily separated.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of a semiconductor integrated circuit device of the present invention.

FIG. 2 is a block diagram showing a second embodiment of the semiconductor integrated circuit device of the present invention.

FIG. 3 is a block diagram showing a third embodiment of the semiconductor integrated circuit device of the present invention.

FIG. 4 is a block diagram showing a fourth embodiment of the semiconductor integrated circuit device of the present invention.

FIG. 5 is a block diagram showing a fifth embodiment of the semiconductor integrated circuit device of the present invention.

FIG. 6 is a circuit diagram showing an example of a single power supply and two power supply delay circuits, respectively.

FIG. 7 is a block diagram illustrating an example of a conventional semiconductor integrated circuit device.

FIG. 8 is a cross-sectional view schematically showing a structure of a P-type MOS transistor constituting the delay circuit of FIG. 6B.

[Explanation of symbols]

1, 2, 2A, 2B, 3, 3A Step-down circuit 11, 21 Operational amplifier 22 Switch circuit 91, 95 P + diffusion layer 92 N + diffusion layer 93 N-type well region 94 P-type substrate 96 Parasitic PNP bipolar element C71 Capacitor M22, M23, N71, P11, P21, P71, P
72 transistors

Claims (5)

[Claims] A first internal power supply having a first voltage lower than the power supply voltage and a second internal power supply having a second voltage lower than the first voltage. And a second step-down circuit provided on a semiconductor chip and supplying the first and second power supplies to corresponding internal circuits, respectively, wherein the second step-down circuit includes the first internal power supply. Wherein the second internal power supply is generated by stepping down the voltage. 2. The semiconductor integrated circuit device according to claim 1, wherein said power supply voltage is an external power supply voltage supplied from outside. 3. The second internal power supply is stepped down to generate the second internal power supply.
2. The semiconductor integrated circuit device according to claim 1, further comprising a third internal power supply for generating a third voltage lower than the third voltage. 4. The first voltage step-down circuit receives a first reference voltage supplied to a first input terminal and feeds back the first internal voltage to a second input terminal to produce a first differential voltage signal. And a first transistor for receiving the supply of the power supply voltage at the source and outputting the first internal power supply from the drain in response to the supply of the first differential voltage signal to the gate The second step-down circuit receives a supply of a second reference voltage at a first input terminal, feeds back the second internal voltage to a second input terminal, and outputs a second differential voltage signal A second operational amplifier,
A second transistor that receives the supply of the first internal power supply to a source and outputs the second internal power supply from a drain in response to the supply of the second differential voltage signal to a gate. The semiconductor integrated circuit device according to claim 1. 5. The second step-down circuit selectively connects the first internal power supply to one of the second power supply and the source of the second transistor in response to supply of a control signal. 5. The semiconductor integrated circuit device according to claim 4, further comprising switch means for supplying.