JP3096711B2 - Output voltage control device for charge pump - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an output voltage control device for a charge pump that operates based on a clock signal.
There is no particular limitation as long as it uses a charge pump, and it can be applied to various devices.

[0002]

2. Description of the Related Art As an output voltage control method of a charge pump operating based on a clock signal, as shown in FIG. 3, two clocks having inverted phases are provided between a clock signal generator 1 and a charge pump 2. The output terminals of the inverters 91A and 91B are connected to the capacitors 21 and 22 in the charge pump 2, and the output terminals of the capacitors 21 and 22; A method is known in which a clamp device 92 is connected to the output terminal of the charge pump 2 and the output voltage of the charge pump 2 is controlled to a constant value by a voltage drop caused by the clamp device 92. Further, as shown in FIG. 4, a method of providing a frequency divider 93 between the clock signal generator 1 and the charge pump 2 and controlling the output voltage of the charge pump 2 by changing the frequency of the clock signal is known. Are known.

[0003]

However, in the method shown in FIG. 3, in order to variably control the output voltage during the operation of the charge pump 2, the clamp device 9 is required.
Although it is necessary to change the number of elements constituting the second element, in that case, it is necessary to provide a separate level shifter after the charge pump 2, and there is a problem that the layout area of the elements becomes large. Further, in the method of FIG. 4, it is necessary to use the frequency divider 93 to change the frequency f of the clock signal, but the frequency divider 93 uses f / 2, f / 4,
Since the frequency is divided by f / 8, there is a problem that the output voltage of the charge pump 2 is inappropriate if it is desired to be variably controlled.

An object of the present invention is to provide a charge pump output voltage control device capable of minutely variably controlling the output voltage of the charge pump without increasing the layout area of the elements.

[0005]

According to the present invention, there is provided an apparatus for controlling an output voltage of a charge pump which operates based on a clock signal, comprising a series circuit of a first capacitor and a second capacitor. A generator, an inverter for inverting the clock signal from the clock signal generator, and an intervening unit between the output of the inverter and one end of the series circuit, which are input to the charge pump. A first control unit for changing the amplitude of the clock signal;
A second control unit interposed between the input side of the inverter and the other end of the series circuit for changing the amplitude of a clock signal input to the charge pump; The first and second control units are provided between power supply voltages having different voltages, a plurality of voltage drop transistors for setting the amplitude of the clock signal according to the voltage drop, and a voltage drop among these transistors. And a plurality of signal input terminals for selecting a transistor that contributes to the selected transistor. A transistor is selected by a combination of logic values that are selection signals input to the plurality of signal input terminals, and a voltage drop of the selected transistor is provided. An output voltage control device for a charge pump, wherein a clock signal having an amplitude corresponding to a minute is input to a charge pump. A method for controlling the output voltage of a charge pump operating based on a clock signal is characterized in that the output voltage of the charge pump is variably controlled by variably controlling the amplitude of a clock signal input to the charge pump.

[0006]

When the amplitude of the clock signal input to the charge pump is changed, the boosting efficiency of the charge pump changes, so that the output voltage of the charge pump changes. That is,
When the amplitude of the clock signal input to the charge pump is large, the output voltage of the charge pump increases, and when the amplitude of the clock signal is small, the output voltage of the charge pump decreases. Accordingly, the output voltage of the charge pump can be minutely variably controlled by minutely changing the amplitude of the clock signal.

[0007]

Embodiments of the present invention will be described below. FIG. 1 is a block circuit diagram showing an embodiment of the control device of the present invention.
1 is a clock signal generator, 2 is a charge pump, and 3 is a clock signal controller. The clock signal control unit 3 is interposed between the clock signal generation unit 1 and the charge pump 2, and includes a first control unit 3A and a second control unit 3B.
The output terminal of the first control unit 3A is connected to one capacitor 21 constituting the charge pump 2, and the second control unit 3B
Is connected to the other capacitor 22 of the charge pump 2. First control unit 3A and second control unit
Control section 3B variably controls the amplitude of the clock signal from the clock signal generating section 1. Clock signals having the same amplitude but inverted phases are generated from their output terminals. One clock signal is supplied to two capacitors 21 and 22 of the charge pump 2, respectively.

According to the above-described control device, the amplitudes of the two clock signals, which are supplied to the two capacitors 21 and 22 constituting the charge pump 2 and whose phases are inverted, are respectively adjusted by the first control unit 3A and the second control unit 3A. Control unit 3
Since the variable control is performed by B, the boosting efficiency of the charge pump 2 changes, and the output voltage at the output terminal 23 of the charge pump 2 can be variably controlled. That is, when the amplitude of the clock signal input to the charge pump 2 is large, the output voltage of the charge pump 2 increases, and when the amplitude of the clock signal is small, the output voltage of the charge pump 2 decreases. As described above, the output voltage of the charge pump 2 can be minutely variably controlled by minutely changing the amplitude of the clock signal supplied to the charge pump 2 by the clock signal control unit 3 so as to be variably controlled. Unlike the conventional method shown, it is not necessary to separately provide a level shifter for changing the number of elements constituting the clamp device, and the problem that the layout area of the elements becomes large does not occur. Further, as compared with the case where the frequency divider 4 is used as in the conventional method shown in FIG.
Can be finely variably controlled.

FIG. 2 is a block circuit diagram showing an embodiment of the control device according to the present invention, wherein 1 is a clock signal generator, 2 is a charge pump, and 3 is a clock signal controller. The clock signal control unit 3 includes a first control unit 3A and a second control unit 3
B. The first control unit 3A has an inverter 31A connected to the clock signal generation unit 1, and the phase of the clock signal is inverted by the inverter 31A. The output terminal of the inverter 31A has four NOR circuits 41A,
One input terminals of 42A, 43A and 44A are respectively connected, and the selected input signals S1, S2, S3 and S4 are input to the other input terminals of these NOR circuits, respectively. The power supply voltage Vdd is connected to, for example, a switching element 51A made of a P-type FET that conducts when the input of the gate is at the L level. A clock signal from the clock signal generator 1 is input to the gate of the switching element 51A. Is done. The source of the switching element 51A is connected to a first selection switching element 61A made of, for example, a P-type FET, and its source is further connected in series with four voltage drop elements 71A, 72A made of, for example, four N-type FETs. 73A and 74A are connected.

A second select switching element 62A is connected between the source of the switching element 51A and the drain of the voltage dropping element 71A, and the gate thereof is connected to a NOR gate.
It is connected to the output terminal of the circuit 42A. A third select switching element 63A is connected between the source of the switching element 51A and the drain of the voltage dropping element 72A, and the gate thereof is connected to the output terminal of the NOR circuit 43A. The fourth select switching element 64A is connected between the source of the switching element 51A and the drain of the voltage dropping element 74A, and the gate thereof is connected to the NO.
It is connected to the output terminal of R circuit 44A. An input terminal 32A is connected to an output terminal of the clock signal generator 1. An output terminal 33A of the first control unit 3A is connected to one capacitor 21 of the charge pump 2.

The second control unit 3B includes an inverter 31 connected to the output terminal of the inverter 31A of the first control unit 3A.
B has the same configuration as that of the first control section 3A, and the corresponding elements are denoted by the reference character B. The output terminal 33B of the second control unit 3B is connected to the other capacitor 22 of the charge pump 2. Reference numeral 8 denotes a protection circuit including a clamp device, which is added as necessary to protect from a high voltage, and is not an essential component in the present invention.

According to the control device having the above configuration, the output voltage of the charge pump 2 is variably controlled as follows.
In order to make the description easy to understand, the power supply voltage Vdd
Is 5 V, for example, and the voltage drop for one voltage drop element is 1 V, for example. First, when the select signal S1 is selected and set only to the L level, only the first select switching element 61A is controlled to be turned on / off by the clock signal from the clock signal generator 1, and the other select signals are selected. Switching elements 62A, 63A, 64A
Are turned off, the four voltage drop elements 71A and 72 are output from the output terminal 32A of the first control unit 3A.
A, a clock signal having a small amplitude by the total voltage drop (4 V) of 73A, 74A is output, and the second control unit 3B
From the output terminal 33B, four voltage drop elements 71B,
A clock signal whose amplitude is small and whose phase is inverted by the total voltage drop (4 V) of 72B, 73B and 74B is output. When these two clock signals are respectively supplied to the two capacitors 21 and 22 of the charge pump 2, the output voltage at the output terminal 23 of the charge pump 2 is 5V at the H level, 4V at the L level, and 1V at the amplitude. Voltage.

Next, when the select signal S2 is selected and only this is set to L level, the clock signal generator 1
The ON / OFF control of only the second selection switching element 62A is performed by the clock signal, and the other selection switching elements 61A, 63A, and 64A are all turned off. Therefore, the output terminal 33A of the first control unit 3A.
Outputs a clock signal having a small amplitude by the total voltage drop (3 V) of the three voltage drop elements 72A, 73A, 74A, and outputs three voltage drop elements from the output terminal 33B of the second control unit 3B. A clock signal whose amplitude is small and whose phase is inverted by the total voltage drop (3 V) of 72B, 73B and 74B is output. These two clock signals are the two capacitors 21 and 2 of the charge pump 2.
2, the output voltage at the output terminal 23 of the charge pump 2 is a voltage having an H level of 5 V, an L level of 3 V, and an amplitude of 2 V.

Further, when the select signal S3 is selected and set only to the L level, only the third select switching element 63A is controlled on / off by the clock signal from the clock signal generator 1, and All of the selection switching elements 61A, 62A, 64A are turned off, so that the output terminal 33 of the first control unit 3A is turned off.
A outputs a clock signal having a small amplitude by the total voltage drop (2 V) of the two voltage drop elements 73A and 74A, and outputs two voltage drop elements 73B from the output terminal 33B of the second control unit 3B. , 74B are output with a clock signal whose amplitude is small and whose phase is inverted by the total voltage drop (2 V). When these two clock signals are respectively supplied to the two capacitors 21 and 22 of the charge pump 2, the output voltage at the output terminal 23 of the charge pump 2 is 5V at the H level, 2V at the L level, and 3V at the amplitude. Voltage.

When the select signal S4 is selected and only the select signal S4 is set to the L level, the clock signal generator 1
The ON / OFF control of only the fourth select switching element 64A is performed by the clock signal, and the other select switching elements 61A, 62A, 63A are all turned off, so that the output terminal 33A of the first control unit 3A is turned off.
Outputs a clock signal of the same amplitude that does not cause any voltage drop by the voltage drop element.
From the output terminal 33B of B, a clock signal whose phase is inverted with the same amplitude is output without any voltage drop by the voltage drop element. When these two clock signals are respectively supplied to the two capacitors 21 and 22 of the charge pump 2, the output terminal 23 of the charge pump 2
Output voltage at H level is 5V and L level is 0V
Thus, a voltage having an amplitude of 5 V is obtained.

According to the above control device, the amplitudes of the two clock signals whose phases are inverted and supplied to the two capacitors 21 and 22 constituting the charge pump 2 are respectively adjusted by the first control unit 3A and the second control unit 3A. Control unit 3
B can be variably controlled in four stages.
Of the charge pump 2 can be variably controlled in four stages. Further, since the configuration is such that the clock signal control unit 3 is interposed between the clock signal generation unit 1 and the charge pump 2, the layout area of the element is increased as compared with the conventional configuration as shown in FIG. Does not occur.

The present invention is not limited to the above embodiment, but can be variously modified. In particular, since the configuration of the clock signal control unit 3 can adopt various configurations,
It is not limited to the configuration of FIG. For example, the control device shown in FIG. 2 has a configuration in which the output voltage of the charge pump 2 is variably controlled in four stages. However, a circuit element having one set of a NOR circuit, a select signal, a select switching element, and a voltage drop element is further multi-staged. If provided, the output voltage of the charge pump 2 can be further variably and finely controlled in more stages. Further, the first control unit 3 shown in FIG.
A, voltage drop elements 71A, 72A, 73A,
The position where 74A is provided may be changed between the switching element 51A and the first selection switching element 61A, and the second control unit 3B may be changed in the same manner. The effect is achieved. FIG.
Then, the voltage drop element 71A in the first control unit 3A,
Although 72A, 73A, and 74A are connected in series, they are connected in parallel to the selection switching elements using voltage drop elements having different threshold voltages and on-resistances, and the second control unit 3B is similarly changed. In this case, the same operation and effect as those of the control device of FIG. 2 can be obtained. Further, the types of elements constituting the voltage dropping element 71A and the like, such as the switching element 51 and the selection switching element 61A, are not particularly limited.

[0018]

According to the control device of the present invention, the clock signal control section is provided between the clock signal generation section and the charge pump to variably control the amplitude of the clock signal from the clock signal generation section. The output voltage of the pump can be minutely variably controlled, and the layout area of the elements does not increase.

[Brief description of the drawings]

FIG. 1 is a block circuit diagram showing an embodiment of a control device according to the present invention.

FIG. 2 is a block circuit diagram showing an embodiment of a control device according to the present invention.

FIG. 3 is a block circuit diagram showing an example of a conventional control device.

FIG. 4 is a block circuit diagram showing another example of a conventional control device.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Clock signal generation part 2 Charge pump 21, 22 Capacitor 3 Clock signal control part 3A 1st control part 3B 2nd control part 31A, 31B Inverter 41A-44A, 41B-44B NOR circuit 51A, 51B Switching element 61A-64A , 61B-64B Switching element for selection 71A-74A, 71B-74B Element for voltage drop 8 Clamp device 91A, 91B Inverter 92 Clamp device 93 Divider

Claims (1)

(57) [Claims] 1. A first capacitor and a second capacitor
That operates based on a clock signal.
In a device for controlling an output voltage of a charge pump, a clock signal generator and a clock signal generator.
An inverter for inverting the clock signal, and the inverter
Interposed between the output side of the series circuit and one end of the series circuit,
Change the amplitude of the clock signal input to the charge pump
A first control unit for controlling the input side of the inverter
Charge pump interposed between the other end of the series circuit
To change the amplitude of the clock signal input to the
And a control unit, wherein the first and second control units have different power supply voltages.
Clock signal oscillation due to the voltage drop.
Multiple voltage drop transistors to set width
And the transistors that contribute to the voltage drop in these transistors
A plurality of signal inputs for selecting transistors.
A selection signal input to the plurality of signal input terminals.
The transistor is selected according to the combination of logical values,
Has an amplitude corresponding to the voltage drop of the selected transistor.
Clock signal is input to the charge pump.
The output voltage control device of the charge pump.